[LSR][NFC] don't collect chains when isNumRegsMajorCostOfLSR is false

[shchenz]

Summary

This is an NFC patch and it only concerns compiling time on targets where isNumRegsMajorCostOfLSR is overloaded. For now, it is only for PowerPC target.

Because all the collected chains will be marked as not profitable in isProfitableChain when isNumRegsMajorCostOfLSR returns false, we don't need to waste time to collect the chain at the very beginning.

This patch just reverts the change in function isProfitableChain in https://reviews.llvm.org/D89665 and moves the newly added hook check at the very beginning.

We may get a potential issue if another hook isProfitableLSRChainElement returns true for some chain element on targets that isNumRegsMajorCostOfLSR returns false, but for now I can not see any target do that. So I guess it should be ok now?

[samparker]

Okay, fair enough.

llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp

if (isa<PHINode>(Chain.tailUserInst())
       && SE.getSCEV(Chain.tailUserInst()) == Chain.Incs[0].IncExpr) {
     --cost;
   }
   const SCEV *LastIncExpr = nullptr;
   unsigned NumConstIncrements = 0;
   unsigned NumVarIncrements = 0;
   unsigned NumReusedIncrements = 0;
 
-  // If any LSRUse in the chain is marked as profitable by target, mark this
-  // chain as profitable.
-  for (const IVInc &Inc : Chain.Incs)
-    if (TTI.isProfitableLSRChainElement(Inc.UserInst))
-      return true;
+  if (TTI.isProfitableLSRChainElement(Chain.Incs[0].UserInst))
 
-  // If number of registers is not the major cost, we cannot benefit from this
-  // profitable chain which is based on number of registers.
-  // FIXME: add profitable chain optimization for other kinds major cost, for
-  // example number of instructions.
-  if (!TTI.isNumRegsMajorCostOfLSR())
-    return false;
-
   for (const IVInc &Inc : Chain) {
+    if (TTI.isProfitableLSRChainElement(Inc.UserInst))
+      return true;
     if (Inc.IncExpr->isZero())
       continue;
 
     // Incrementing by zero or some constant is neutral. We assume constants can
     // be folded into an addressing mode or an add's immediate operand.
     if (isa<SCEVConstant>(Inc.IncExpr)) {
       ++NumConstIncrements;
       continue;
#endif // DEBUG
 
   // Skip nested loops until we can model them better with formulae.
   if (!L->isInnermost()) {
     LLVM_DEBUG(dbgs() << "LSR skipping outer loop " << *L << "\n");
     return;
   }
 
   // Start collecting data and preparing for the solver.
+  // If number of registers is not the major cost, we cannot benefit from the
+  // current profitable chain optimization which is based on number of
+  // registers.
+  // FIXME: add profitable chain optimization for other kinds major cost, for
+  // example number of instructions.
+  if (TTI.isNumRegsMajorCostOfLSR() || StressIVChain)
     CollectChains();
   CollectInterestingTypesAndFactors();
   CollectFixupsAndInitialFormulae();
   CollectLoopInvariantFixupsAndFormulae();
 
   if (Uses.empty())
     return;
 
   LLVM_DEBUG(dbgs() << "LSR found " << Uses.size() << " uses:\n";