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Differential D91163

[SelectionDAG] fminnum should be a binary operator
ClosedPublic

Authored by shchenz on Nov 10 2020, 7:04 AM.

Details

Reviewers
craig.topper
spatel
jsji
steven.zhang
Commits
rG09e34048bf7e: [SelectionDAG] fminnum should be a binary operator
Summary

This is a typo fix.

fminnum is a binary operator instead of a unary operator.

Diff Detail

Event Timeline

shchenz created this revision.Nov 10 2020, 7:04 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 10 2020, 7:04 AM
Herald added subscribers: llvm-commits, ecnelises, hiraditya, nemanjai. · View Herald Transcript
shchenz requested review of this revision.Nov 10 2020, 7:04 AM
Harbormaster completed remote builds in B78290: Diff 304176.Nov 10 2020, 7:04 AM
craig.topper accepted this revision.Nov 10 2020, 9:30 AM

LGTM

This revision is now accepted and ready to land.Nov 10 2020, 9:30 AM
This revision was landed with ongoing or failed builds.Nov 11 2020, 12:41 AM
Closed by commit rG09e34048bf7e: [SelectionDAG] fminnum should be a binary operator (authored by shchenz). · Explain Why
This revision was automatically updated to reflect the committed changes.
shchenz added a commit: rG09e34048bf7e: [SelectionDAG] fminnum should be a binary operator.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
2 lines
test/
CodeGen/
PowerPC/
98 lines

Diff 304420

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Show First 20 Lines • Show All 1,288 Lines • ▼ Show 20 Linesvoid DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
// Lo = Hi==fabs(Hi) ? Lo : -Lo; // Lo = Hi==fabs(Hi) ? Lo : -Lo;
Lo = DAG.getSelectCC(dl, Tmp, Hi, Lo, Lo = DAG.getSelectCC(dl, Tmp, Hi, Lo,
DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo),
ISD::SETEQ); ISD::SETEQ);
} }
void DAGTypeLegalizer::ExpandFloatRes_FMINNUM(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandFloatRes_FMINNUM(SDNode *N, SDValue &Lo,
SDValue &Hi) { SDValue &Hi) {
ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
RTLIB::FMIN_F32, RTLIB::FMIN_F64, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
RTLIB::FMIN_F80, RTLIB::FMIN_F128, RTLIB::FMIN_F80, RTLIB::FMIN_F128,
RTLIB::FMIN_PPCF128), Lo, Hi); RTLIB::FMIN_PPCF128), Lo, Hi);
} }
void DAGTypeLegalizer::ExpandFloatRes_FMAXNUM(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandFloatRes_FMAXNUM(SDNode *N, SDValue &Lo,
SDValue &Hi) { SDValue &Hi) {
ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0), ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
▲ Show 20 Lines • Show All 1,678 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/fminnum.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
ret double %z ret double %z
} }
define ppc_fp128 @test_fminl(ppc_fp128 %x, ppc_fp128 %y) { define ppc_fp128 @test_fminl(ppc_fp128 %x, ppc_fp128 %y) {
; CHECK-LABEL: test_fminl: ; CHECK-LABEL: test_fminl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1) ; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -80(1) ; CHECK-NEXT: stwu 1, -112(1)
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: stfd 1, 40(1) ; CHECK-NEXT: stfd 1, 40(1)
; CHECK-NEXT: lwz 3, 44(1) ; CHECK-NEXT: lwz 3, 44(1)
; CHECK-NEXT: stfd 2, 32(1) ; CHECK-NEXT: stfd 2, 32(1)
; CHECK-NEXT: stw 3, 60(1) ; CHECK-NEXT: stw 3, 60(1)
; CHECK-NEXT: lwz 3, 40(1) ; CHECK-NEXT: lwz 3, 40(1)
; CHECK-NEXT: stfd 3, 72(1)
; CHECK-NEXT: stw 3, 56(1) ; CHECK-NEXT: stw 3, 56(1)
; CHECK-NEXT: lwz 3, 36(1) ; CHECK-NEXT: lwz 3, 36(1)
; CHECK-NEXT: lfd 1, 56(1) ; CHECK-NEXT: stfd 4, 64(1)
; CHECK-NEXT: stw 3, 52(1) ; CHECK-NEXT: stw 3, 52(1)
; CHECK-NEXT: lwz 3, 32(1) ; CHECK-NEXT: lwz 3, 32(1)
; CHECK-NEXT: lfd 1, 56(1)
; CHECK-NEXT: stw 3, 48(1) ; CHECK-NEXT: stw 3, 48(1)
; CHECK-NEXT: lwz 3, 76(1)
; CHECK-NEXT: lfd 2, 48(1) ; CHECK-NEXT: lfd 2, 48(1)
; CHECK-NEXT: stw 3, 92(1)
; CHECK-NEXT: lwz 3, 72(1)
; CHECK-NEXT: stw 3, 88(1)
; CHECK-NEXT: lwz 3, 68(1)
; CHECK-NEXT: lfd 3, 88(1)
; CHECK-NEXT: stw 3, 84(1)
; CHECK-NEXT: lwz 3, 64(1)
; CHECK-NEXT: stw 3, 80(1)
; CHECK-NEXT: lfd 4, 80(1)
; CHECK-NEXT: bl fminl ; CHECK-NEXT: bl fminl
; CHECK-NEXT: stfd 1, 16(1) ; CHECK-NEXT: stfd 1, 16(1)
; CHECK-NEXT: lwz 3, 20(1) ; CHECK-NEXT: lwz 3, 20(1)
; CHECK-NEXT: stfd 2, 24(1) ; CHECK-NEXT: stfd 2, 24(1)
; CHECK-NEXT: stw 3, 76(1) ; CHECK-NEXT: stw 3, 108(1)
; CHECK-NEXT: lwz 3, 16(1) ; CHECK-NEXT: lwz 3, 16(1)
; CHECK-NEXT: stw 3, 72(1) ; CHECK-NEXT: stw 3, 104(1)
; CHECK-NEXT: lwz 3, 28(1) ; CHECK-NEXT: lwz 3, 28(1)
; CHECK-NEXT: lfd 1, 72(1) ; CHECK-NEXT: lfd 1, 104(1)
; CHECK-NEXT: stw 3, 68(1) ; CHECK-NEXT: stw 3, 100(1)
; CHECK-NEXT: lwz 3, 24(1) ; CHECK-NEXT: lwz 3, 24(1)
; CHECK-NEXT: stw 3, 64(1) ; CHECK-NEXT: stw 3, 96(1)
; CHECK-NEXT: lfd 2, 64(1) ; CHECK-NEXT: lfd 2, 96(1)
; CHECK-NEXT: lwz 0, 84(1) ; CHECK-NEXT: lwz 0, 116(1)
; CHECK-NEXT: addi 1, 1, 80 ; CHECK-NEXT: addi 1, 1, 112
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%z = call ppc_fp128 @fminl(ppc_fp128 %x, ppc_fp128 %y) readnone %z = call ppc_fp128 @fminl(ppc_fp128 %x, ppc_fp128 %y) readnone
ret ppc_fp128 %z ret ppc_fp128 %z
} }
define float @test_intrinsic_fmin_f32(float %x, float %y) { define float @test_intrinsic_fmin_f32(float %x, float %y) {
; CHECK-LABEL: test_intrinsic_fmin_f32: ; CHECK-LABEL: test_intrinsic_fmin_f32:
Show All 29 Lines; CHECK-NEXT: blr
ret double %z ret double %z
} }
define ppc_fp128 @test_intrinsic_fmin_f128(ppc_fp128 %x, ppc_fp128 %y) { define ppc_fp128 @test_intrinsic_fmin_f128(ppc_fp128 %x, ppc_fp128 %y) {
; CHECK-LABEL: test_intrinsic_fmin_f128: ; CHECK-LABEL: test_intrinsic_fmin_f128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1) ; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -80(1) ; CHECK-NEXT: stwu 1, -112(1)
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: stfd 1, 40(1) ; CHECK-NEXT: stfd 1, 40(1)
; CHECK-NEXT: lwz 3, 44(1) ; CHECK-NEXT: lwz 3, 44(1)
; CHECK-NEXT: stfd 2, 32(1) ; CHECK-NEXT: stfd 2, 32(1)
; CHECK-NEXT: stw 3, 60(1) ; CHECK-NEXT: stw 3, 60(1)
; CHECK-NEXT: lwz 3, 40(1) ; CHECK-NEXT: lwz 3, 40(1)
; CHECK-NEXT: stfd 3, 72(1)
; CHECK-NEXT: stw 3, 56(1) ; CHECK-NEXT: stw 3, 56(1)
; CHECK-NEXT: lwz 3, 36(1) ; CHECK-NEXT: lwz 3, 36(1)
; CHECK-NEXT: lfd 1, 56(1) ; CHECK-NEXT: stfd 4, 64(1)
; CHECK-NEXT: stw 3, 52(1) ; CHECK-NEXT: stw 3, 52(1)
; CHECK-NEXT: lwz 3, 32(1) ; CHECK-NEXT: lwz 3, 32(1)
; CHECK-NEXT: lfd 1, 56(1)
; CHECK-NEXT: stw 3, 48(1) ; CHECK-NEXT: stw 3, 48(1)
; CHECK-NEXT: lwz 3, 76(1)
; CHECK-NEXT: lfd 2, 48(1) ; CHECK-NEXT: lfd 2, 48(1)
; CHECK-NEXT: stw 3, 92(1)
; CHECK-NEXT: lwz 3, 72(1)
; CHECK-NEXT: stw 3, 88(1)
; CHECK-NEXT: lwz 3, 68(1)
; CHECK-NEXT: lfd 3, 88(1)
; CHECK-NEXT: stw 3, 84(1)
; CHECK-NEXT: lwz 3, 64(1)
; CHECK-NEXT: stw 3, 80(1)
; CHECK-NEXT: lfd 4, 80(1)
; CHECK-NEXT: bl fminl ; CHECK-NEXT: bl fminl
; CHECK-NEXT: stfd 1, 16(1) ; CHECK-NEXT: stfd 1, 16(1)
; CHECK-NEXT: lwz 3, 20(1) ; CHECK-NEXT: lwz 3, 20(1)
; CHECK-NEXT: stfd 2, 24(1) ; CHECK-NEXT: stfd 2, 24(1)
; CHECK-NEXT: stw 3, 76(1) ; CHECK-NEXT: stw 3, 108(1)
; CHECK-NEXT: lwz 3, 16(1) ; CHECK-NEXT: lwz 3, 16(1)
; CHECK-NEXT: stw 3, 72(1) ; CHECK-NEXT: stw 3, 104(1)
; CHECK-NEXT: lwz 3, 28(1) ; CHECK-NEXT: lwz 3, 28(1)
; CHECK-NEXT: lfd 1, 72(1) ; CHECK-NEXT: lfd 1, 104(1)
; CHECK-NEXT: stw 3, 68(1) ; CHECK-NEXT: stw 3, 100(1)
; CHECK-NEXT: lwz 3, 24(1) ; CHECK-NEXT: lwz 3, 24(1)
; CHECK-NEXT: stw 3, 64(1) ; CHECK-NEXT: stw 3, 96(1)
; CHECK-NEXT: lfd 2, 64(1) ; CHECK-NEXT: lfd 2, 96(1)
; CHECK-NEXT: lwz 0, 84(1) ; CHECK-NEXT: lwz 0, 116(1)
; CHECK-NEXT: addi 1, 1, 80 ; CHECK-NEXT: addi 1, 1, 112
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%z = call ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %x, ppc_fp128 %y) readnone %z = call ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %x, ppc_fp128 %y) readnone
ret ppc_fp128 %z ret ppc_fp128 %z
} }
define <2 x float> @test_intrinsic_fminf_v2f32(<2 x float> %x, <2 x float> %y) { define <2 x float> @test_intrinsic_fminf_v2f32(<2 x float> %x, <2 x float> %y) {
; CHECK-LABEL: test_intrinsic_fminf_v2f32: ; CHECK-LABEL: test_intrinsic_fminf_v2f32:
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
ret <8 x float> %z ret <8 x float> %z
} }
define ppc_fp128 @fminnum_const(ppc_fp128 %0) { define ppc_fp128 @fminnum_const(ppc_fp128 %0) {
; CHECK-LABEL: fminnum_const: ; CHECK-LABEL: fminnum_const:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1) ; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -80(1) ; CHECK-NEXT: stwu 1, -96(1)
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: stfd 1, 40(1) ; CHECK-NEXT: stfd 1, 40(1)
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: stw 3, 76(1)
; CHECK-NEXT: lis 4, 16368
; CHECK-NEXT: stw 3, 68(1)
; CHECK-NEXT: stw 3, 64(1)
; CHECK-NEXT: lwz 3, 44(1) ; CHECK-NEXT: lwz 3, 44(1)
; CHECK-NEXT: stfd 2, 32(1) ; CHECK-NEXT: stfd 2, 32(1)
; CHECK-NEXT: stw 3, 60(1) ; CHECK-NEXT: stw 3, 60(1)
; CHECK-NEXT: lwz 3, 40(1) ; CHECK-NEXT: lwz 3, 40(1)
; CHECK-NEXT: stw 4, 72(1)
; CHECK-NEXT: stw 3, 56(1) ; CHECK-NEXT: stw 3, 56(1)
; CHECK-NEXT: lwz 3, 36(1) ; CHECK-NEXT: lwz 3, 36(1)
; CHECK-NEXT: lfd 1, 56(1) ; CHECK-NEXT: lfd 3, 72(1)
; CHECK-NEXT: stw 3, 52(1) ; CHECK-NEXT: stw 3, 52(1)
; CHECK-NEXT: lwz 3, 32(1) ; CHECK-NEXT: lwz 3, 32(1)
; CHECK-NEXT: lfd 4, 64(1)
; CHECK-NEXT: stw 3, 48(1) ; CHECK-NEXT: stw 3, 48(1)
; CHECK-NEXT: lfd 1, 56(1)
; CHECK-NEXT: lfd 2, 48(1) ; CHECK-NEXT: lfd 2, 48(1)
; CHECK-NEXT: bl fminl ; CHECK-NEXT: bl fminl
; CHECK-NEXT: stfd 1, 16(1) ; CHECK-NEXT: stfd 1, 16(1)
; CHECK-NEXT: lwz 3, 20(1) ; CHECK-NEXT: lwz 3, 20(1)
; CHECK-NEXT: stfd 2, 24(1) ; CHECK-NEXT: stfd 2, 24(1)
; CHECK-NEXT: stw 3, 76(1) ; CHECK-NEXT: stw 3, 92(1)
; CHECK-NEXT: lwz 3, 16(1) ; CHECK-NEXT: lwz 3, 16(1)
; CHECK-NEXT: stw 3, 72(1) ; CHECK-NEXT: stw 3, 88(1)
; CHECK-NEXT: lwz 3, 28(1) ; CHECK-NEXT: lwz 3, 28(1)
; CHECK-NEXT: lfd 1, 72(1) ; CHECK-NEXT: lfd 1, 88(1)
; CHECK-NEXT: stw 3, 68(1) ; CHECK-NEXT: stw 3, 84(1)
; CHECK-NEXT: lwz 3, 24(1) ; CHECK-NEXT: lwz 3, 24(1)
; CHECK-NEXT: stw 3, 64(1) ; CHECK-NEXT: stw 3, 80(1)
; CHECK-NEXT: lfd 2, 64(1) ; CHECK-NEXT: lfd 2, 80(1)
; CHECK-NEXT: lwz 0, 84(1) ; CHECK-NEXT: lwz 0, 100(1)
; CHECK-NEXT: addi 1, 1, 80 ; CHECK-NEXT: addi 1, 1, 96
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%2 = tail call fast ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %0, ppc_fp128 0xM3FF00000000000000000000000000000) %2 = tail call fast ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %0, ppc_fp128 0xM3FF00000000000000000000000000000)
ret ppc_fp128 %2 ret ppc_fp128 %2
} }