[GlobalISel] Add combine for (x | mask) -> x when (x | mask) == x

[mbrkusanin]

Summary

If we have a mask, and a value x, where (x | mask) == x, we can drop the OR
and just use x.

[foad]

LGTM modulo minor comments inline.

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

441

matchRedundantOr?

llvm/include/llvm/Target/GlobalISel/Combine.td

393

Update comment to say that (x | y) could be simplified to either x or y.

[mbrkusanin]

• Rename
• Updated comments

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

public:
   /// \return true if \p MI is a G_AND instruction whose operands are x and y
   /// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
   ///
   /// \param [in] MI - The G_AND instruction.
   /// \param [out] Replacement - A register the G_AND should be replaced with on
   /// success.
   bool matchRedundantAnd(MachineInstr &MI, Register &Replacement);
 
+  /// \return true if \p MI is a G_OR instruction whose operands are x and y
+  /// where x | y == x or x | y == y. (E.g., one of operands is all-zeros
+  /// value.)
+  ///
+  /// \param [in] MI - The G_OR instruction.
+  /// \param [out] Replacement - A register the G_OR should be replaced with on
+  /// success.
+  bool matchRedundantOr(MachineInstr &MI, Register &Replacement);
+
   /// \return true if \p MI is a G_SEXT_INREG that can be erased.
   bool matchRedundantSExtInReg(MachineInstr &MI);
 
   /// Combine inverting a result of a compare into the opposite cond code.
   bool matchNotCmp(MachineInstr &MI, SmallVectorImpl<Register> &RegsToNegate);
   bool applyNotCmp(MachineInstr &MI, SmallVectorImpl<Register> &RegsToNegate);
 
   /// Fold (xor (and x, y), y) -> (and (not x), y)

llvm/include/llvm/Target/GlobalISel/Combine.td

 def redundant_and_matchinfo : GIDefMatchData<"Register">;
 def redundant_and: GICombineRule <
   (defs root:$root, redundant_and_matchinfo:$matchinfo),
   (match (wip_match_opcode G_AND):$root,
          [{ return Helper.matchRedundantAnd(*${root}, ${matchinfo}); }]),
   (apply [{ return Helper.replaceSingleDefInstWithReg(*${root}, ${matchinfo}); }])
 >;
 
+// Fold (x | y) -> x or (x | y) -> y when (x | y) is known to equal x or equal y.
+def redundant_or_matchinfo : GIDefMatchData<"Register">;
+def redundant_or: GICombineRule <
+  (defs root:$root, redundant_or_matchinfo:$matchinfo),
+  (match (wip_match_opcode G_OR):$root,
+         [{ return Helper.matchRedundantOr(*${root}, ${matchinfo}); }]),
+  (apply [{ return Helper.replaceSingleDefInstWithReg(*${root}, ${matchinfo}); }])
+>;
+
 // If the input is already sign extended, just drop the extension.
 // sext_inreg x, K ->
 //   if computeNumSignBits(x) >= (x.getScalarSizeInBits() - K + 1)
 def redundant_sext_inreg: GICombineRule <
   (defs root:$root),
   (match (wip_match_opcode G_SEXT_INREG):$root,
          [{ return Helper.matchRedundantSExtInReg(*${root}); }]),
      (apply [{ return Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
                                         binop_same_val, binop_left_to_zero,
                                         binop_right_to_zero, p2i_to_i2p,
                                         i2p_to_p2i, anyext_trunc_fold,
                                         fneg_fneg_fold, right_identity_one]>;
 
 def const_combines : GICombineGroup<[constant_fp_op, const_ptradd_to_i2p]>;
 
 def known_bits_simplifications : GICombineGroup<[
-  redundant_and, redundant_sext_inreg]>;
+  redundant_and, redundant_sext_inreg, redundant_or]>;
 
 def width_reduction_combines : GICombineGroup<[reduce_shl_of_extend]>;
 
 def select_combines : GICombineGroup<[select_undef_cmp, select_constant_cmp]>;
 
 def trivial_combines : GICombineGroup<[copy_prop, mul_to_shl, add_p2i_to_ptradd,
                                        mul_by_neg_one]>;
 

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

if (canReplaceReg(AndDst, RHS, MRI) &&
       (LHSBits.One | RHSBits.Zero).isAllOnesValue()) {
     Replacement = RHS;
     return true;
   }
 
   return false;
 }
 
+bool CombinerHelper::matchRedundantOr(MachineInstr &MI, Register &Replacement) {
+  // Given
+  //
+  // %y:_(sN) = G_SOMETHING
+  // %x:_(sN) = G_SOMETHING
+  // %res:_(sN) = G_OR %x, %y
+  //
+  // Eliminate the G_OR when it is known that x | y == x or x | y == y.
+  assert(MI.getOpcode() == TargetOpcode::G_OR);
+  if (!KB)
+    return false;
+
+  Register OrDst = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(OrDst);
+
+  // FIXME: This should be removed once GISelKnownBits supports vectors.
+  if (DstTy.isVector())
+    return false;
+
+  Register LHS = MI.getOperand(1).getReg();
+  Register RHS = MI.getOperand(2).getReg();
+  KnownBits LHSBits = KB->getKnownBits(LHS);
+  KnownBits RHSBits = KB->getKnownBits(RHS);
+
+  // Check that x | Mask == x.
+  // x | 0 == x, always
+  // x | 1 == x, only if x is also 1
+  // Meaning Mask has no effect if every bit is either zero in Mask or one in x.
+  //
+  // Check if we can replace OrDst with the LHS of the G_OR
+  if (canReplaceReg(OrDst, LHS, MRI) &&
+      (LHSBits.One | RHSBits.Zero).isAllOnesValue()) {
+    Replacement = LHS;
+    return true;
+  }
+
+  // Check if we can replace OrDst with the RHS of the G_OR
+  if (canReplaceReg(OrDst, RHS, MRI) &&
+      (LHSBits.Zero | RHSBits.One).isAllOnesValue()) {
+    Replacement = RHS;
+    return true;
+  }
+
+  return false;
+}
+
 bool CombinerHelper::matchRedundantSExtInReg(MachineInstr &MI) {
   // If the input is already sign extended, just drop the extension.
   Register Src = MI.getOperand(1).getReg();
   unsigned ExtBits = MI.getOperand(2).getImm();
   unsigned TypeSize = MRI.getType(Src).getScalarSizeInBits();
   return KB->computeNumSignBits(Src) >= (TypeSize - ExtBits + 1);
 }
 

llvm/lib/Target/AArch64/AArch64Combine.td

 
 // Post-legalization combines which are primarily optimizations.
 def AArch64PostLegalizerCombinerHelper
     : GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
                        [copy_prop, erase_undef_store, combines_for_extload,
                         sext_trunc_sextload,
                         hoist_logic_op_with_same_opcode_hands,
                         redundant_and, xor_of_and_with_same_reg,
-                        extractvecelt_pairwise_add]> {
+                        extractvecelt_pairwise_add, redundant_or]> {
   let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            test_const_const_1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_const_const_1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: $sgpr0 = COPY [[C]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
+    %0:_(s32) = G_CONSTANT i32 255
+    %1:_(s32) = G_CONSTANT i32 15
+    %2:_(s32) = G_OR %0(s32), %1(s32)
+    $sgpr0 = COPY %2(s32)
+    SI_RETURN_TO_EPILOG implicit $sgpr0
+...
+
+---
+name:            test_const_const_2
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_const_const_2
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: $vgpr0 = COPY [[C]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = G_CONSTANT i32 15
+    %1:_(s32) = G_CONSTANT i32 255
+    %2:_(s32) = G_OR %0(s32), %1(s32)
+    $vgpr0 = COPY %2(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name:            test_const_const_3
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_const_const_3
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
+    ; CHECK: $vgpr0 = COPY [[C]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = G_CONSTANT i32 1431655765
+    %1:_(s32) = G_CONSTANT i32 1145324612
+    %2:_(s32) = G_OR %1(s32), %0(s32)
+    $vgpr0 = COPY %2(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name:            test_or_or
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_or_or
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[OR]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = G_CONSTANT i32 255
+    %2:_(s32) = G_CONSTANT i32 15
+    %3:_(s32) = G_OR %0, %1(s32)
+    %4:_(s32) = G_OR %3, %2
+    $vgpr0 = COPY %4(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name:            test_shl_xor_or
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0
+
+    ; CHECK-LABEL: name: test_shl_xor_or
+    ; CHECK: liveins: $sgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
+    ; CHECK: $sgpr0 = COPY [[XOR]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s32) = G_CONSTANT i32 5
+    %2:_(s32) = G_CONSTANT i32 -1
+    %3:_(s32) = G_CONSTANT i32 31
+    %4:_(s32) = G_SHL %0, %1(s32)
+    %5:_(s32) = G_XOR %4(s32), %2(s32)
+    %6:_(s32) = G_OR %5(s32), %3(s32)
+    $sgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $sgpr0
+...
+
+---
+name:            test_lshr_xor_or
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_lshr_xor_or
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
+    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[XOR]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = G_CONSTANT i32 5
+    %2:_(s32) = G_CONSTANT i32 -1
+    %3:_(s32) = G_CONSTANT i32 4160749568
+    %4:_(s32) = G_LSHR %0, %1(s32)
+    %5:_(s32) = G_XOR %4(s32), %2(s32)
+    %6:_(s32) = G_OR %5(s32), %3(s32)
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name:            test_or_non_const
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+
+    ; CHECK-LABEL: name: test_or_non_const
+    ; CHECK: liveins: $sgpr0, $sgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
+    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]
+    ; CHECK: $sgpr0 = COPY [[XOR]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s32) = COPY $sgpr1
+    %2:_(s32) = G_CONSTANT i32 16
+    %3:_(s32) = G_CONSTANT i32 -1
+    %4:_(s32) = G_CONSTANT i32 4294901760
+    %5:_(s32) = G_LSHR %0, %2(s32)
+    %6:_(s32) = G_XOR %5, %3(s32)
+    %7:_(s32) = G_AND %1, %4(s32)
+    %8:_(s32) = G_OR %6, %7
+    $sgpr0 = COPY %8(s32)
+    SI_RETURN_TO_EPILOG implicit $sgpr0
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll

.entry:
   %z2 = or i32 %z1, 3
   %z3 = lshr i32 %z2, 2
   ret i32 %z3
 }
 
 define amdgpu_cs i32 @test_lshr_or_2(i32 inreg %arg1) {
 ; CHECK-LABEL: test_lshr_or_2:
 ; CHECK:       ; %bb.0: ; %.entry
-; CHECK-NEXT:    s_lshr_b32 s0, s0, 8
-; CHECK-NEXT:    s_or_b32 s0, s0, 0xffffff
+; CHECK-NEXT:    s_mov_b32 s0, 0xffffff
 ; CHECK-NEXT:    ; return to shader part epilog
 .entry:
   %z1 = lshr i32 %arg1, 3
   %z2 = or i32 %z1, 536870880
   %z3 = lshr i32 %z2, 5
   ret i32 %z3
 }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll

 ; GISEL-NEXT:    v_mov_b32_e32 v1, 0
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_sdiv_i64_24bit:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    s_mov_b32 s4, 0xffffff
 ; CGP-NEXT:    v_and_b32_e32 v1, s4, v2
-; CGP-NEXT:    v_cvt_f32_i32_e32 v2, v1
+; CGP-NEXT:    v_cvt_f32_i32_e32 v1, v1
 ; CGP-NEXT:    v_and_b32_e32 v0, s4, v0
-; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v0
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v1
-; CGP-NEXT:    v_rcp_f32_e32 v4, v2
-; CGP-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
-; CGP-NEXT:    v_or_b32_e32 v0, 1, v0
-; CGP-NEXT:    v_mul_f32_e32 v1, v3, v4
-; CGP-NEXT:    v_trunc_f32_e32 v1, v1
-; CGP-NEXT:    v_mad_f32 v3, -v1, v2, v3
-; CGP-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; CGP-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
-; CGP-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
+; CGP-NEXT:    v_cvt_f32_i32_e32 v0, v0
+; CGP-NEXT:    v_rcp_f32_e32 v2, v1
+; CGP-NEXT:    v_mul_f32_e32 v2, v0, v2
+; CGP-NEXT:    v_trunc_f32_e32 v2, v2
+; CGP-NEXT:    v_mad_f32 v0, -v2, v1, v0
+; CGP-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v0|, |v1|
+; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %num.mask = and i64 %num, 16777215
   %den.mask = and i64 %den, 16777215
   %result = sdiv i64 %num.mask, %den.mask
   ret i64 %result
 }

 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_sdiv_v2i64_24bit:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    s_mov_b32 s4, 0xffffff
 ; CGP-NEXT:    v_and_b32_e32 v1, s4, v4
-; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v1
+; CGP-NEXT:    v_cvt_f32_i32_e32 v1, v1
 ; CGP-NEXT:    v_and_b32_e32 v0, s4, v0
+; CGP-NEXT:    v_cvt_f32_i32_e32 v0, v0
 ; CGP-NEXT:    v_and_b32_e32 v4, s4, v6
-; CGP-NEXT:    v_cvt_f32_i32_e32 v5, v0
-; CGP-NEXT:    v_rcp_f32_e32 v6, v3
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v1
+; CGP-NEXT:    v_rcp_f32_e32 v3, v1
+; CGP-NEXT:    v_cvt_f32_i32_e32 v4, v4
 ; CGP-NEXT:    v_and_b32_e32 v2, s4, v2
-; CGP-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
-; CGP-NEXT:    v_mul_f32_e32 v1, v5, v6
-; CGP-NEXT:    v_trunc_f32_e32 v1, v1
-; CGP-NEXT:    v_mad_f32 v5, -v1, v3, v5
-; CGP-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v3|
-; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v4
-; CGP-NEXT:    v_cvt_f32_i32_e32 v5, v2
-; CGP-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v4
-; CGP-NEXT:    v_rcp_f32_e32 v6, v3
-; CGP-NEXT:    v_or_b32_e32 v0, 1, v0
-; CGP-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; CGP-NEXT:    v_mul_f32_e32 v4, v5, v6
-; CGP-NEXT:    v_trunc_f32_e32 v4, v4
-; CGP-NEXT:    v_mad_f32 v5, -v4, v3, v5
-; CGP-NEXT:    v_cvt_i32_f32_e32 v4, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v2, 30, v2
-; CGP-NEXT:    v_or_b32_e32 v2, 1, v2
-; CGP-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v3|
-; CGP-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; CGP-NEXT:    v_cvt_f32_i32_e32 v2, v2
+; CGP-NEXT:    v_mul_f32_e32 v3, v0, v3
+; CGP-NEXT:    v_trunc_f32_e32 v3, v3
+; CGP-NEXT:    v_mad_f32 v0, -v3, v1, v0
+; CGP-NEXT:    v_cvt_i32_f32_e32 v3, v3
+; CGP-NEXT:    v_rcp_f32_e32 v5, v4
+; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v0|, |v1|
+; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
+; CGP-NEXT:    v_mul_f32_e32 v3, v2, v5
+; CGP-NEXT:    v_trunc_f32_e32 v3, v3
+; CGP-NEXT:    v_mad_f32 v2, -v3, v4, v2
+; CGP-NEXT:    v_cvt_i32_f32_e32 v3, v3
+; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v2|, |v4|
+; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[4:5]
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CGP-NEXT:    v_bfe_i32 v2, v2, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %num.mask = and <2 x i64> %num, <i64 16777215, i64 16777215>
   %den.mask = and <2 x i64> %den, <i64 16777215, i64 16777215>
   %result = sdiv <2 x i64> %num.mask, %den.mask
   ret <2 x i64> %result
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll

 ; CGP-LABEL: v_srem_i64_24bit:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    s_mov_b32 s4, 0xffffff
 ; CGP-NEXT:    v_and_b32_e32 v1, s4, v2
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v2, v1
 ; CGP-NEXT:    v_and_b32_e32 v0, s4, v0
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v0
-; CGP-NEXT:    v_xor_b32_e32 v5, v0, v1
 ; CGP-NEXT:    v_rcp_f32_e32 v4, v2
-; CGP-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
-; CGP-NEXT:    v_or_b32_e32 v5, 1, v5
 ; CGP-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; CGP-NEXT:    v_trunc_f32_e32 v4, v4
 ; CGP-NEXT:    v_mad_f32 v3, -v4, v2, v3
 ; CGP-NEXT:    v_cvt_i32_f32_e32 v4, v4
-; CGP-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
-; CGP-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
+; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|
+; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; CGP-NEXT:    v_mul_lo_u32 v1, v2, v1
 ; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %num.mask = and i64 %num, 16777215
   %den.mask = and i64 %den, 16777215

 ; CGP-LABEL: v_srem_v2i64_24bit:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    s_mov_b32 s4, 0xffffff
 ; CGP-NEXT:    v_and_b32_e32 v1, s4, v4
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v1
 ; CGP-NEXT:    v_and_b32_e32 v0, s4, v0
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v4, v0
-; CGP-NEXT:    v_xor_b32_e32 v7, v0, v1
+; CGP-NEXT:    v_and_b32_e32 v6, s4, v6
 ; CGP-NEXT:    v_rcp_f32_e32 v5, v3
-; CGP-NEXT:    v_ashrrev_i32_e32 v7, 30, v7
-; CGP-NEXT:    v_or_b32_e32 v7, 1, v7
 ; CGP-NEXT:    v_and_b32_e32 v2, s4, v2
 ; CGP-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; CGP-NEXT:    v_trunc_f32_e32 v5, v5
 ; CGP-NEXT:    v_mad_f32 v4, -v5, v3, v4
 ; CGP-NEXT:    v_cvt_i32_f32_e32 v5, v5
-; CGP-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
-; CGP-NEXT:    v_cndmask_b32_e32 v3, 0, v7, vcc
+; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v4|, |v3|
+; CGP-NEXT:    v_cvt_f32_i32_e32 v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; CGP-NEXT:    v_mul_lo_u32 v1, v3, v1
-; CGP-NEXT:    v_and_b32_e32 v3, s4, v6
-; CGP-NEXT:    v_cvt_f32_i32_e32 v4, v3
-; CGP-NEXT:    v_xor_b32_e32 v6, v2, v3
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
-; CGP-NEXT:    v_cvt_f32_i32_e32 v1, v2
+; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v2
 ; CGP-NEXT:    v_rcp_f32_e32 v5, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v6, 30, v6
-; CGP-NEXT:    v_or_b32_e32 v6, 1, v6
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
-; CGP-NEXT:    v_mul_f32_e32 v5, v1, v5
-; CGP-NEXT:    v_trunc_f32_e32 v5, v5
-; CGP-NEXT:    v_mad_f32 v1, -v5, v4, v1
-; CGP-NEXT:    v_cvt_i32_f32_e32 v5, v5
-; CGP-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v4|
-; CGP-NEXT:    v_cndmask_b32_e32 v1, 0, v6, vcc
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v5, v1
-; CGP-NEXT:    v_mul_lo_u32 v3, v1, v3
+; CGP-NEXT:    v_mul_f32_e32 v1, v3, v5
+; CGP-NEXT:    v_trunc_f32_e32 v1, v1
+; CGP-NEXT:    v_mad_f32 v3, -v1, v4, v3
+; CGP-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v3|, |v4|
+; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
+; CGP-NEXT:    v_mul_lo_u32 v3, v1, v6
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
 ; CGP-NEXT:    v_bfe_i32 v2, v2, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %num.mask = and <2 x i64> %num, <i64 16777215, i64 16777215>
   %den.mask = and <2 x i64> %den, <i64 16777215, i64 16777215>
   %result = srem <2 x i64> %num.mask, %den.mask
   ret <2 x i64> %result
 }