[NFC] Use Register/MCRegister

[google-llvm-upstream-contributions]

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

40–41

@critson - Looking at the uses of CondReg and ExecReg, it seems they are always physical registers (never virtual/stack slots), is this correct?

Thanks!

[mtrofin]

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

40–41

(sorry, somehow used the wrong account for this comment)

[gjain]

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

142

Does it make sense that instead of converting a MCRegister to a Register we should just compare the id's? I would think we we'd want to avoid easy conversions of MCRegister to Register.

Another options is we actually provide a comparison operator between MCRegister and Register.

[mtrofin]

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

142

Probably a pair == & != operators would be reasonable; I hit this a couple of times... hmm... may be best to do it in one swoop.

I'd add them in a subsequent patch, wdyt?

[gjain]

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

142

Of course!

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

int GCNHazardRecognizer::getWaitStatesSinceSetReg(IsHazardFn IsHazard,
 
   return getWaitStatesSince(IsHazardFn, Limit);
 }
 
 //===----------------------------------------------------------------------===//
 // No-op Hazard Detection
 //===----------------------------------------------------------------------===//
 
-static void addRegUnits(const SIRegisterInfo &TRI,
-                        BitVector &BV, unsigned Reg) {
+static void addRegUnits(const SIRegisterInfo &TRI, BitVector &BV,
+                        MCRegister Reg) {
   for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI)
     BV.set(*RUI);
 }
 
 static void addRegsToSet(const SIRegisterInfo &TRI,
                          iterator_range<MachineInstr::const_mop_iterator> Ops,
                          BitVector &Set) {
   for (const MachineOperand &Op : Ops) {
     if (Op.isReg())
-      addRegUnits(TRI, Set, Op.getReg());
+      addRegUnits(TRI, Set, Op.getReg().asMCReg());
   }
 }
 
 void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) {
   // XXX: Do we need to worry about implicit operands
   addRegsToSet(TRI, MI.defs(), ClauseDefs);
   addRegsToSet(TRI, MI.uses(), ClauseUses);
 }

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

private:
   const SIInstrInfo *TII;
   MachineRegisterInfo *MRI;
   LiveIntervals *LIS;
 
   unsigned AndOpc;
   unsigned Andn2Opc;
   unsigned OrSaveExecOpc;
   unsigned XorTermrOpc;
-  Register CondReg;
-  Register ExecReg;
+  MCRegister CondReg;
+  MCRegister ExecReg;
 
   Register optimizeVcndVcmpPair(MachineBasicBlock &MBB);
   bool optimizeElseBranch(MachineBasicBlock &MBB);
 
 public:
   static char ID;
 
   SIOptimizeExecMaskingPreRA() : MachineFunctionPass(ID) {
static bool isDefBetween(const SIRegisterInfo &TRI,
                          LiveIntervals *LIS, Register Reg,
                          const MachineInstr &Sel, const MachineInstr &And) {
   SlotIndex AndIdx = LIS->getInstructionIndex(And);
   SlotIndex SelIdx = LIS->getInstructionIndex(Sel);
 
   if (Reg.isVirtual())
     return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx);
 
-  for (MCRegUnitIterator UI(Reg, &TRI); UI.isValid(); ++UI) {
+  for (MCRegUnitIterator UI(Reg.asMCReg(), &TRI); UI.isValid(); ++UI) {
     if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx))
       return true;
   }
 
   return false;
 }
 
 // Optimize sequence
auto *And =
       TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS);
   if (!And || And->getOpcode() != AndOpc ||
       !And->getOperand(1).isReg() || !And->getOperand(2).isReg())
     return Register();
 
   MachineOperand *AndCC = &And->getOperand(1);
   Register CmpReg = AndCC->getReg();
   unsigned CmpSubReg = AndCC->getSubReg();
-  if (CmpReg == ExecReg) {
+  if (CmpReg == Register(ExecReg)) {
     AndCC = &And->getOperand(2);
     CmpReg = AndCC->getReg();
     CmpSubReg = AndCC->getSubReg();
-  } else if (And->getOperand(2).getReg() != ExecReg) {
+  } else if (And->getOperand(2).getReg() != Register(ExecReg)) {
     return Register();
   }
 
   auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS);
   if (!Cmp || !(Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e32 ||
                 Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e64) ||
       Cmp->getParent() != And->getParent())
     return Register();
SIOptimizeExecMaskingPreRA::optimizeVcndVcmpPair(MachineBasicBlock &MBB) {
   And->eraseFromParent();
   LIS->InsertMachineInstrInMaps(*Andn2);
 
   LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
 
   // Try to remove compare. Cmp value should not used in between of cmp
   // and s_and_b64 if VCC or just unused if any other register.
   if ((CmpReg.isVirtual() && MRI->use_nodbg_empty(CmpReg)) ||
-      (CmpReg == CondReg &&
+      (CmpReg == Register(CondReg) &&
        std::none_of(std::next(Cmp->getIterator()), Andn2->getIterator(),
                     [&](const MachineInstr &MI) {
                       return MI.readsRegister(CondReg, TRI);
                     }))) {
     LLVM_DEBUG(dbgs() << "Erasing: " << *Cmp << '\n');
 
     LIS->RemoveMachineInstrFromMaps(*Cmp);
     Cmp->eraseFromParent();
bool SIOptimizeExecMaskingPreRA::optimizeElseBranch(MachineBasicBlock &MBB) {
 
   auto I = llvm::find_if(MBB.terminators(), [this](const MachineInstr &MI) {
     return MI.getOpcode() == XorTermrOpc;
   });
   if (I == MBB.terminators().end())
     return false;
 
   MachineInstr &XorTermMI = *I;
-  if (XorTermMI.getOperand(1).getReg() != ExecReg)
+  if (XorTermMI.getOperand(1).getReg() != Register(ExecReg))
     return false;
 
   Register SavedExecReg = SaveExecMI.getOperand(0).getReg();
   Register DstReg = XorTermMI.getOperand(2).getReg();
 
   // Find potentially unnecessary S_AND
   MachineInstr *AndExecMI = nullptr;
   I--;
   while (I != First && !AndExecMI) {
     if (I->getOpcode() == AndOpc && I->getOperand(0).getReg() == DstReg &&
-        I->getOperand(1).getReg() == ExecReg)
+        I->getOperand(1).getReg() == Register(ExecReg))
       AndExecMI = &*I;
     I--;
   }
   if (!AndExecMI)
     return false;
 
   // Check for exec modifying instructions.
   // Note: exec defs do not create live ranges beyond the
bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
   LIS = &getAnalysis<LiveIntervals>();
 
   const bool Wave32 = ST.isWave32();
   AndOpc = Wave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
   Andn2Opc = Wave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;
   OrSaveExecOpc =
       Wave32 ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64;
   XorTermrOpc = Wave32 ? AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term;
-  CondReg = Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC;
-  ExecReg = Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
+  CondReg = MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC);
+  ExecReg = MCRegister::from(Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC);
 
   DenseSet<Register> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});
   bool Changed = false;
 
   for (MachineBasicBlock &MBB : MF) {
 
     if (optimizeElseBranch(MBB)) {
       RecalcRegs.insert(AMDGPU::SCC);
for (MachineBasicBlock &MBB : MF) {
     //    %0:sreg_64 = COPY $exec
     //    %1:sreg_64 = S_AND_B64 %0:sreg_64, %2:sreg_64
     // =>
     //    %1 = S_AND_B64 $exec, %2:sreg_64
     unsigned ScanThreshold = 10;
     for (auto I = MBB.rbegin(), E = MBB.rend(); I != E
          && ScanThreshold--; ++I) {
       // Continue scanning if this is not a full exec copy
-      if (!(I->isFullCopy() && I->getOperand(1).getReg() == ExecReg))
+      if (!(I->isFullCopy() && I->getOperand(1).getReg() == Register(ExecReg)))
         continue;
 
       Register SavedExec = I->getOperand(0).getReg();
       if (SavedExec.isVirtual() && MRI->hasOneNonDBGUse(SavedExec) &&
           MRI->use_instr_nodbg_begin(SavedExec)->getParent() ==
               I->getParent()) {
         LLVM_DEBUG(dbgs() << "Redundant EXEC COPY: " << *I << '\n');
         LIS->RemoveMachineInstrFromMaps(*I);