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[mlir][spirv] Allow usage of vector size 8 and 16 with Vector16 capability
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Authored by abialas on Nov 3 2020, 6:18 AM.

Details

Summary

Per spec, vector sizes 8 and 16 are allowed when Vector16 capability is present. This change expand the limitation of vector sizes to accept these sizes.

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Event Timeline

abialas created this revision.Nov 3 2020, 6:18 AM
abialas requested review of this revision.Nov 3 2020, 6:18 AM
antiagainst requested changes to this revision.Nov 3 2020, 9:33 AM

Cool! Can you also add a test to test/Dialect/SPIRV/availability.mlir to check that Vector16 capability kicks in?

mlir/lib/Dialect/SPIRV/SPIRVTypes.cpp
175

This variable isn't needed really? I think we can just let valid sizes pass through to the final check?

mlir/test/Dialect/SPIRV/Serialization/ocl-ops.mlir
18

This is size 16? :)

This revision now requires changes to proceed.Nov 3 2020, 9:33 AM
abialas updated this revision to Diff 302774.Nov 4 2020, 1:26 AM

Thank You for the review. Added requested changes, except testing in availability.mlir. As this is test type required capability it is not being kicked there when checking particular ops, similar to Int8 or Float16. I added one more test for this in vce-deduction.mlir

antiagainst accepted this revision.Nov 4 2020, 4:39 AM
This revision is now accepted and ready to land.Nov 4 2020, 4:39 AM