[AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds

[foad]

Summary

By setting up the AsmStrings correctly we can remove some special cases
from AMDGPUInstPrinter::printOffset.

[foad]

Unfortunately I can't reliably test this change with FileCheck. It seems to tolerate a double space in the input when I only want to match a single space, even if I use a regexp pattern like {{\ }}.

[arsenm]

llvm/lib/Target/AMDGPU/DSInstructions.td

333

Why is there a $gds operand here if it's not used for printing?

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

142

Single quotes

[arsenm]

In D90307#2359027, @foad wrote:

Unfortunately I can't reliably test this change with FileCheck. It seems to tolerate a double space in the input when I only want to match a single space, even if I use a regexp pattern like {{\ }}.

There's a -strict-whitespace flag

[foad]

Rebase after adding -strict-whitespace to the tests.

[foad]

Use single quotes.

[foad]

llvm/lib/Target/AMDGPU/DSInstructions.td

333

There's already a TODO for that: https://github.com/llvm/llvm-project/blob/5febc535c4f8e278124cdeb88a4a82d99016944c/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp#L2501

[rampitec]

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

142

Are you sure it didn't add an extra space in some other instructions? Are there any other instructions where offset can be the first operand?

[foad]

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

142

Are you sure it didn't add an extra space in some other instructions?

Well it didn't break any disassembler tests with -strict-whitespace. I did wonder if it might add an extra space at the *end* of some other instruction, that would be hidden because -show-encoding pads with spaces to a fixed column number before adding the "; encoding:" comment. But...

Are there any other instructions where offset can be the first operand?

No, I have looked through the output of tablegen and I can't find any others.

[foad]

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

142

An alternative fix would be to remove this special handling of OpNo==0 and change the AsmStrings to remove the space between the mnemonic and the $offset operand. I can try that out.

[rampitec]

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

142

If it works it would be cleaner.

[foad]

Cleaner fix.

[foad]

llvm/lib/Target/AMDGPU/DSInstructions.td

333

D90378

[rampitec]

Thanks, Jay!

llvm/lib/Target/AMDGPU/DSInstructions.td

class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
   bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
 
   bits<1> has_m0_read = 1;
 
   let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
 }
 
 class DS_Real <DS_Pseudo ds> :
-  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
+  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # ds.AsmOperands, []>,
   Enc64 {
 
   let isPseudo = 0;
   let isCodeGenOnly = 0;
   let DS = 1;
   let UseNamedOperandTable = 1;
 
   // copy relevant pseudo op flags

 
 
 // DS Pseudo instructions
 
 class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
 : DS_Pseudo<opName,
   (outs),
   (ins rc:$data0, offset:$offset, gds:$gds),
-  "$data0$offset$gds"> {
+  " $data0$offset$gds"> {
 
   let has_addr = 0;
   let has_data1 = 0;
   let has_vdst = 0;
 }
 
 class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
 : DS_Pseudo<opName,
   (outs),
   (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
-  "$addr, $data0$offset$gds"> {
+  " $addr, $data0$offset$gds"> {
 
   let has_data1 = 0;
   let has_vdst = 0;
 }
 
 multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
   def "" : DS_1A1D_NORET<opName, rc>,
            AtomicNoRet<opName, 0>;
 
   let has_m0_read = 0 in {
     def _gfx9 : DS_1A1D_NORET<opName, rc>,
                 AtomicNoRet<opName#"_gfx9", 0>;
   }
 }
 
 class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
 : DS_Pseudo<opName,
   (outs),
   (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
-  "$addr, $data0, $data1$offset$gds"> {
+  " $addr, $data0, $data1$offset$gds"> {
 
   let has_vdst = 0;
 }
 
 multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
   def "" : DS_1A2D_NORET<opName, rc>,
            AtomicNoRet<opName, 0>;
 
   let has_m0_read = 0 in {
     def _gfx9 : DS_1A2D_NORET<opName, rc>,
                 AtomicNoRet<opName#"_gfx9", 0>;
   }
 }
 
 class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
 : DS_Pseudo<opName,
   (outs),
   (ins VGPR_32:$addr, rc:$data0, rc:$data1,
        offset0:$offset0, offset1:$offset1, gds:$gds),
-  "$addr, $data0, $data1$offset0$offset1$gds"> {
+  " $addr, $data0, $data1$offset0$offset1$gds"> {
 
   let has_vdst = 0;
   let has_offset = 0;
   let AsmMatchConverter = "cvtDSOffset01";
 }
 
 multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
   def "" : DS_1A2D_Off8_NORET<opName, rc>;
 
   let has_m0_read = 0 in {
     def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
   }
 }
 
 class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
 : DS_Pseudo<opName,
   (outs rc:$vdst),
   (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
-  "$vdst, $addr, $data0$offset$gds"> {
+  " $vdst, $addr, $data0$offset$gds"> {
 
   let hasPostISelHook = 1;
   let has_data1 = 0;
 }
 
 multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
                            string NoRetOp = ""> {
   def "" : DS_1A1D_RET<opName, rc>,
     AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
 
   let has_m0_read = 0 in {
     def _gfx9 : DS_1A1D_RET<opName, rc>,
       AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
                   !ne(NoRetOp, "")>;
   }
 }
 
 class DS_1A2D_RET<string opName,
                   RegisterClass rc = VGPR_32,
                   RegisterClass src = rc>
 : DS_Pseudo<opName,
   (outs rc:$vdst),
   (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
-  "$vdst, $addr, $data0, $data1$offset$gds"> {
+  " $vdst, $addr, $data0, $data1$offset$gds"> {
 
   let hasPostISelHook = 1;
 }
 
 multiclass DS_1A2D_RET_mc<string opName,
                           RegisterClass rc = VGPR_32,
                           string NoRetOp = "",
                           RegisterClass src = rc> {
   def "" : DS_1A2D_RET<opName, rc, src>,
     AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
 
   let has_m0_read = 0 in {
     def _gfx9 : DS_1A2D_RET<opName, rc, src>,
       AtomicNoRet<NoRetOp#"_gfx9", !ne(NoRetOp, "")>;
   }
 }
 
 class DS_1A2D_Off8_RET<string opName,
                        RegisterClass rc = VGPR_32,
                        RegisterClass src = rc>
 : DS_Pseudo<opName,
   (outs rc:$vdst),
   (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
-  "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
+  " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
 
   let has_offset = 0;
   let AsmMatchConverter = "cvtDSOffset01";
 
   let hasPostISelHook = 1;
 }
 
 multiclass DS_1A2D_Off8_RET_mc<string opName,
                                RegisterClass rc = VGPR_32,
                                RegisterClass src = rc> {
   def "" : DS_1A2D_Off8_RET<opName, rc, src>;
 
   let has_m0_read = 0 in {
     def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
   }
 }
 
 
 class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset>
 : DS_Pseudo<opName,
   (outs rc:$vdst),
   !if(HasTiedOutput,
     (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
     (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
-  "$vdst, $addr$offset$gds"> {
+  " $vdst, $addr$offset$gds"> {
   let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
   let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
   let has_data0 = 0;
   let has_data1 = 0;
 }
 
 multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
   def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
 
   let has_m0_read = 0 in {
     def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
   }
 }
 
 class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
   DS_1A_RET<opName, rc, 1>;
 
 class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
 : DS_Pseudo<opName,
   (outs rc:$vdst),
   (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
-  "$vdst, $addr$offset0$offset1$gds"> {
+  " $vdst, $addr$offset0$offset1$gds"> {
 
   let has_offset = 0;
   let has_data0 = 0;
   let has_data1 = 0;
   let AsmMatchConverter = "cvtDSOffset01";
 }
 
 multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
   def "" : DS_1A_Off8_RET<opName, rc>;
 
   let has_m0_read = 0 in {
     def _gfx9 : DS_1A_Off8_RET<opName, rc>;
   }
 }
 
 class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
   (outs VGPR_32:$vdst),
   (ins VGPR_32:$addr, offset:$offset),
-  "$vdst, $addr$offset gds"> {
+  " $vdst, $addr$offset gds"> {
 
   let has_data0 = 0;
   let has_data1 = 0;
   let has_gds = 0;
   let gdsValue = 1;
   let AsmMatchConverter = "cvtDSGds";
 }
 
 class DS_0A_RET <string opName> : DS_Pseudo<opName,
   (outs VGPR_32:$vdst),
   (ins offset:$offset, gds:$gds),
-  "$vdst$offset$gds"> {
+  " $vdst$offset$gds"> {
 
   let mayLoad = 1;
   let mayStore = 1;
 
   let has_addr = 0;
   let has_data0 = 0;
   let has_data1 = 0;
 }
 
 class DS_1A <string opName> : DS_Pseudo<opName,
   (outs),
   (ins VGPR_32:$addr, offset:$offset, gds:$gds),
-  "$addr$offset$gds"> {
+  " $addr$offset$gds"> {
 
   let mayLoad = 1;
   let mayStore = 1;
 
   let has_vdst = 0;
   let has_data0 = 0;
   let has_data1 = 0;
 }
: DS_Pseudo<opName, (outs), ins, asmOps> {
 
   let has_gds   = 0;
   let gdsValue  = 1;
   let AsmMatchConverter = "cvtDSGds";
 }
 
 class DS_GWS_0D <string opName>
 : DS_GWS<opName,
   (ins offset:$offset, gds:$gds), "$offset gds"> {
   let hasSideEffects = 1;
 }
 
 class DS_GWS_1D <string opName>
 : DS_GWS<opName,
-  (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
+  (ins VGPR_32:$data0, offset:$offset, gds:$gds), " $data0$offset gds"> {
 
   let has_gws_data0 = 1;
   let hasSideEffects = 1;
 }
 
 class DS_VOID <string opName> : DS_Pseudo<opName,
   (outs), (ins), ""> {
   let mayLoad = 0;
class DS_VOID <string opName> : DS_Pseudo<opName,
   let has_offset1 = 0;
   let has_gds = 0;
 }
 
 class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
 : DS_Pseudo<opName,
   (outs VGPR_32:$vdst),
   (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
-  "$vdst, $addr, $data0$offset",
+  " $vdst, $addr, $data0$offset",
   [(set i32:$vdst,
    (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
 
   let mayLoad = 0;
   let mayStore = 0;
   let isConvergent = 1;
 
   let has_data1 = 0;

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
   }
 }
 
 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
                                     const MCSubtargetInfo &STI,
                                     raw_ostream &O) {
   uint16_t Imm = MI->getOperand(OpNo).getImm();
   if (Imm != 0) {
-    O << ((OpNo == 0)? "offset:" : " offset:");
+    O << " offset:";
     printU16ImmDecOperand(MI, OpNo, O);
   }
 }
 
 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   uint16_t Imm = MI->getOperand(OpNo).getImm();
   if (Imm != 0) {
-    O << ((OpNo == 0)? "offset:" : " offset:");
+    O << " offset:";
 
     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
     bool IsFlatSeg = !(Desc.TSFlags & SIInstrFlags::IsNonFlatSeg);
 
     if (IsFlatSeg) { // Unsigned offset
       printU16ImmDecOperand(MI, OpNo, O);
     } else {         // Signed offset
       if (AMDGPU::isGFX10(STI)) {

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 0x00,0x00,0x6e,0xd8,0xff,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_br v255 offset:4660 gds     ; encoding: [0x34,0x12,0x6e,0xd8,0xff,0x00,0x00,0x00]
 0x34,0x12,0x6e,0xd8,0xff,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_br v255 offset:65535 gds    ; encoding: [0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00]
 0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00
 
-# GFX10: ds_gws_sema_p  gds                      ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_p gds                       ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
 0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_p offset:4660 gds           ; encoding: [0x34,0x12,0x72,0xd8,0x00,0x00,0x00,0x00]
 0x34,0x12,0x72,0xd8,0x00,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_p offset:65535 gds          ; encoding: [0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00]
 0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00
 
-# GFX10: ds_gws_sema_release_all  gds            ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_release_all gds             ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
 0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_release_all offset:4660 gds ; encoding: [0x34,0x12,0x62,0xd8,0x00,0x00,0x00,0x00]
 0x34,0x12,0x62,0xd8,0x00,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
 0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00
 
-# GFX10: ds_gws_sema_v  gds                      ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_v gds                       ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
 0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_v offset:4660 gds           ; encoding: [0x34,0x12,0x6a,0xd8,0x00,0x00,0x00,0x00]
 0x34,0x12,0x6a,0xd8,0x00,0x00,0x00,0x00
 
 # GFX10: ds_gws_sema_v offset:65535 gds          ; encoding: [0xff,0xff,0x6a,0xd8,0x00,0x00,0x00,0x00]
 0xff,0xff,0x6a,0xd8,0x00,0x00,0x00,0x00
 

llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt

 0x04,0x00,0x26,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_max_src2_f32 v1 offset:65535 gds     ; encoding: [0xff,0xff,0x27,0xd9,0x01,0x00,0x00,0x00]
 0xff,0xff,0x27,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_release_all  gds            ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_release_all gds             ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_release_all offset:4 gds    ; encoding: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
 0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_init v1 offset:65535 gds         ; encoding: [0xff,0xff,0x33,0xd9,0x01,0x00,0x00,0x00]
 0xff,0xff,0x33,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_init v255 offset:65535 gds       ; encoding: [0xff,0xff,0x33,0xd9,0xff,0x00,0x00,0x00]
 0xff,0xff,0x33,0xd9,0xff,0x00,0x00,0x00
 
 # CHECK: ds_gws_init v1 gds                      ; encoding: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
 0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_init v1 offset:4 gds             ; encoding: [0x04,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
 0x04,0x00,0x33,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_v offset:65535 gds          ; encoding: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_v  gds                      ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_v gds                       ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_v offset:4 gds              ; encoding: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
 0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_br v1 offset:65535 gds      ; encoding: [0xff,0xff,0x37,0xd9,0x01,0x00,0x00,0x00]
 0xff,0xff,0x37,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_br v255 offset:65535 gds    ; encoding: [0xff,0xff,0x37,0xd9,0xff,0x00,0x00,0x00]
 0xff,0xff,0x37,0xd9,0xff,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_br v1 gds                   ; encoding: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
 0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_br v1 offset:4 gds          ; encoding: [0x04,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
 0x04,0x00,0x37,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_p offset:65535 gds          ; encoding: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_p  gds                      ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_p gds                       ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_p offset:4 gds              ; encoding: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
 0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_barrier v1 offset:65535 gds      ; encoding: [0xff,0xff,0x3b,0xd9,0x01,0x00,0x00,0x00]
 0xff,0xff,0x3b,0xd9,0x01,0x00,0x00,0x00
 

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

 0x04,0x00,0x26,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_max_src2_f32 v1 offset:65535 gds     ; encoding: [0xff,0xff,0x27,0xd9,0x01,0x00,0x00,0x00]
 0xff,0xff,0x27,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_release_all  gds            ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_release_all gds             ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_release_all offset:4 gds    ; encoding: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
 0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_init v1 offset:65535 gds         ; encoding: [0xff,0xff,0x33,0xd9,0x01,0x00,0x00,0x00]
 0xff,0xff,0x33,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_init v255 offset:65535 gds       ; encoding: [0xff,0xff,0x33,0xd9,0xff,0x00,0x00,0x00]
 0xff,0xff,0x33,0xd9,0xff,0x00,0x00,0x00
 
 # CHECK: ds_gws_init v1 gds                      ; encoding: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
 0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_init v1 offset:4 gds             ; encoding: [0x04,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
 0x04,0x00,0x33,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_v offset:65535 gds          ; encoding: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_v  gds                      ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_v gds                       ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_v offset:4 gds              ; encoding: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
 0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_br v1 offset:65535 gds      ; encoding: [0xff,0xff,0x37,0xd9,0x01,0x00,0x00,0x00]
 0xff,0xff,0x37,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_br v255 offset:65535 gds    ; encoding: [0xff,0xff,0x37,0xd9,0xff,0x00,0x00,0x00]
 0xff,0xff,0x37,0xd9,0xff,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_br v1 gds                   ; encoding: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
 0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_br v1 offset:4 gds          ; encoding: [0x04,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
 0x04,0x00,0x37,0xd9,0x01,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_p offset:65535 gds          ; encoding: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
 0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00
 
-# CHECK: ds_gws_sema_p  gds                      ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_p gds                       ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
 0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_sema_p offset:4 gds              ; encoding: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
 0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00
 
 # CHECK: ds_gws_barrier v1 offset:65535 gds      ; encoding: [0xff,0xff,0x3b,0xd9,0x01,0x00,0x00,0x00]
 0xff,0xff,0x3b,0xd9,0x01,0x00,0x00,0x00