[PowerPC] Exploit splat instruction xxsplti32dx in Power10

[Conanap]

Summary

Exploits the instruction xxsplti32dx.

It can be used to materialize any 64 bit scalar/vector splat by using two instances, one for the upper 32 bits and the other for the lower 32 bits. It should not materialize the cases which can be materialized by using the instruction xxspltidp.

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8609

Slightly over 80 characters.

8618

These lines are also a bit over 80 characters, and I think we prefer to capitalize the variables.

nit: Maybe we can go with something like Hi and Lo?

8622

nit: I believe the braces in all of these ifs can be omitted.

8623

nit: Capitalize the sentence and end with period.

8634

Might be a dumb question, but do you not need dl here?

8645–8646

Unintended change?

llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll

17–18

Since the CHECKs are usually generated by update_llc_test_checks.py in this test case like stated on the top, I think the formatting of the CHECKs won't be outputted the way you currently have it the next time this test gets updated.

It might be better to just run the script and have all the CHECKs be separated out.

[Conanap]

Addressed some formatting problems as well as corrected incorrect arguments for Hi case.

[Conanap]

The unrelated change no longer shows as diff, thank you!

[Conanap]

Updated a test file.

[NeHuang]

Please clang-format the patch to pass pre-merge checks.

[Conanap]

Clang-format

[Conanap]

clang format

[NeHuang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8604

please follow the naming convention in this file to use IsLE

8618

Agree with Amy it is better to use Hi and Lo` as the variable names.
Also it is still taking more than 80 characters. Please double check if you properly clang-format it.

8619

85 characters in this line, please double check you properly do clang-format

8627

I do not quite understand the if and else logic here, current logic seems we can overwrite SplatNode after we execute SplatNode = DAG.getTargetConstant(0, dl, MVT::v2i64);
Is that as expected?

llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll

17–18

alignment issue

19

alignment issue

52–53

alignment issue

[Conanap]

Addressed some formatting comments

[Conanap]

Replied to a comment

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8627

Thanks for bringing this up. SplatNode is reused in if (Lo) and if (Hi); it just saves a variable and a ternary statement (if (Hi) will also have to check if Lo created a SDNode before deciding between SplatNode or the SDNode created by Lo), but can understandably be confusing. I could separate them in to different variables and if statements to make it easier to understand if that's preferred.

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8629

Braces can be omitted here and on 9364 if it's just a single statement.

8638

I think I'm still a little confused by this. Do we not need dl when we do getNode() here?

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2388

It would be good to put this under the "Anonymous Patterns" section.

[Conanap]

addressed a comment

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8638

Hey so the DL is supplied from SplatNode's definition, and then we pass in SDLoc(SplatNode) here as the proper SDLoc after new instr def.

[Conanap]

Removed braces for single lines

[Conanap]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2388

thanks for catching that, I meant to put it there originally.

[nemanjai]

This is not functionally correct.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8617

Nit: full sentences in comments. Capitalize the first word.

8621

Won't this just produce a zero?

8623

Initialize to undef to simplify the logic below.

8631

The debug location comes from the original node (i.e. dl in this case). Just use that - no ternary operator.

8633

Why does the index change depending on endianness? You are trying to produce a 64-bit pattern that is in no way dependent on endianness.

[Conanap]

Addressed some comments for formatting and style

[Conanap]

initialize as a form of undef instead

[Conanap]

Removed unecessary ternary

[Conanap]

Fixed a typo that prevented successful builds

[NeHuang]

LGTM and please wait for Nemanja's approval before committing this patch.

[nemanjai]

This is still incorrect. The indices for the hi/low words are backwards. You can easily demonstrate this with a test case such as:

a.c:
vector double test() { return (vector double)4.23422e12; }

b.c:
#include <stdio.h>

vector double test();
int main(int argc, const char **argv) {
  vector double vec = test();
  return printf("{ %g, %g }\n", vec[0], vec[1]);
}

$ clang -O3 a.c b.c -mcpu=pwr10
$ ./a.out
{ 5.55224e+224, 5.55224e+224 }

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8632

The high word goes to index zero and the low word goes to index 1. This is backwards.

8638

Why? Please don't use implicit conversion this way.
DAG.getTargetConstant() takes and SDLoc, you are passing an SDValue. This of course works because the former has a constructor that does the implicit conversion, but this is completely unnecessary and actually makes code less readable.

[Conanap]

Loads Hi before Lo now; removed implicit cast.

[nemanjai]

LGTM.

[Conanap]

Pushed; differential revision link accidentally had an extra https:// so it did not automatically close.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
 
   // Check if this is a splat of a constant value.
   APInt APSplatBits, APSplatUndef;
   unsigned SplatBitSize;
   bool HasAnyUndefs;
   bool BVNIsConstantSplat =
       BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
                            HasAnyUndefs, 0, !Subtarget.isLittleEndian());
 
   // If it is a splat of a double, check if we can shrink it to a 32 bit
   // non-denormal float which when converted back to double gives us the same
   // double. This is to exploit the XXSPLTIDP instruction.
-  if (BVNIsConstantSplat && Subtarget.hasPrefixInstrs() &&
-      (SplatBitSize == 64) && (Op->getValueType(0) == MVT::v2f64) &&
-      convertToNonDenormSingle(APSplatBits)) {
+  // If we lose precision, we use XXSPLTI32DX.
+  if (BVNIsConstantSplat && (SplatBitSize == 64) &&
+      Subtarget.hasPrefixInstrs()) {
+    if (convertToNonDenormSingle(APSplatBits) &&
+        (Op->getValueType(0) == MVT::v2f64)) {
       SDValue SplatNode = DAG.getNode(
           PPCISD::XXSPLTI_SP_TO_DP, dl, MVT::v2f64,
           DAG.getTargetConstant(APSplatBits.getZExtValue(), dl, MVT::i32));
       return DAG.getBitcast(Op.getValueType(), SplatNode);
+    } else { // We may lose precision, so we have to use XXSPLTI32DX.
+
+      uint32_t Hi =
+          (uint32_t)((APSplatBits.getZExtValue() & 0xFFFFFFFF00000000LL) >> 32);
+      uint32_t Lo =
+          (uint32_t)(APSplatBits.getZExtValue() & 0xFFFFFFFF);
+      SDValue SplatNode = DAG.getUNDEF(MVT::v2i64);
+
+      if (!Hi || !Lo)
+        // If either load is 0, then we should generate XXLXOR to set to 0.
+        SplatNode = DAG.getTargetConstant(0, dl, MVT::v2i64);
+
+      if (Hi)
+        SplatNode = DAG.getNode(
+            PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode,
+            DAG.getTargetConstant(0, dl, MVT::i32),
+            DAG.getTargetConstant(Hi, dl, MVT::i32));
+
+      if (Lo)
+        SplatNode =
+            DAG.getNode(PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode,
+                        DAG.getTargetConstant(1, dl, MVT::i32),
+                        DAG.getTargetConstant(Lo, dl, MVT::i32));
+
+      return DAG.getBitcast(Op.getValueType(), SplatNode);
+    }
   }
 
   if (!BVNIsConstantSplat || SplatBitSize > 32) {
 
     bool IsPermutedLoad = false;
     const SDValue *InputLoad =
         getNormalLoadInput(Op.getOperand(0), IsPermutedLoad);
     // Handle load-and-splat patterns as we have instructions that will do this
     // in one go.
     if (InputLoad && DAG.isSplatValue(Op, true)) {
       LoadSDNode *LD = cast<LoadSDNode>(*InputLoad);
 

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let Predicates = [IsISA3_1] in {
   def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
   def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
   def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
   def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
   def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
   def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
   def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
 }
 
 let Predicates = [IsISA3_1, HasVSX] in {
   def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
   def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
 }
 
 // Multiclass defining patterns for Set Boolean Extension Reverse Instructions.
 // This is analogous to the CRNotPat multiclass but specifically for Power10
 // and newer subtargets since the extended forms use Set Boolean instructions.
def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 16)),
              (v1i128 (COPY_TO_REGCLASS (LXVRHX xoaddr:$src), VRRC))>;
   def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 32)),
              (v1i128 (COPY_TO_REGCLASS (LXVRWX xoaddr:$src), VRRC))>;
   def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 64)),
              (v1i128 (COPY_TO_REGCLASS (LXVRDX xoaddr:$src), VRRC))>;
 
   def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)),
             (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>;
+
+  def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)),
+             (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>;
 }
 
 let Predicates = [IsISA3_1, HasVSX] in {
   def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)),
             (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>;
   def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)),
             (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;
 }

llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s --check-prefixes=CHECK-LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
-; RUN:     --check-prefix=CHECK-NOPCREL
+; RUN:     --check-prefixes=CHECK-NOPCREL-BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:     -mattr=-pcrelative-memops -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
-; RUN:     FileCheck %s --check-prefix=CHECK-NOPCREL
+; RUN:     FileCheck %s --check-prefixes=CHECK-NOPCREL-LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:     -mattr=-prefix-instrs -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
-; RUN:     FileCheck %s --check-prefix=CHECK-NOPCREL
+; RUN:     FileCheck %s --check-prefixes=CHECK-NOPREFIX
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:     -ppc-asm-full-reg-names -target-abi=elfv2 -mcpu=pwr10 < %s | \
-; RUN:     FileCheck %s
+; RUN:     FileCheck %s --check-prefixes=CHECK-BE
 
 define dso_local <2 x double> @testDoubleToDoubleFail() local_unnamed_addr {
-; CHECK-LABEL: testDoubleToDoubleFail:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI0_0@PCREL(0), 1
-; CHECK-NEXT:    blr
-;
-; CHECK-NOPCREL-LABEL: testDoubleToDoubleFail:
-; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-NOPCREL-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-NOPCREL-NEXT:    lxvx vs34, 0, r3
-; CHECK-NOPCREL-NEXT:    blr
-
+; CHECK-LE-LABEL: testDoubleToDoubleFail:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxsplti32dx vs34, 0, 1081435463
+; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, -1374389535
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-NOPCREL-BE-LABEL: testDoubleToDoubleFail:
+; CHECK-NOPCREL-BE:       # %bb.0: # %entry
+; CHECK-NOPCREL-BE-NEXT:    xxsplti32dx vs34, 0, 1081435463
+; CHECK-NOPCREL-BE-NEXT:    xxsplti32dx vs34, 1, -1374389535
+; CHECK-NOPCREL-BE-NEXT:    blr
+;
+; CHECK-NOPCREL-LE-LABEL: testDoubleToDoubleFail:
+; CHECK-NOPCREL-LE:       # %bb.0: # %entry
+; CHECK-NOPCREL-LE-NEXT:    xxsplti32dx vs34, 0, 1081435463
+; CHECK-NOPCREL-LE-NEXT:    xxsplti32dx vs34, 1, -1374389535
+; CHECK-NOPCREL-LE-NEXT:    blr
+;
+; CHECK-NOPREFIX-LABEL: testDoubleToDoubleFail:
+; CHECK-NOPREFIX:       # %bb.0: # %entry
+; CHECK-NOPREFIX-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-NOPREFIX-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-NOPREFIX-NEXT:    lxvx vs34, 0, r3
+; CHECK-NOPREFIX-NEXT:    blr
+;
+; CHECK-BE-LABEL: testDoubleToDoubleFail:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, 1081435463
+; CHECK-BE-NEXT:    xxsplti32dx vs34, 1, -1374389535
+; CHECK-BE-NEXT:    blr
 entry:
   ret <2 x double> <double 3.423300e+02, double 3.423300e+02>
 }
 
 define dso_local <2 x double> @testFloatDenormToDouble() local_unnamed_addr {
-; CHECK-LABEL: testFloatDenormToDouble:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI1_0@PCREL(0), 1
-; CHECK-NEXT:    blr
-;
-; CHECK-NOPCREL-LABEL: testFloatDenormToDouble:
-; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-NOPCREL-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-NOPCREL-NEXT:    lxvx vs34, 0, r3
-; CHECK-NOPCREL-NEXT:    blr
-
+; CHECK-LE-LABEL: testFloatDenormToDouble:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxsplti32dx vs34, 0, 940259579
+; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, -2147483648
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-NOPCREL-BE-LABEL: testFloatDenormToDouble:
+; CHECK-NOPCREL-BE:       # %bb.0: # %entry
+; CHECK-NOPCREL-BE-NEXT:    xxsplti32dx vs34, 0, 940259579
+; CHECK-NOPCREL-BE-NEXT:    xxsplti32dx vs34, 1, -2147483648
+; CHECK-NOPCREL-BE-NEXT:    blr
+;
+; CHECK-NOPCREL-LE-LABEL: testFloatDenormToDouble:
+; CHECK-NOPCREL-LE:       # %bb.0: # %entry
+; CHECK-NOPCREL-LE-NEXT:    xxsplti32dx vs34, 0, 940259579
+; CHECK-NOPCREL-LE-NEXT:    xxsplti32dx vs34, 1, -2147483648
+; CHECK-NOPCREL-LE-NEXT:    blr
+;
+; CHECK-NOPREFIX-LABEL: testFloatDenormToDouble:
+; CHECK-NOPREFIX:       # %bb.0: # %entry
+; CHECK-NOPREFIX-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-NOPREFIX-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-NOPREFIX-NEXT:    lxvx vs34, 0, r3
+; CHECK-NOPREFIX-NEXT:    blr
+;
+; CHECK-BE-LABEL: testFloatDenormToDouble:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, 940259579
+; CHECK-BE-NEXT:    xxsplti32dx vs34, 1, -2147483648
+; CHECK-BE-NEXT:    blr
 entry:
   ret <2 x double> <double 0x380B38FB80000000, double 0x380B38FB80000000>
 }
 
 define dso_local <2 x double> @testDoubleToDoubleNaNFail() local_unnamed_addr {
-; CHECK-LABEL: testDoubleToDoubleNaNFail:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI2_0@PCREL(0), 1
-; CHECK-NEXT:    blr
-;
-; CHECK-NOPCREL-LABEL: testDoubleToDoubleNaNFail:
-; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-NOPCREL-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-NOPCREL-NEXT:    lxvx vs34, 0, r3
-; CHECK-NOPCREL-NEXT:    blr
-
+; CHECK-LE-LABEL: testDoubleToDoubleNaNFail:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxsplti32dx vs34, 0, -1
+; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, -16
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-NOPCREL-BE-LABEL: testDoubleToDoubleNaNFail:
+; CHECK-NOPCREL-BE:       # %bb.0: # %entry
+; CHECK-NOPCREL-BE-NEXT:    xxsplti32dx vs34, 0, -1
+; CHECK-NOPCREL-BE-NEXT:    xxsplti32dx vs34, 1, -16
+; CHECK-NOPCREL-BE-NEXT:    blr
+;
+; CHECK-NOPCREL-LE-LABEL: testDoubleToDoubleNaNFail:
+; CHECK-NOPCREL-LE:       # %bb.0: # %entry
+; CHECK-NOPCREL-LE-NEXT:    xxsplti32dx vs34, 0, -1
+; CHECK-NOPCREL-LE-NEXT:    xxsplti32dx vs34, 1, -16
+; CHECK-NOPCREL-LE-NEXT:    blr
+;
+; CHECK-NOPREFIX-LABEL: testDoubleToDoubleNaNFail:
+; CHECK-NOPREFIX:       # %bb.0: # %entry
+; CHECK-NOPREFIX-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-NOPREFIX-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-NOPREFIX-NEXT:    lxvx vs34, 0, r3
+; CHECK-NOPREFIX-NEXT:    blr
+;
+; CHECK-BE-LABEL: testDoubleToDoubleNaNFail:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, -1
+; CHECK-BE-NEXT:    xxsplti32dx vs34, 1, -16
+; CHECK-BE-NEXT:    blr
 entry:
   ret <2 x double> <double 0xFFFFFFFFFFFFFFF0, double 0xFFFFFFFFFFFFFFF0>
 }
 
 define dso_local double @testDoubleNonRepresentableScalar() local_unnamed_addr {
-; CHECK-LABEL: testDoubleNonRepresentableScalar:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plfd f1, .LCPI3_0@PCREL(0), 1
-; CHECK-NEXT:    blr
-;
-; CHECK-NOPCREL-LABEL: testDoubleNonRepresentableScalar:
-; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-NOPCREL-NEXT:    lfd f1, .LCPI3_0@toc@l(r3)
-; CHECK-NOPCREL-NEXT:    blr
-
+; CHECK-LE-LABEL: testDoubleNonRepresentableScalar:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    plfd f1, .LCPI3_0@PCREL(0), 1
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-NOPCREL-BE-LABEL: testDoubleNonRepresentableScalar:
+; CHECK-NOPCREL-BE:       # %bb.0: # %entry
+; CHECK-NOPCREL-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-NOPCREL-BE-NEXT:    lfd f1, .LCPI3_0@toc@l(r3)
+; CHECK-NOPCREL-BE-NEXT:    blr
+;
+; CHECK-NOPCREL-LE-LABEL: testDoubleNonRepresentableScalar:
+; CHECK-NOPCREL-LE:       # %bb.0: # %entry
+; CHECK-NOPCREL-LE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-NOPCREL-LE-NEXT:    lfd f1, .LCPI3_0@toc@l(r3)
+; CHECK-NOPCREL-LE-NEXT:    blr
+;
+; CHECK-NOPREFIX-LABEL: testDoubleNonRepresentableScalar:
+; CHECK-NOPREFIX:       # %bb.0: # %entry
+; CHECK-NOPREFIX-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-NOPREFIX-NEXT:    lfd f1, .LCPI3_0@toc@l(r3)
+; CHECK-NOPREFIX-NEXT:    blr
+;
+; CHECK-BE-LABEL: testDoubleNonRepresentableScalar:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    plfd f1, .LCPI3_0@PCREL(0), 1
+; CHECK-BE-NEXT:    blr
 entry:
   ret double 3.423300e+02
 }
 
 define dso_local float @testFloatDenormScalar() local_unnamed_addr {
-; CHECK-LABEL: testFloatDenormScalar:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plfs f1, .LCPI4_0@PCREL(0), 1
-; CHECK-NEXT:    blr
-;
-; CHECK-NOPCREL-LABEL: testFloatDenormScalar:
-; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-NOPCREL-NEXT:    lfs f1, .LCPI4_0@toc@l(r3)
-; CHECK-NOPCREL-NEXT:    blr
-
+; CHECK-LE-LABEL: testFloatDenormScalar:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    plfs f1, .LCPI4_0@PCREL(0), 1
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-NOPCREL-BE-LABEL: testFloatDenormScalar:
+; CHECK-NOPCREL-BE:       # %bb.0: # %entry
+; CHECK-NOPCREL-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; CHECK-NOPCREL-BE-NEXT:    lfs f1, .LCPI4_0@toc@l(r3)
+; CHECK-NOPCREL-BE-NEXT:    blr
+;
+; CHECK-NOPCREL-LE-LABEL: testFloatDenormScalar:
+; CHECK-NOPCREL-LE:       # %bb.0: # %entry
+; CHECK-NOPCREL-LE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; CHECK-NOPCREL-LE-NEXT:    lfs f1, .LCPI4_0@toc@l(r3)
+; CHECK-NOPCREL-LE-NEXT:    blr
+;
+; CHECK-NOPREFIX-LABEL: testFloatDenormScalar:
+; CHECK-NOPREFIX:       # %bb.0: # %entry
+; CHECK-NOPREFIX-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; CHECK-NOPREFIX-NEXT:    lfs f1, .LCPI4_0@toc@l(r3)
+; CHECK-NOPREFIX-NEXT:    blr
+;
+; CHECK-BE-LABEL: testFloatDenormScalar:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    plfs f1, .LCPI4_0@PCREL(0), 1
+; CHECK-BE-NEXT:    blr
 entry:
   ret float 0x380B38FB80000000
 }
 
 define dso_local double @testFloatDenormToDoubleScalar() local_unnamed_addr {
-; CHECK-LABEL: testFloatDenormToDoubleScalar:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plfs f1, .LCPI5_0@PCREL(0), 1
-; CHECK-NEXT:    blr
-;
-; CHECK-NOPCREL-LABEL: testFloatDenormToDoubleScalar:
-; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-NOPCREL-NEXT:    lfs f1, .LCPI5_0@toc@l(r3)
-; CHECK-NOPCREL-NEXT:    blr
-
+; CHECK-LE-LABEL: testFloatDenormToDoubleScalar:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    plfs f1, .LCPI5_0@PCREL(0), 1
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-NOPCREL-BE-LABEL: testFloatDenormToDoubleScalar:
+; CHECK-NOPCREL-BE:       # %bb.0: # %entry
+; CHECK-NOPCREL-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-NOPCREL-BE-NEXT:    lfs f1, .LCPI5_0@toc@l(r3)
+; CHECK-NOPCREL-BE-NEXT:    blr
+;
+; CHECK-NOPCREL-LE-LABEL: testFloatDenormToDoubleScalar:
+; CHECK-NOPCREL-LE:       # %bb.0: # %entry
+; CHECK-NOPCREL-LE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-NOPCREL-LE-NEXT:    lfs f1, .LCPI5_0@toc@l(r3)
+; CHECK-NOPCREL-LE-NEXT:    blr
+;
+; CHECK-NOPREFIX-LABEL: testFloatDenormToDoubleScalar:
+; CHECK-NOPREFIX:       # %bb.0: # %entry
+; CHECK-NOPREFIX-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-NOPREFIX-NEXT:    lfs f1, .LCPI5_0@toc@l(r3)
+; CHECK-NOPREFIX-NEXT:    blr
+;
+; CHECK-BE-LABEL: testFloatDenormToDoubleScalar:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    plfs f1, .LCPI5_0@PCREL(0), 1
+; CHECK-BE-NEXT:    blr
 entry:
   ret double 0x380B38FB80000000
 }

llvm/test/CodeGen/PowerPC/p10-splatImm32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
-; RUN:     FileCheck --check-prefix=CHECK-LE %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
-; RUN:     FileCheck --check-prefix=CHECK-BE %s
+; RUN:     FileCheck %s
 
 ; Function Attrs: norecurse nounwind readnone
 define  <4 x i32> @test_xxsplti32dx_1(<4 x i32> %a) {
-; CHECK-LE-LABEL: test_xxsplti32dx_1:
-; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxsplti32dx vs34, 0, 566
-; CHECK-LE-NEXT:    blr
-;
-; CHECK-BE-LABEL: test_xxsplti32dx_1:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsplti32dx vs34, 1, 566
-; CHECK-BE-NEXT:    blr
+; CHECK-LABEL: test_xxsplti32dx_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx vs34, 0, 566
+; CHECK-NEXT:    blr
 entry:
   %vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 566, i32 undef, i32 566>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x i32> %vecins1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define  <4 x i32> @test_xxsplti32dx_2(<4 x i32> %a) {
-; CHECK-LE-LABEL: test_xxsplti32dx_2:
-; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, 33
-; CHECK-LE-NEXT:    blr
-;
-; CHECK-BE-LABEL: test_xxsplti32dx_2:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, 33
-; CHECK-BE-NEXT:    blr
+; CHECK-LABEL: test_xxsplti32dx_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx vs34, 1, 33
+; CHECK-NEXT:    blr
 entry:
   %vecins1 = shufflevector <4 x i32> <i32 33, i32 undef, i32 33, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x i32> %vecins1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define  <4 x i32> @test_xxsplti32dx_3(<4 x i32> %a) {
-; CHECK-LE-LABEL: test_xxsplti32dx_3:
-; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxsplti32dx vs34, 0, 12
-; CHECK-LE-NEXT:    blr
-;
-; CHECK-BE-LABEL: test_xxsplti32dx_3:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsplti32dx vs34, 1, 12
-; CHECK-BE-NEXT:    blr
+; CHECK-LABEL: test_xxsplti32dx_3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx vs34, 0, 12
+; CHECK-NEXT:    blr
 entry:
   %vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 12, i32 undef, i32 12>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x i32> %vecins1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define  <4 x i32> @test_xxsplti32dx_4(<4 x i32> %a) {
-; CHECK-LE-LABEL: test_xxsplti32dx_4:
-; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, -683
-; CHECK-LE-NEXT:    blr
-;
-; CHECK-BE-LABEL: test_xxsplti32dx_4:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, -683
-; CHECK-BE-NEXT:    blr
+; CHECK-LABEL: test_xxsplti32dx_4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx vs34, 1, -683
+; CHECK-NEXT:    blr
 entry:
   %vecins1 = shufflevector <4 x i32> <i32 -683, i32 undef, i32 -683, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x i32> %vecins1
 }
 
 ; Function Attrs: nounwind
 define  <4 x float> @test_xxsplti32dx_5(<4 x float> %vfa) {
-; CHECK-LE-LABEL: test_xxsplti32dx_5:
-; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxsplti32dx vs34, 0, 1065353216
-; CHECK-LE-NEXT:    blr
-;
-; CHECK-BE-LABEL: test_xxsplti32dx_5:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsplti32dx vs34, 1, 1065353216
-; CHECK-BE-NEXT:    blr
+; CHECK-LABEL: test_xxsplti32dx_5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx vs34, 0, 1065353216
+; CHECK-NEXT:    blr
 entry:
   %vecins3.i = shufflevector <4 x float> %vfa, <4 x float> <float undef, float 1.000000e+00, float undef, float 1.000000e+00>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x float> %vecins3.i
 }
 
 ; Function Attrs: nounwind
 define  <4 x float> @test_xxsplti32dx_6(<4 x float> %vfa) {
-; CHECK-LE-LABEL: test_xxsplti32dx_6:
-; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, 1073741824
-; CHECK-LE-NEXT:    blr
-;
-; CHECK-BE-LABEL: test_xxsplti32dx_6:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, 1073741824
-; CHECK-BE-NEXT:    blr
+; CHECK-LABEL: test_xxsplti32dx_6:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx vs34, 1, 1073741824
+; CHECK-NEXT:    blr
 entry:
   %vecins3.i = shufflevector <4 x float> <float 2.000000e+00, float undef, float 2.000000e+00, float undef>, <4 x float> %vfa, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x float> %vecins3.i
 }
 
 ; Function Attrs: norecurse nounwind readnone
 ; Test to illustrate when the splat is narrower than 32-bits.
 define dso_local <4 x i32> @test_xxsplti32dx_7(<4 x i32> %a) local_unnamed_addr #0 {
-; CHECK-LE-LABEL: test_xxsplti32dx_7:
-; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxsplti32dx vs34, 1, -1414812757
-; CHECK-LE-NEXT:    blr
-;
-; CHECK-BE-LABEL: test_xxsplti32dx_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsplti32dx vs34, 0, -1414812757
-; CHECK-BE-NEXT:    blr
+; CHECK-LABEL: test_xxsplti32dx_7:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx vs34, 1, -1414812757
+; CHECK-NEXT:    blr
 entry:
   %vecins1 = shufflevector <4 x i32> <i32 -1414812757, i32 undef, i32 -1414812757, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x i32> %vecins1
 }
+
+define dso_local <2 x double> @test_xxsplti32dx_8() {
+; CHECK-LABEL: test_xxsplti32dx_8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx vs34, 0, 1082660167
+; CHECK-NEXT:    xxsplti32dx vs34, 1, -1374389535
+; CHECK-NEXT:    blr
+entry:
+  ret <2 x double> <double 0x40881547AE147AE1, double 0x40881547AE147AE1>
+}
+
+define dso_local <8 x i16> @test_xxsplti32dx_9() {
+; CHECK-LABEL: test_xxsplti32dx_9:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx vs34, 0, 23855277
+; CHECK-NEXT:    xxsplti32dx vs34, 1, 65827
+; CHECK-NEXT:    blr
+entry:
+  ret <8 x i16> <i16 291, i16 undef, i16 undef, i16 364, i16 undef, i16 1, i16 173, i16 undef>
+}