[TableGen] [AMDGPU] Add !sub bang operator for subtraction

[Paul-C-Anagnostopoulos]

Summary

In my travels through TableGen and the backends, I came across:

foreach Index = Indexes<!add(33, !mul(Size, -1))>.slice in {

To clean this up, I changed it to:

foreach Index = Indexes<!sub(33, Size)>.slice in {

Only then did I finally realize that there is no subtraction bang operator. So there is now.

I also used this opportunity to change the old '-' range punctuation to '...'.

[foad]

I like it.

llvm/docs/TableGen/ProgRef.rst

1667

Can you improve this description so that I can understand what it does if there are more than two operands please? :) (I guess it probably follows the LISP precedent where (- a b c d) is (- a (+ b c d))?)

[Paul-C-Anagnostopoulos]

llvm/docs/TableGen/ProgRef.rst

1667

Thank you for asking this question! In fact, it does something silly, so I will not allow more than two arguments.

[Paul-C-Anagnostopoulos]

Changed !sub so it takes only two arguments.

[foad]

llvm/test/TableGen/arithmetic.td

30–35

Nit: choose two numbers for which !sub and !xor give different results? And preferably !srl and !sra too.

[Paul-C-Anagnostopoulos]

llvm/test/TableGen/arithmetic.td

30–35

Good idea. I will do that.

[Paul-C-Anagnostopoulos]

Improve the arithmetic.td test so all results are different.

[Paul-C-Anagnostopoulos]

I will auto-LGTM this revision on Wednesday.

[madhur13490]

llvm/docs/TableGen/ProgRef.rst

1667

nit; ".. and produces the arithmetic difference"

llvm/lib/TableGen/TGParser.cpp

1259

I think the condition can be moved to a separate function before it becomes unmanageable.

[Paul-C-Anagnostopoulos]

llvm/lib/TableGen/TGParser.cpp

1259

There are complex conditions like this all over TableGen.

llvm/docs/TableGen/ProgRef.rst

 
 .. productionlist::
    BangOperator: one of
                : !add        !and         !cast        !con         !dag
                : !empty      !eq          !foldl       !foreach     !ge
                : !getdagop   !gt          !head        !if          !isa
                : !le         !listconcat  !listsplat   !lt          !mul
                : !ne         !not         !or          !setdagop    !shl
-               : !size       !sra         !srl         !strconcat   !subst
-               : !tail       !xor
+               : !size       !sra         !srl         !strconcat   !sub
+               : !subst      !tail        !xor
 
 The ``!cond`` operator has a slightly different
 syntax compared to other bang operators, so it is defined separately:
 
 .. productionlist::
    CondOperator: !cond
 
 See `Appendix A: Bang Operators`_ for a description of each bang operator.
``!strconcat(``\ *str1*\ ``,`` *str2*\ ``, ...)``
     produces the resulting string.
 
 *str1*\ ``#``\ *str2*
     The paste operator (``#``) is a shorthand for
     ``!strconcat`` with two arguments.  It can be used to concatenate operands that
     are not strings, in which
     case an implicit ``!cast<string>`` is done on those operands.
 
+``!sub(``\ *a*\ ``,`` *b*\ ``)``
+    This operator subtracts *b* from *a* and produces the arithmetic difference.
+
 ``!subst(``\ *target*\ ``,`` *repl*\ ``,`` *value*\ ``)``
     This operator replaces all occurrences of the *target* in the *value* with
     the *repl* and produces the resulting value. The *value* can
     be a string, in which case substring substitution is performed.
 
     The *value* can be a record name, in which case the operator produces the *repl*
     record if the *target* record name equals the *value* record name; otherwise it
     produces the *value*.

llvm/include/llvm/TableGen/Record.h

public:
   Init *resolveReferences(Resolver &R) const override;
 
   std::string getAsString() const override;
 };
 
 /// !op (X, Y) - Combine two inits.
 class BinOpInit : public OpInit, public FoldingSetNode {
 public:
-  enum BinaryOp : uint8_t { ADD, MUL, AND, OR, XOR, SHL, SRA, SRL, LISTCONCAT,
+  enum BinaryOp : uint8_t { ADD, SUB, MUL, AND, OR, XOR, SHL, SRA, SRL, LISTCONCAT,
                             LISTSPLAT, STRCONCAT, CONCAT, EQ, NE, LE, LT, GE,
                             GT, SETDAGOP };
 
 private:
   Init *LHS, *RHS;
 
   BinOpInit(BinaryOp opc, Init *lhs, Init *rhs, RecTy *Type) :
       OpInit(IK_BinOpInit, Type, opc), LHS(lhs), RHS(rhs) {}

llvm/lib/TableGen/Record.cpp

if (Dag && Op) {
         Args.push_back(Dag->getArg(i));
         ArgNames.push_back(Dag->getArgName(i));
       }
       return DagInit::get(Op, nullptr, Args, ArgNames);
     }
     break;
   }
   case ADD:
+  case SUB:
   case MUL:
   case AND:
   case OR:
   case XOR:
   case SHL:
   case SRA:
   case SRL: {
     IntInit *LHSi =
       dyn_cast_or_null<IntInit>(LHS->convertInitializerTo(IntRecTy::get()));
     IntInit *RHSi =
       dyn_cast_or_null<IntInit>(RHS->convertInitializerTo(IntRecTy::get()));
     if (LHSi && RHSi) {
       int64_t LHSv = LHSi->getValue(), RHSv = RHSi->getValue();
       int64_t Result;
       switch (getOpcode()) {
       default: llvm_unreachable("Bad opcode!");
-      case ADD: Result = LHSv +  RHSv; break;
-      case MUL: Result = LHSv *  RHSv; break;
-      case AND: Result = LHSv &  RHSv; break;
+      case ADD: Result = LHSv + RHSv; break;
+      case SUB: Result = LHSv - RHSv; break;
+      case MUL: Result = LHSv * RHSv; break;
+      case AND: Result = LHSv & RHSv; break;
       case OR:  Result = LHSv | RHSv; break;
       case XOR: Result = LHSv ^ RHSv; break;
       case SHL: Result = (uint64_t)LHSv << (uint64_t)RHSv; break;
       case SRA: Result = LHSv >> RHSv; break;
       case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
       }
       return IntInit::get(Result);
     }
Init *BinOpInit::resolveReferences(Resolver &R) const {
   return const_cast<BinOpInit *>(this);
 }
 
 std::string BinOpInit::getAsString() const {
   std::string Result;
   switch (getOpcode()) {
   case CONCAT: Result = "!con"; break;
   case ADD: Result = "!add"; break;
+  case SUB: Result = "!sub"; break;
   case MUL: Result = "!mul"; break;
   case AND: Result = "!and"; break;
   case OR: Result = "!or"; break;
   case XOR: Result = "!xor"; break;
   case SHL: Result = "!shl"; break;
   case SRA: Result = "!sra"; break;
   case SRL: Result = "!srl"; break;
   case EQ: Result = "!eq"; break;

llvm/lib/TableGen/TGLexer.h

enum TokKind {
     dotdotdot,          // ...
 
     // Keywords. ('ElseKW' is named to distinguish it from the existing 'Else'
     // that means the preprocessor #else.)
     Bit, Bits, Class, Code, Dag, Def, Foreach, Defm, Field, In, Int, Let, List,
     MultiClass, String, Defset, Defvar, If, Then, ElseKW,
 
     // !keywords.
-    XConcat, XADD, XMUL, XNOT, XAND, XOR, XXOR, XSRA, XSRL, XSHL,
+    XConcat, XADD, XSUB, XMUL, XNOT, XAND, XOR, XXOR, XSRA, XSRL, XSHL,
     XListConcat, XListSplat, XStrConcat, XCast, XSubst, XForEach, XFoldl,
     XHead, XTail, XSize, XEmpty, XIf, XCond, XEq, XIsA, XDag, XNe, XLe,
     XLt, XGe, XGt, XSetDagOp, XGetDagOp,
 
     // Integer value.
     IntVal,
 
     // Binary constant.  Note that these are sized according to the number of

llvm/lib/TableGen/TGLexer.cpp

tgtok::TokKind Kind =
     .Case("cond", tgtok::XCond)
     .Case("isa", tgtok::XIsA)
     .Case("head", tgtok::XHead)
     .Case("tail", tgtok::XTail)
     .Case("size", tgtok::XSize)
     .Case("con", tgtok::XConcat)
     .Case("dag", tgtok::XDag)
     .Case("add", tgtok::XADD)
+    .Case("sub", tgtok::XSUB)
     .Case("mul", tgtok::XMUL)
     .Case("not", tgtok::XNOT)
     .Case("and", tgtok::XAND)
     .Case("or", tgtok::XOR)
     .Case("xor", tgtok::XXOR)
     .Case("shl", tgtok::XSHL)
     .Case("sra", tgtok::XSRA)
     .Case("srl", tgtok::XSRL)

llvm/lib/TableGen/TGParser.cpp

if (!consume(tgtok::r_paren)) {
       return nullptr;
     }
 
     return (IsAOpInit::get(Type, LHS))->Fold();
   }
 
   case tgtok::XConcat:
   case tgtok::XADD:
+  case tgtok::XSUB:
   case tgtok::XMUL:
   case tgtok::XAND:
   case tgtok::XOR:
   case tgtok::XXOR:
   case tgtok::XSRA:
   case tgtok::XSRL:
   case tgtok::XSHL:
   case tgtok::XEq:
case tgtok::XSetDagOp: { // Value ::= !binop '(' Value ',' Value ')'
     SMLoc OpLoc = Lex.getLoc();
     Lex.Lex();  // eat the operation
 
     BinOpInit::BinaryOp Code;
     switch (OpTok) {
     default: llvm_unreachable("Unhandled code!");
     case tgtok::XConcat: Code = BinOpInit::CONCAT; break;
     case tgtok::XADD:    Code = BinOpInit::ADD; break;
+    case tgtok::XSUB:    Code = BinOpInit::SUB; break;
     case tgtok::XMUL:    Code = BinOpInit::MUL; break;
     case tgtok::XAND:    Code = BinOpInit::AND; break;
     case tgtok::XOR:     Code = BinOpInit::OR; break;
     case tgtok::XXOR:    Code = BinOpInit::XOR; break;
     case tgtok::XSRA:    Code = BinOpInit::SRA; break;
     case tgtok::XSRL:    Code = BinOpInit::SRL; break;
     case tgtok::XSHL:    Code = BinOpInit::SHL; break;
     case tgtok::XEq:     Code = BinOpInit::EQ; break;
case tgtok::XSetDagOp:
       break;
     case tgtok::XAND:
     case tgtok::XOR:
     case tgtok::XXOR:
     case tgtok::XSRA:
     case tgtok::XSRL:
     case tgtok::XSHL:
     case tgtok::XADD:
+    case tgtok::XSUB:
     case tgtok::XMUL:
       Type = IntRecTy::get();
       ArgType = IntRecTy::get();
       break;
     case tgtok::XEq:
     case tgtok::XNe:
       Type = BitRecTy::get();
       // ArgType for Eq / Ne is not known at this point
for (;;) {
       } else {
         RecTy *Resolved = resolveTypes(ArgType, ListType);
         if (!Resolved) {
           Error(InitLoc, Twine("expected value of type '") +
                              ArgType->getAsString() + "', got '" +
                              ListType->getAsString() + "'");
           return nullptr;
         }
-        if (Code != BinOpInit::ADD && Code != BinOpInit::AND &&
-            Code != BinOpInit::OR && Code != BinOpInit::XOR &&
-            Code != BinOpInit::SRA && Code != BinOpInit::SRL &&
-            Code != BinOpInit::SHL && Code != BinOpInit::MUL)
+        if (Code != BinOpInit::ADD && Code != BinOpInit::SUB &&
+            Code != BinOpInit::AND && Code != BinOpInit::OR &&
+            Code != BinOpInit::XOR && Code != BinOpInit::SRA &&
+            Code != BinOpInit::SRL && Code != BinOpInit::SHL &&
+            Code != BinOpInit::MUL)
           ArgType = Resolved;
       }
 
       // Deal with BinOps whose arguments have different types, by
       // rewriting ArgType in between them.
       switch (Code) {
         case BinOpInit::SETDAGOP:
           // After parsing the first dag argument, switch to expecting

 ///   SimpleValue ::= CODEFRAGMENT
 ///   SimpleValue ::= '?'
 ///   SimpleValue ::= '{' ValueList '}'
 ///   SimpleValue ::= ID '<' ValueListNE '>'
 ///   SimpleValue ::= '[' ValueList ']'
 ///   SimpleValue ::= '(' IDValue DagArgList ')'
 ///   SimpleValue ::= CONCATTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= ADDTOK '(' Value ',' Value ')'
+///   SimpleValue ::= SUBTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= SHLTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= SRATOK '(' Value ',' Value ')'
 ///   SimpleValue ::= SRLTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= LISTCONCATTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= LISTSPLATTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= STRCONCATTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= COND '(' [Value ':' Value,]+ ')'
 ///
Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType,
   case tgtok::XSize:
   case tgtok::XEmpty:
   case tgtok::XCast:
   case tgtok::XGetDagOp: // Value ::= !unop '(' Value ')'
   case tgtok::XIsA:
   case tgtok::XConcat:
   case tgtok::XDag:
   case tgtok::XADD:
+  case tgtok::XSUB:
   case tgtok::XMUL:
   case tgtok::XNOT:
   case tgtok::XAND:
   case tgtok::XOR:
   case tgtok::XXOR:
   case tgtok::XSRA:
   case tgtok::XSRL:
   case tgtok::XSHL:

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

!foldl([]<int>, all, acc, cur,
            !listconcat(acc, !if(!lt(cur, N), [cur], [])));
 }
 
 let Namespace = "AMDGPU" in {
 
 def lo16 : SubRegIndex<16, 0>;
 def hi16 : SubRegIndex<16, 16>;
 
-foreach Index = 0-31 in {
+foreach Index = 0...31 in {
   def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
-foreach Index = 1-31 in {
+foreach Index = 1...31 in {
   def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>;
   def sub#Index#_hi16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), hi16>;
 }
 
-foreach Size = {2-6,8,16} in {
-  foreach Index = Indexes<!add(33, !mul(Size, -1))>.slice in {
+foreach Size = {2...6,8,16} in {
+  foreach Index = Indexes<!sub(33, Size)>.slice in {
     def !foldl("", Indexes<Size>.slice, acc, cur,
                !strconcat(acc#!if(!eq(acc,""),"","_"), "sub"#!add(cur, Index))) :
       SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {
       let CoveringSubRegIndices =
         !foldl([]<SubRegIndex>, Indexes<Size>.slice, acc, cur,
                !listconcat(acc, [!cast<SubRegIndex>(sub#!add(cur, Index))]));
     }
   }
list<SubRegIndex> ret = !if(!eq(size, 2), ret2,
                                                       ret32)))))));
 }
 
 // Generates list of sequential register tuple names.
 // E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ]
 class RegSeqNames<int last_reg, int stride, int size, string prefix,
                   int start = 0> {
   int next = !add(start, stride);
-  int end_reg = !add(!add(start, size), -1);
+  int end_reg = !add(start, size, -1);
   list<string> ret =
     !if(!le(end_reg, last_reg),
         !listconcat([prefix # "[" # start # ":" # end_reg # "]"],
                     RegSeqNames<last_reg, stride, size, prefix, next>.ret),
                     []);
 }
 
 // Generates list of dags for register tupless.
 class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size,
                 int start = 0> {
   dag trunc_rc = (trunc RC,
                   !if(!and(!eq(stride, 1), !eq(start, 0)),
-                      !add(!add(last_reg, 2), !mul(size, -1)),
+                      !sub(!add(last_reg, 2), size),
                       !add(last_reg, 1)));
   list<dag> ret =
     !if(!lt(start, size),
         !listconcat([(add (decimate (shl trunc_rc, start), stride))],
                     RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret),
         []);
 }
 

 defm TMA_HI : SIRegLoHi16<"tma_hi", 111>;
 
 def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = 110;
 }
 
-foreach Index = 0-15 in {
+foreach Index = 0...15 in {
   defm TTMP#Index#_vi         : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>;
   defm TTMP#Index#_gfx9_gfx10 : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>;
   defm TTMP#Index             : SIRegLoHi16<"ttmp"#Index, 0>;
 }
 
 multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
   defm _ci : SIRegLoHi16<n, ci_e>;
   defm _vi : SIRegLoHi16<n, vi_e>;

 defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes.
 defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes.
 
 def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>;
 def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>;
 def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
 
 // SGPR registers
-foreach Index = 0-105 in {
+foreach Index = 0...105 in {
   defm SGPR#Index :
      SIRegLoHi16 <"s"#Index, Index>,
      DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
                   !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
 }
 
 // VGPR registers
-foreach Index = 0-255 in {
+foreach Index = 0...255 in {
   defm VGPR#Index :
     SIRegLoHi16 <"v"#Index, Index, 0, 1>,
     DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>;
 }
 
 // AccVGPR registers
-foreach Index = 0-255 in {
+foreach Index = 0...255 in {
   defm AGPR#Index :
       SIRegLoHi16 <"a"#Index, Index, 1, 1>,
       DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>;
 }
 
 //===----------------------------------------------------------------------===//
 //  Groupings using register classes and tuples
 //===----------------------------------------------------------------------===//

 
 def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">;
 
 def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">;
 
 class TmpRegTuplesBase<int index, int size,
                        list<Register> subRegs,
                        list<SubRegIndex> indices = getSubRegs<size>.ret,
-                       int index1 = !add(index, !add(size, -1)),
+                       int index1 = !add(index, size, -1),
                        string name = "ttmp["#index#":"#index1#"]"> :
   RegisterWithSubRegs<name, subRegs> {
   let HWEncoding = subRegs[0].HWEncoding;
   let SubRegIndices = indices;
 }
 
 class TmpRegTuples<string tgt,
                    int size,

llvm/test/TableGen/arithmetic.td

 // RUN: llvm-tblgen %s | FileCheck %s
 // XFAIL: vg_leak
 
 // CHECK: --- Defs ---
 
 // CHECK: def A0 {
-// CHECK:   bits<8> add = { 0, 1, 0, 0, 0, 0, 0, 0 };
+// CHECK:   bits<8> add = { 0, 0, 0, 1, 1, 0, 0, 0 };
+// CHECK:   bits<8> sub = { 0, 0, 0, 1, 0, 0, 1, 0 };
 // CHECK:   bits<8> and = { 0, 0, 0, 0, 0, 0, 0, 1 };
-// CHECK:   bits<8> or =  { 0, 0, 1, 1, 1, 1, 1, 1 };
-// CHECK:   bits<8> xor = { 0, 0, 1, 1, 1, 1, 1, 0 };
-// CHECK:   bits<8> srl = { 0, 0, 0, 1, 1, 1, 1, 1 };
-// CHECK:   bits<8> sra = { 0, 0, 0, 1, 1, 1, 1, 1 };
-// CHECK:   bits<8> shl = { 0, 1, 1, 1, 1, 1, 1, 0 };
-// CHECK: }
+// CHECK:   bits<8> or = { 0, 0, 0, 1, 0, 1, 1, 1 };
+// CHECK:   bits<8> xor = { 0, 0, 0, 1, 0, 1, 1, 0 };
+// CHECK:   bits<8> srl = { 0, 0, 0, 0, 0, 0, 1, 0 };
+// CHECK:   bits<8> sra = { 0, 0, 0, 0, 0, 0, 1, 0 };
+// CHECK:   bits<8> shl = { 1, 0, 1, 0, 1, 0, 0, 0 };
+
+// CHECK:   bits<8> sra = { 1, 1, 1, 1, 1, 1, 1, 1 };
 
 class A<bits<8> a, bits<2> b> {
   // Operands of different bits types are allowed.
   bits<8> add = !add(a, b);
+  bits<8> sub = !sub(a, b);
   bits<8> and = !and(a, b);
-  bits<8> or = !or(a, b);
+  bits<8> or =  !or(a, b);
   bits<8> xor = !xor(a, b);
   bits<8> srl = !srl(a, b);
   bits<8> sra = !sra(a, b);
   bits<8> shl = !shl(a, b);
 }
 
-def A0 : A<63, 1>;
+def A0 : A<21, 3>;
+
+def A1 {
+  bits<8> sra = !sra(-1, 3);
+}
+

llvm/test/TableGen/math.td

 // RUN: llvm-tblgen %s | FileCheck %s
 // XFAIL: vg_leak
 
+// CHECK: def shifts
+// CHECK: shifted_b = 8
+// CHECK: shifted_i = 8
 def shifts {
     bits<2> b = 0b10;
     int i = 2;
     int shifted_b = !shl(b, 2);
     int shifted_i = !shl(i, 2);
 }
-// CHECK: def shifts
-// CHECK: shifted_b = 8
-// CHECK: shifted_i = 8
 
 class Int<int value> {
   int Value = value;
 }
 
-def v1022   : Int<1022>;
+def int2 : Int<2>;
+def int1022 : Int<1022>;
+def int1024 : Int<1024>;
 
-// CHECK: def v0
+// CHECK: def v0a
 // CHECK: Value = 0
+def v0a : Int<!sub(int1024.Value, int1024.Value)>;
+
+// CHECK: def v0b
+// CHECK: Value = 0
+def v0b : Int<!and(int1024.Value, 2048)>;
 
 // CHECK: def v1
 // CHECK: Value = 1
+def v1 : Int<!and(1025, 1)>;
+
+// CHECK: def v1019
+// CHECK: Value = 1019
+def v1019 : Int<!sub(int1022.Value, 3)>;
 
 // CHECK: def v1023
 // CHECK: Value = 1023
-def v1023 : Int<!or(v1022.Value, 1)>;
-
-def v1024   : Int<1024>;
-// CHECK: def v1024
-// CHECK: Value = 1024
+def v1023 : Int<!or(int1022.Value, 1)>;
 
-def v1025   : Int<!add(v1024.Value, 1)>;
+def v1025   : Int<!add(int1024.Value, 1)>;
 // CHECK: def v1025
 // CHECK: Value = 1025
 
 // CHECK: def v12
 // CHECK: Value = 12
 def v12   : Int<!mul(4, 3)>;
 
 // CHECK: def v1a
 // CHECK: Value = 1
 
-// CHECK: def v2
-// CHECK: Value = 2
-def v2 : Int<2>;
-
-def v2048   : Int<!add(v1024.Value, v1024.Value)>;
 // CHECK: def v2048
 // CHECK: Value = 2048
-
-def v0 : Int<!and(v1024.Value, v2048.Value)>;
-def v1 : Int<!and(v1025.Value, 1)>;
+def v2048   : Int<!add(int1024.Value, int1024.Value)>;
 
 // CHECK: def v3072
 // CHECK: Value = 3072
-def v3072 : Int<!or(v1024.Value, v2048.Value)>;
+def v3072 : Int<!or(int1024.Value, v2048.Value)>;
 
 // CHECK: def v4
 // CHECK: Value = 4
 
 // CHECK: def v7
 // CHECK: Value = 7
 
-def v4 : Int<!add(v2.Value, 1, v1.Value)>;
-def v7 : Int<!or(v1.Value, v2.Value, v4.Value)>;
+def v4 : Int<!add(int2.Value, 1, v1.Value)>;
+def v7 : Int<!or(v1.Value, int2.Value, v4.Value)>;
 def v1a : Int<!and(v7.Value, 5, v1.Value)>;
 
 // CHECK: def v84
 // CHECK: Value = 84
 def v84   : Int<!mul(v12.Value, v7.Value)>;
 
 // CHECK: def v9
 // CHECK: Value = 9
 def v9 : Int<!xor(v7.Value, 0x0E)>;
 
 // CHECK: def v924
 // CHECK: Value = 924
 def v924   : Int<!mul(v84.Value, 11)>;
 
-
+// CHECK: def v925
+// CHECK: Value = 925
+def v925 : Int<!sub(v924.Value, -1)>;
+
+// CHECK: def vneg
+// CHECK: Value = -2
+def vneg : Int<!sub(v925.Value, 927)>;
 No newline at end of file