[AMDGPU] Allow SOP asm mnemonic to differ

[Joe_Nash]

Summary

Allows the creation of real SOP1 instructions with
assembler mnemonics that differ from their
pseudo-instruction mnemonics. The default behavior
keeps the mnemonics matching.

Corrects a subtarget label typo in a comment.

[rampitec]

LGTM

[Joe_Nash]

I do not have commit access, please commit the patch for me.

[rampitec]

In D88708#2307437, @Joe_Nash wrote:

I do not have commit access, please commit the patch for me.

I will commit it shortly.

llvm/lib/Target/AMDGPU/SOPInstructions.td

class SOP1_Pseudo <string opName, dag outs, dag ins,
   let SchedRW = [WriteSALU];
   let Size = 4;
   let UseNamedOperandTable = 1;
 
   bits<1> has_src0 = 1;
   bits<1> has_sdst = 1;
 }
 
-class SOP1_Real<bits<8> op, SOP1_Pseudo ps> :
+class SOP1_Real<bits<8> op, SOP1_Pseudo ps, string real_name = ps.Mnemonic> :
   InstSI <ps.OutOperandList, ps.InOperandList,
-          ps.Mnemonic # " " # ps.AsmOperands, []>,
+          real_name # " " # ps.AsmOperands, []>,
   Enc32 {
 
   let isPseudo = 0;
   let isCodeGenOnly = 0;
   let Size = 4;
 
   // copy relevant pseudo op flags
   let SubtargetPredicate = ps.SubtargetPredicate;

 defm S_CMPK_LE_U32      : SOPK_Real32_gfx6_gfx7_gfx10<0x00e>;
 defm S_ADDK_I32         : SOPK_Real32_gfx6_gfx7_gfx10<0x00f>;
 defm S_MULK_I32         : SOPK_Real32_gfx6_gfx7_gfx10<0x010>;
 defm S_GETREG_B32       : SOPK_Real32_gfx6_gfx7_gfx10<0x012>;
 defm S_SETREG_B32       : SOPK_Real32_gfx6_gfx7_gfx10<0x013>;
 defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>;
 
 //===----------------------------------------------------------------------===//
-// GFX8, GFX9 (VI).
+// GFX8 (VI), GFX9.
 //===----------------------------------------------------------------------===//
 
 class Select_vi<string opName> :
   SIMCInstr<opName, SIEncodingFamily.VI> {
   Predicate AssemblerPredicate = isGFX8GFX9;
   string DecoderNamespace = "GFX8";
 }