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Differential D88548

Fix limit behavior of dynamic alloca
ClosedPublic

Authored by serge-sans-paille on Sep 30 2020, 3:12 AM.

Details

Reviewers
jankratochvil
efriedma
lkail
Commits
rG9573c9f2a363: Fix limit behavior of dynamic alloca
Summary

When the allocation size is 0, we shouldn't probe. Within [1, PAGE_SIZE], we should probe once etc.




This fixes https://bugs.llvm.org/show_bug.cgi?id=47657
Diff Detail
Event Timeline
serge-sans-paille created this revision.Sep 30 2020, 3:12 AM
Herald added a project: Restricted Project.  ·  View Herald TranscriptSep 30 2020, 3:12 AM
Herald added subscribers: llvm-commits, hiraditya.  ·  View Herald Transcript
serge-sans-paille requested review of this revision.Sep 30 2020, 3:12 AM
serge-sans-paille added reviewers: jankratochvil, efriedma, lkail.Sep 30 2020, 4:12 AM
efriedma accepted this revision.Sep 30 2020, 12:23 PM
LGTM
This revision is now accepted and ready to land.Sep 30 2020, 12:23 PM
Closed by commit rG9573c9f2a363: Fix limit behavior of dynamic alloca (authored by serge-sans-paille).  ·  Explain WhyOct 2 2020, 2:10 AM
This revision was automatically updated to reflect the committed changes.
serge-sans-paille added a commit: rG9573c9f2a363: Fix limit behavior of dynamic alloca.
cuviper mentioned this in D90216: [stack-clash] Fix probing of dynamic alloca.Oct 27 2020, 1:26 PM
Revision Contents
PathSize
llvm/
lib/
Target/
X86/
2 lines
test/
CodeGen/
X86/
8 lines
Diff 295217
llvm/lib/Target/X86/X86ISelLowering.cpp
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 32,209 Lines • ▼ Show 20 LinesX86TargetLowering::EmitLoweredProbedAlloca(MachineInstr &MI,




  BuildMI(testMBB, DL,
  BuildMI(testMBB, DL,

          TII->get(TFI.Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
          TII->get(TFI.Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))

      .addReg(FinalStackPtr)
      .addReg(FinalStackPtr)

      .addReg(physSPReg);
      .addReg(physSPReg);




  BuildMI(testMBB, DL, TII->get(X86::JCC_1))
  BuildMI(testMBB, DL, TII->get(X86::JCC_1))

      .addMBB(tailMBB)
      .addMBB(tailMBB)

      .addImm(X86::COND_L);
      .addImm(X86::COND_LE);

  testMBB->addSuccessor(blockMBB);
  testMBB->addSuccessor(blockMBB);

  testMBB->addSuccessor(tailMBB);
  testMBB->addSuccessor(tailMBB);




  // Touch the block then extend it. This is done on the opposite side of
  // Touch the block then extend it. This is done on the opposite side of

  // static probe where we allocate then touch, to avoid the need of probing the
  // static probe where we allocate then touch, to avoid the need of probing the

  // tail of the static alloca. Possible scenarios are:
  // tail of the static alloca. Possible scenarios are:

  //
  //

  //       + ---- <- ------------ <- ------------- <- ------------ +
  //       + ---- <- ------------ <- ------------- <- ------------ +

▲ Show 20 Lines • Show All 18,851 Lines • Show Last 20 Lines
llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll
Show All 18 Lines
; CHECK-X86-64-NEXT:    movq  %rsp, %rbp
; CHECK-X86-64-NEXT:    movq  %rsp, %rbp

; CHECK-X86-64-NEXT:    .cfi_def_cfa_register %rbp
; CHECK-X86-64-NEXT:    .cfi_def_cfa_register %rbp

; CHECK-X86-64-NEXT:    movq    %rsp, %rax
; CHECK-X86-64-NEXT:    movq    %rsp, %rax

; CHECK-X86-64-NEXT:    movl    %edi, %ecx
; CHECK-X86-64-NEXT:    movl    %edi, %ecx

; CHECK-X86-64-NEXT:    leaq 15(,%rcx,4), %rcx
; CHECK-X86-64-NEXT:    leaq 15(,%rcx,4), %rcx

; CHECK-X86-64-NEXT:    andq  $-16, %rcx
; CHECK-X86-64-NEXT:    andq  $-16, %rcx

; CHECK-X86-64-NEXT:    subq  %rcx, %rax
; CHECK-X86-64-NEXT:    subq  %rcx, %rax

; CHECK-X86-64-NEXT:    cmpq  %rsp, %rax
; CHECK-X86-64-NEXT:    cmpq  %rsp, %rax

; CHECK-X86-64-NEXT:    jl  .LBB0_3
; CHECK-X86-64-NEXT:    jle .LBB0_3

; CHECK-X86-64-NEXT:  .LBB0_2: # =>This Inner Loop Header: Depth=1
; CHECK-X86-64-NEXT:  .LBB0_2: # =>This Inner Loop Header: Depth=1

; CHECK-X86-64-NEXT:    movq  $0, (%rsp)
; CHECK-X86-64-NEXT:    movq  $0, (%rsp)

; CHECK-X86-64-NEXT:    subq  $4096, %rsp # imm = 0x1000
; CHECK-X86-64-NEXT:    subq  $4096, %rsp # imm = 0x1000

; CHECK-X86-64-NEXT:    cmpq  %rsp, %rax
; CHECK-X86-64-NEXT:    cmpq  %rsp, %rax

; CHECK-X86-64-NEXT:    jge .LBB0_2
; CHECK-X86-64-NEXT:    jg  .LBB0_2

; CHECK-X86-64-NEXT:  .LBB0_3:
; CHECK-X86-64-NEXT:  .LBB0_3:

; CHECK-X86-64-NEXT:    movq  %rax, %rsp
; CHECK-X86-64-NEXT:    movq  %rax, %rsp

; CHECK-X86-64-NEXT:    movl  $1, 4792(%rax)
; CHECK-X86-64-NEXT:    movl  $1, 4792(%rax)

; CHECK-X86-64-NEXT:    movl  (%rax), %eax
; CHECK-X86-64-NEXT:    movl  (%rax), %eax

; CHECK-X86-64-NEXT:    movq  %rbp, %rsp
; CHECK-X86-64-NEXT:    movq  %rbp, %rsp

; CHECK-X86-64-NEXT:    popq  %rbp
; CHECK-X86-64-NEXT:    popq  %rbp

; CHECK-X86-64-NEXT:  .cfi_def_cfa %rsp, 8
; CHECK-X86-64-NEXT:  .cfi_def_cfa %rsp, 8

; CHECK-X86-64-NEXT:   retq
; CHECK-X86-64-NEXT:   retq







; CHECK-X86-32-LABEL: foo:
; CHECK-X86-32-LABEL: foo:

; CHECK-X86-32:       # %bb.0:
; CHECK-X86-32:       # %bb.0:

; CHECK-X86-32-NEXT:    pushl   %ebp
; CHECK-X86-32-NEXT:    pushl   %ebp

; CHECK-X86-32-NEXT:    .cfi_def_cfa_offset 8
; CHECK-X86-32-NEXT:    .cfi_def_cfa_offset 8

; CHECK-X86-32-NEXT:    .cfi_offset %ebp, -8
; CHECK-X86-32-NEXT:    .cfi_offset %ebp, -8

; CHECK-X86-32-NEXT:    movl    %esp, %ebp
; CHECK-X86-32-NEXT:    movl    %esp, %ebp

; CHECK-X86-32-NEXT:    .cfi_def_cfa_register %ebp
; CHECK-X86-32-NEXT:    .cfi_def_cfa_register %ebp

; CHECK-X86-32-NEXT:    subl    $8, %esp
; CHECK-X86-32-NEXT:    subl    $8, %esp

; CHECK-X86-32-NEXT:    movl    8(%ebp), %ecx
; CHECK-X86-32-NEXT:    movl    8(%ebp), %ecx

; CHECK-X86-32-NEXT:    movl    %esp, %eax
; CHECK-X86-32-NEXT:    movl    %esp, %eax

; CHECK-X86-32-NEXT:    leal    15(,%ecx,4), %ecx
; CHECK-X86-32-NEXT:    leal    15(,%ecx,4), %ecx

; CHECK-X86-32-NEXT:    andl    $-16, %ecx
; CHECK-X86-32-NEXT:    andl    $-16, %ecx

; CHECK-X86-32-NEXT:    subl    %ecx, %eax
; CHECK-X86-32-NEXT:    subl    %ecx, %eax

; CHECK-X86-32-NEXT:    cmpl    %esp, %eax
; CHECK-X86-32-NEXT:    cmpl    %esp, %eax

; CHECK-X86-32-NEXT:    jl  .LBB0_3
; CHECK-X86-32-NEXT:    jle  .LBB0_3

; CHECK-X86-32-NEXT:  .LBB0_2: # =>This Inner Loop Header: Depth=1
; CHECK-X86-32-NEXT:  .LBB0_2: # =>This Inner Loop Header: Depth=1

; CHECK-X86-32-NEXT:    movl    $0, (%esp)
; CHECK-X86-32-NEXT:    movl    $0, (%esp)

; CHECK-X86-32-NEXT:    subl    $4096, %esp # imm = 0x1000
; CHECK-X86-32-NEXT:    subl    $4096, %esp # imm = 0x1000

; CHECK-X86-32-NEXT:    cmpl    %esp, %eax
; CHECK-X86-32-NEXT:    cmpl    %esp, %eax

; CHECK-X86-32-NEXT:    jge .LBB0_2
; CHECK-X86-32-NEXT:    jg .LBB0_2

; CHECK-X86-32-NEXT:  .LBB0_3:
; CHECK-X86-32-NEXT:  .LBB0_3:

; CHECK-X86-32-NEXT:    movl    %eax, %esp
; CHECK-X86-32-NEXT:    movl    %eax, %esp

; CHECK-X86-32-NEXT:    movl    $1, 4792(%eax)
; CHECK-X86-32-NEXT:    movl    $1, 4792(%eax)

; CHECK-X86-32-NEXT:    movl    (%eax), %eax
; CHECK-X86-32-NEXT:    movl    (%eax), %eax

; CHECK-X86-32-NEXT:    movl    %ebp, %esp
; CHECK-X86-32-NEXT:    movl    %ebp, %esp

; CHECK-X86-32-NEXT:    popl    %ebp
; CHECK-X86-32-NEXT:    popl    %ebp

; CHECK-X86-32-NEXT:    .cfi_def_cfa %esp, 4
; CHECK-X86-32-NEXT:    .cfi_def_cfa %esp, 4

; CHECK-X86-32-NEXT:    retl
; CHECK-X86-32-NEXT:    retl