[ARM] Fix IT block generation after Thumb2SizeReduce with -Oz

[NickGuy]

Summary

Fixes a regression caused by D82439, in which IT blocks were no longer being generated when -Oz is present.

[NickGuy]

Rebased atop changes to https://reviews.llvm.org/D88494

[SjoerdMeijer]

llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.ll

3 ↗

(On Diff #299624)

I think a MIR test would be better here.

[NickGuy]

I think a MIR test would be better here.

Done

[SjoerdMeijer]

llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir

50

Not sure if I follow this codegen or what to expect, but every time I look at this patch I need to get up to speed again. But to help me, and to be a bit annoying, can you upload a diff with just the changes ? So, locally add this test first, and then create the diff against that.

[NickGuy]

I appreciate that the history and context for this has been a bit obscured. Most of it can be gathered on the patch D83667

can you upload a diff with just the changes ?

Done

[SjoerdMeijer]

Thanks, LGTM

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

 }
 
 bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI,
                                          std::vector<MachineOperand> &Pred,
                                          bool SkipDead) const {
   bool Found = false;
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI.getOperand(i);
-    if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
-        (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
+    bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR);
+    bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR;
+    if (ClobbersCPSR || IsCPSR) {
+
+      // Filter out T1 instructions that have a dead CPSR,
+      // allowing IT blocks to be generated containing T1 instructions
+      const MCInstrDesc &MCID = MI.getDesc();
+      if (MCID.TSFlags & ARMII::ThumbArithFlagSetting && MO.isDead() &&
+          SkipDead)
+        continue;
+
       Pred.push_back(MO);
       Found = true;
     }
   }
 
   return Found;
 }
 

llvm/test/CodeGen/Thumb2/constant-hoisting.ll

 ; CHECK-V6M-NEXT:    .long 537923600
 ;
 ; CHECK-V7M-LABEL: test_values:
 ; CHECK-V7M:         mov r2, r0
 ; CHECK-V7M-NEXT:    ldr r0, .LCPI0_0
 ; CHECK-V7M-NEXT:    cmp r2, #50
 ; CHECK-V7M-NEXT:    beq .LBB0_5
 ; CHECK-V7M-NEXT:    cmp r2, #1
-; CHECK-V7M-NEXT:    beq .LBB0_7
+; CHECK-V7M-NEXT:    ittt eq
+; CHECK-V7M-NEXT:    addeq r0, r1
+; CHECK-V7M-NEXT:    addeq r0, #1
+; CHECK-V7M-NEXT:    bxeq lr
+; CHECK-V7M-NEXT:  .LBB0_2:
 ; CHECK-V7M-NEXT:    cmp r2, #30
-; CHECK-V7M-NEXT:    beq .LBB0_8
+; CHECK-V7M-NEXT:    ittt eq
+; CHECK-V7M-NEXT:    addeq r0, r1
+; CHECK-V7M-NEXT:    addeq r0, #2
+; CHECK-V7M-NEXT:    bxeq lr
+; CHECK-V7M-NEXT:  .LBB0_3:
 ; CHECK-V7M-NEXT:    cbnz r2, .LBB0_6
 ; CHECK-V7M-NEXT:    add r0, r1
 ; CHECK-V7M-NEXT:    bx lr
 ; CHECK-V7M-NEXT:  .LBB0_5:
 ; CHECK-V7M-NEXT:    add r0, r1
 ; CHECK-V7M-NEXT:    adds r0, #4
 ; CHECK-V7M-NEXT:  .LBB0_6:
 ; CHECK-V7M-NEXT:    bx lr
-; CHECK-V7M-NEXT:  .LBB0_7:
-; CHECK-V7M-NEXT:    add r0, r1
-; CHECK-V7M-NEXT:    adds r0, #1
-; CHECK-V7M-NEXT:    bx lr
-; CHECK-V7M-NEXT:  .LBB0_8:
-; CHECK-V7M-NEXT:    add r0, r1
-; CHECK-V7M-NEXT:    adds r0, #2
-; CHECK-V7M-NEXT:    bx lr
 ; CHECK-V7M-NEXT:    .p2align 2
 ; CHECK-V7M-NEXT:  .LCPI0_0:
 ; CHECK-V7M-NEXT:    .long 537923600
 entry:
   switch i32 %a, label %return [
     i32 0, label %sw.bb
     i32 1, label %sw.bb1
     i32 30, label %sw.bb3

llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir

liveins:
   - { reg: '$r2' }
 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: branch_entry
   ; CHECK: bb.0.entry:
-  ; CHECK:   successors: %bb.1, %bb.2
+  ; CHECK:   successors: %bb.1
   ; CHECK:   liveins: $r0, $r1, $r2
   ; CHECK:   renamable $r0 = tLDRBi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.command_set, align 4)
   ; CHECK:   dead renamable $r0, $cpsr = tLSLri killed renamable $r0, 24, 14 /* CC::al */, $noreg
-  ; CHECK:   t2Bcc %bb.2, 4 /* CC::mi */, killed $cpsr
-  ; CHECK: bb.1.land.end:
-  ; CHECK:   $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
-  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
-  ; CHECK: bb.2.land.rhs:
+  ; CHECK:   $r0, dead $noreg = tMOVi8 0, 5 /* CC::pl */, $cpsr
+  ; CHECK:   tBX_RET 5 /* CC::pl */, killed $cpsr, implicit killed $r0
+  ; CHECK: bb.1.land.rhs:
   ; CHECK:   liveins: $r1, $r2
   ; CHECK:   $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg
   ; CHECK:   $r1 = tMOVr killed $r2, 14 /* CC::al */, $noreg
   ; CHECK:   tTAILJMPdND @branch_target, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit $r0, implicit $r1
   bb.0.entry:
     successors: %bb.1, %bb.2
     liveins: $r0, $r1, $r2