[PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

[Conanap]

Summary

This patch implements 128-bit Binary Vector Mod and Sign Extend builtins for PowerPC10.

[amyk]

A question I have is, is it possible for the 128-bit vector modulo instructions be open coded?

clang/lib/Headers/altivec.h

17455

nit: Move these under the existing vec_mod builtins.
Also, is it possible for these to be open coded instead? We have vec_mod for other types that are open coded.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

1343

nit: Indent v1i128 underneath the top v1i128.

[Conanap]

clang/lib/Headers/altivec.h

17455

Probably? Although the downsteram impementation is actually not open coded. We can still change it though.

[Conanap]

Open coded VMODS/UQ instead.

[Conanap]

Open Coded instead

clang/lib/Headers/altivec.h

17455

Probably? Although the downsteram impementation is actually not open coded. We can still change it though.

[nemanjai]

The nits can be addressed when committing the code. LGTM otherwise.

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1452

The indentation is off on all of these. Should probably be something like:

def VEXTSB2W :
  VX_VT5_EO5_VB5<1538, 16, "vextsb2w",
                 [(set v4i32:$vD, (int_ppc_altivec_vextsb2w v16i8:$vB))]>;

llvm/test/CodeGen/PowerPC/p10-vector-sign-extend.ll

1

Nit: only one of these requires P10. The others are P9 instructions. You have split the tests for the front end changes, please split the back end test as well.

[amyk]

Thanks for open coding. Aside from Nemanja's nits, I believe all my concerns have been addressed. LGTM.

[Conanap]

Committed with Nemanja's comments addressed in the commit. Hash d7eb917a7cb793f49e16841fc24826b988dd5c8f

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_altivec_vsrv, "V16UcV16UcV16Uc", "")
 
 // P9 Vector rotate built-ins
 BUILTIN(__builtin_altivec_vrlwmi, "V4UiV4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vrldmi, "V2ULLiV2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "")
 
+// P9 Vector extend sign builtins.
+BUILTIN(__builtin_altivec_vextsb2w, "V4SiV16Sc", "")
+BUILTIN(__builtin_altivec_vextsb2d, "V2SLLiV16Sc", "")
+BUILTIN(__builtin_altivec_vextsh2w, "V4SiV8Ss", "")
+BUILTIN(__builtin_altivec_vextsh2d, "V2SLLiV8Ss", "")
+BUILTIN(__builtin_altivec_vextsw2d, "V2SLLiV4Si", "")
+
+// P10 Vector extend sign builtins.
+BUILTIN(__builtin_altivec_vextsd2q, "V1SLLLiV2SLLi", "")
+
 // P10 Vector Extract with Mask built-ins.
 BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "")
 BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "")
 BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui", "")
 BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "")
 BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "")
 
 // P10 Vector Divide Extended built-ins.

clang/lib/Headers/altivec.h

 #else
 #define vec_ctu __builtin_altivec_vctuxs
 #endif
 
 /* vec_vctuxs */
 
 #define vec_vctuxs __builtin_altivec_vctuxs
 
+/* vec_signext */
+
+#ifdef __POWER9_VECTOR__
+static __inline__ vector signed int __ATTRS_o_ai
+vec_signexti(vector signed char __a) {
+  return __builtin_altivec_vextsb2w(__a);
+}
+
+static __inline__ vector signed int __ATTRS_o_ai
+vec_signexti(vector signed short __a) {
+  return __builtin_altivec_vextsh2w(__a);
+}
+
+static __inline__ vector signed long long __ATTRS_o_ai
+vec_signextll(vector signed char __a) {
+  return __builtin_altivec_vextsb2d(__a);
+}
+
+static __inline__ vector signed long long __ATTRS_o_ai
+vec_signextll(vector signed short __a) {
+  return __builtin_altivec_vextsh2d(__a);
+}
+
+static __inline__ vector signed long long __ATTRS_o_ai
+vec_signextll(vector signed int __a) {
+  return __builtin_altivec_vextsw2d(__a);
+}
+#endif
+
+#ifdef __POWER10_VECTOR__
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_signextq(vector signed long long __a) {
+  return __builtin_altivec_vextsd2q(__a);
+}
+#endif
+
 /* vec_signed */
 
 static __inline__ vector signed int __ATTRS_o_ai
 vec_sld(vector signed int, vector signed int, unsigned const int __c);
 
 static __inline__ vector signed int __ATTRS_o_ai
 vec_signed(vector float __a) {
   return __builtin_convertvector(__a, vector signed int);
vec_mod(vector signed long long __a, vector signed long long __b) {
   return __a % __b;
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_mod(vector unsigned long long __a, vector unsigned long long __b) {
   return __a % __b;
 }
 
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_mod(vector signed __int128 __a, vector signed __int128 __b) {
+  return __a % __b;
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_mod(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+  return  __a % __b;
+}
+
 /* vec_sldbi */
 
 #define vec_sldb(__a, __b, __c) __builtin_altivec_vsldbi(__a, __b, (__c & 0x7))
 
 /* vec_srdbi */
 
 #define vec_srdb(__a, __b, __c) __builtin_altivec_vsrdbi(__a, __b, (__c & 0x7))
 

 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vinswvlx(__b, __c, __a);
 #else
   return __builtin_altivec_vinswvrx(__b, __c, __a);
 #endif
 }
 
 /* vec_extractl */
 
 static __inline__ vector unsigned long long __ATTRS_o_ai vec_extractl(
     vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vextdubvrx(__a, __b, __c);
 #else
   vector unsigned long long __ret = __builtin_altivec_vextdubvlx(__a, __b, __c);
   return vec_sld(__ret, __ret, 8);
 #endif

clang/test/CodeGen/builtins-ppc-p10vector.c

 }
 
 vector unsigned __int128 test_vec_xl_zext_i64(void) {
   // CHECK: load i64
   // CHECK: zext i64
   // CHECK: ret <1 x i128>
   return vec_xl_zext(llb, ullap);
 }
+
+vector signed __int128 test_vec_signextq_s128(void) {
+    // CHECK: @llvm.ppc.altivec.vextsd2q(<2 x i64>
+    // CHECK-NEXT: ret <1 x i128>
+    return vec_signextq(vslla);
+}
+
+vector unsigned __int128 test_vec_mod_u128(void) {
+    // CHECK: urem <1 x i128>
+    // CHECK-NEXT: ret <1 x i128>
+    return vec_mod(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_mod_s128(void) {
+    // CHECK: srem <1 x i128>
+    // CHECK-NEXT: ret <1 x i128>
+    return vec_mod(vsi128a, vsi128b);
+}

clang/test/CodeGen/builtins-ppc-p9vector.c

 // CHECK-BE: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 0)
 // CHECK-BE-NEXT: ret <2 x i64>
 // CHECK: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 12)
 // CHECK-NEXT: shufflevector <2 x i64> [[T1]], <2 x i64> [[T1]], <2 x i32> <i32 1, i32 0>
 // CHECK-NEXT: ret <2 x i64>
   return vec_extract4b(vuca, -5);
 }
 
+vector signed int test_vec_signexti_si_sc(void) {
+    // CHECK: @llvm.ppc.altivec.vextsb2w(<16 x i8>
+    // CHECK-NEXT: ret <4 x i32>
+    return vec_signexti(vsca);
+}
+
+vector signed int test_vec_signexti_si_ss(void) {
+    // CHECK: @llvm.ppc.altivec.vextsh2w(<8 x i16>
+    // CHECK-NEXT: ret <4 x i32>
+    return vec_signexti(vssa);
+}
+
+vector signed long long test_vec_signextll_sll_sc(void) {
+    // CHECK: @llvm.ppc.altivec.vextsb2d(<16 x i8>
+    // CHECK-NEXT: ret <2 x i64>
+    return vec_signextll(vsca);
+}
+
+vector signed long long test_vec_signextll_sll_ss(void) {
+    // CHECK: @llvm.ppc.altivec.vextsh2d(<8 x i16>
+    // CHECK-NEXT: ret <2 x i64>
+    return vec_signextll(vssa);
+}
+
+vector signed long long test_vec_signextll_sll_si(void) {
+    // CHECK: @llvm.ppc.altivec.vextsw2d(<4 x i32>
+    // CHECK-NEXT: ret <2 x i64>
+    return vec_signextll(vsia);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_vsum4sbs : GCCBuiltin<"__builtin_altivec_vsum4sbs">,
                       [IntrNoMem]>;
   def int_ppc_altivec_vsum4shs : GCCBuiltin<"__builtin_altivec_vsum4shs">,
             Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v4i32_ty],
                       [IntrNoMem]>;
   def int_ppc_altivec_vsum4ubs : GCCBuiltin<"__builtin_altivec_vsum4ubs">,
             Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v4i32_ty],
                       [IntrNoMem]>;
 
+  // Vector Sign Extension Instructions
+  def int_ppc_altivec_vextsb2w : GCCBuiltin<"__builtin_altivec_vextsb2w">,
+            Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vextsb2d : GCCBuiltin<"__builtin_altivec_vextsb2d">,
+            Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vextsh2w : GCCBuiltin<"__builtin_altivec_vextsh2w">,
+            Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vextsh2d : GCCBuiltin<"__builtin_altivec_vextsh2d">,
+            Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vextsw2d : GCCBuiltin<"__builtin_altivec_vextsw2d">,
+            Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vextsd2q : GCCBuiltin<"__builtin_altivec_vextsd2q">,
+            Intrinsic<[llvm_v1i128_ty], [llvm_v2i64_ty], [IntrNoMem]>;
+
   // Other multiplies.
   def int_ppc_altivec_vmladduhm : GCCBuiltin<"__builtin_altivec_vmladduhm">,
             Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
                        llvm_v8i16_ty], [IntrNoMem]>;
 
   // Packs.
   def int_ppc_altivec_vpkpx : GCCBuiltin<"__builtin_altivec_vpkpx">,
             Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty],

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.isISA3_1()) {
       setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
       setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
       setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
       setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
       setOperationAction(ISD::UREM, MVT::v2i64, Legal);
       setOperationAction(ISD::SREM, MVT::v2i64, Legal);
       setOperationAction(ISD::UREM, MVT::v4i32, Legal);
       setOperationAction(ISD::SREM, MVT::v4i32, Legal);
+      setOperationAction(ISD::UREM, MVT::v1i128, Legal);
+      setOperationAction(ISD::SREM, MVT::v1i128, Legal);
       setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
       setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
     }
 
     setOperationAction(ISD::MUL, MVT::v8i16, Legal);
     setOperationAction(ISD::MUL, MVT::v16i8, Custom);
 
     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh",
                            [(set v8i16:$vD, (cttz v8i16:$vB))]>;
 def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw",
                            [(set v4i32:$vD, (cttz v4i32:$vB))]>;
 def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd",
                            [(set v2i64:$vD, (cttz v2i64:$vB))]>;
 
 // Vector Extend Sign
-def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>;
-def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>;
-def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>;
-def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>;
-def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>;
+def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", [(set v4i32:$vD,
+                              (int_ppc_altivec_vextsb2w v16i8:$vB))]>;
+def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", [(set v4i32:$vD,
+                              (int_ppc_altivec_vextsh2w v8i16:$vB))]>;
+def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", [(set v2i64:$vD,
+                              (int_ppc_altivec_vextsb2d v16i8:$vB))]>;
+def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", [(set v2i64:$vD,
+                              (int_ppc_altivec_vextsh2d v8i16:$vB))]>;
+def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", [(set v2i64:$vD,
+                              (int_ppc_altivec_vextsw2d v4i32:$vB))]>;
 let isCodeGenOnly = 1 in {
   def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>;
   def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>;
   def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>;
   def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>;
   def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>;
 }
 

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vdiveuq $vD, $vA, $vB", IIC_VecGeneral, []>;
   def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>;
   def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>;
   def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>;
   def VCMPEQUQ_rec : VCMPo <455, "vcmpequq. $vD, $vA, $vB" , v1i128>;
   def VCMPGTSQ_rec : VCMPo <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>;
   def VCMPGTUQ_rec : VCMPo <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>;
   def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                        "vmodsq $vD, $vA, $vB", IIC_VecGeneral, []>;
+                        "vmodsq $vD, $vA, $vB", IIC_VecGeneral,
+                        [(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>;
   def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                        "vmoduq $vD, $vA, $vB", IIC_VecGeneral, []>;
+                        "vmoduq $vD, $vA, $vB", IIC_VecGeneral,
+                        [(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>;
   def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB),
-                                    "vextsd2q $vD, $vB", IIC_VecGeneral, []>;
+                               "vextsd2q $vD, $vB", IIC_VecGeneral,
+                               [(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>;
   def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
                                "vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>;
   def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
                                "vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>;
   def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", []>;
   def VRLQMI : VXForm_1<69, (outs vrrc:$vD),
                         (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
                         "vrlqmi $vD, $vA, $vB", IIC_VecFP, []>,

llvm/test/CodeGen/PowerPC/p10-vector-modulo.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
 
 ; This test case aims to test the vector modulo instructions on Power10.
 ; The vector modulo instructions operate on signed and unsigned words
 ; and doublewords.
 
+; The vector modulo instructions operate on signed and unsigned words,
+; doublewords and 128-bit values.
+
+
+define <1 x i128> @test_vmodsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
+; CHECK-LABEL: test_vmodsq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmodsq v2, v2, v3
+; CHECK-NEXT:    blr
+  %tmp = srem <1 x i128> %x, %y
+  ret <1 x i128> %tmp
+}
+
+define <1 x i128> @test_vmoduq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
+; CHECK-LABEL: test_vmoduq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmoduq v2, v2, v3
+; CHECK-NEXT:    blr
+  %tmp = urem <1 x i128> %x, %y
+  ret <1 x i128> %tmp
+}
+
 define <2 x i64> @test_vmodud(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vmodud:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmodud v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %rem = urem <2 x i64> %a, %b
   ret <2 x i64> %rem

llvm/test/CodeGen/PowerPC/p10-vector-sign-extend.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; This test case aims to test vector sign extend builtins.
+
+declare <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vextsw2d(<4 x i32>) nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64>) nounwind readnone
+
+define <4 x i32> @test_vextsb2w(<16 x i8> %x) nounwind readnone {
+; CHECK-LABEL: test_vextsb2w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vextsb2w v2, v2
+; CHECK-NEXT:    blr
+  %tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8> %x)
+  ret <4 x i32> %tmp
+}
+
+define <2 x i64> @test_vextsb2d(<16 x i8> %x) nounwind readnone {
+; CHECK-LABEL: test_vextsb2d:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vextsb2d v2, v2
+; CHECK-NEXT:    blr
+  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8> %x)
+  ret <2 x i64> %tmp
+}
+
+define <4 x i32> @test_vextsh2w(<8 x i16> %x) nounwind readnone {
+; CHECK-LABEL: test_vextsh2w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vextsh2w v2, v2
+; CHECK-NEXT:    blr
+  %tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16> %x)
+  ret <4 x i32> %tmp
+}
+
+define <2 x i64> @test_vextsh2d(<8 x i16> %x) nounwind readnone {
+; CHECK-LABEL: test_vextsh2d:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vextsh2d v2, v2
+; CHECK-NEXT:    blr
+  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16> %x)
+  ret <2 x i64> %tmp
+}
+
+define <2 x i64> @test_vextsw2d(<4 x i32> %x) nounwind readnone {
+; CHECK-LABEL: test_vextsw2d:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vextsw2d v2, v2
+; CHECK-NEXT:    blr
+  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsw2d(<4 x i32> %x)
+  ret <2 x i64> %tmp
+}
+
+define <1 x i128> @test_vextsd2q(<2 x i64> %x) nounwind readnone {
+; CHECK-LABEL: test_vextsd2q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vextsd2q v2, v2
+; CHECK-NEXT:    blr
+  %tmp = tail call <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64> %x)
+  ret <1 x i128> %tmp
+}