[GlobalISel] Avoid making G_PTR_ADD with nullptr

[mbrkusanin]

Summary

When the first operand is a null pointer we can avoid making a G_PTR_ADD and
make a G_INTTOPTR with the offset operand.
This helps us avoid making add with 0 later on for targets such as AMDGPU.

[arsenm]

This is probably wrong for non integral pointers. Why not do this as a combine later? We need to start recognizing G_PTRADD (constant) + constant anyway to handle lowered LDS addresses

[foad]

llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll

11

Can you avoid generating this unused constant in the first place?

[mbrkusanin]

• Reimplemented as a AMDGPU GICombineRule.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

40 ↗

(On Diff #292192)

ptr_add

40–45 ↗

(On Diff #292192)

This should go in the generic combiner

llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp

45 ↗

(On Diff #292192)

Should not construct a local MachineIRBuilder

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir

52–53 ↗

(On Diff #292192)

Can simplify these out of the test

56 ↗

(On Diff #292192)

Should add vector test

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

2737–2740 ↗

(On Diff #294334)

Combine the scalar and vector check above?

2743 ↗

(On Diff #294334)

I have a patch to generalize these checks I haven't posted yet, but I guess having the two paths is fine for now

[mbrkusanin]

• Refactored matchPtrAddZero().

[mbrkusanin]

• Rebase
• Ping

[foad]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

2774 ↗

(On Diff #297787)

This is just Ty.getScalarType().

2783 ↗

(On Diff #297787)

You should be able to assert that it is a vector here.

[mbrkusanin]

• Addressed comments.

[foad]

LGTM.

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

if (StructType *StTy = GTI.getStructTypeOrNull()) {
       if (ElementSize != 1) {
         auto ElementSizeMIB = MIRBuilder.buildConstant(
             getLLTForType(*OffsetIRTy, *DL), ElementSize);
         GepOffsetReg =
             MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0);
       } else
         GepOffsetReg = IdxReg;
 
-      BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
+      if (isa<ConstantPointerNull>(Op0))
+        BaseReg = MIRBuilder.buildIntToPtr(PtrTy, GepOffsetReg).getReg(0);
+      else
+        BaseReg =
+            MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
     }
   }
 
   if (Offset != 0) {
     auto OffsetMIB =
         MIRBuilder.buildConstant(OffsetTy, Offset);
     MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0));
     return true;

llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll

 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
 
 %type = type [4 x {i8, i32}]
 
 define i8*  @translate_element_size1(i64 %arg) {
   ; CHECK-LABEL: name: translate_element_size1
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK:   liveins: $x0
   ; CHECK:   [[COPY:%[0-9]+]]:_(s64) = COPY $x0
   ; CHECK:   [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
-  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[C]], [[COPY]](s64)
-  ; CHECK:   [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
+  ; CHECK:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
   ; CHECK:   $x0 = COPY [[COPY1]](p0)
   ; CHECK:   RET_ReallyLR implicit $x0
   %tmp = getelementptr i8, i8* null, i64 %arg
   ret i8* %tmp
 }
 
 define %type* @first_offset_const(%type* %addr) {
 

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-add-nullptr.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -march=amdgcn -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+
+define amdgpu_cs i32 @_amdgpu_cs_main(i32 inreg %arg) {
+  ; CHECK-LABEL: name: _amdgpu_cs_main
+  ; CHECK: bb.1..entry:
+  ; CHECK:   liveins: $sgpr0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+  ; CHECK:   [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[C]]
+  ; CHECK:   [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[MUL]](s32)
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(p6) = COPY [[INTTOPTR]](p6)
+  ; CHECK:   [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p6)
+  ; CHECK:   [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[PTRTOINT]](s32)
+  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
+  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0
+.entry:
+  %ptr = getelementptr {i32, i32}, {i32, i32} addrspace(6)* null, i32 %arg, i32 0
+  %iptr = ptrtoint i32 addrspace(6)* %ptr to i32
+  ret i32 %iptr
+}