[CodeGen] Properly propagating Calling Convention information when lowering vector arguments

[pratlucas]

Summary

When joining the legal parts of vector arguments into its original value
during the lower of Formal Arguments in SelectionDAGBuilder, the Calling
Convention information was not being propagated for the handling of each
individual parts. The same did not happen when lowering calls, causing a
mismatch.

This patch fixes the issue by properly propagating the Calling
Convention details.

This fixes Bugzilla #47001.

[pratlucas]

Removing unrelated whitespace change.

[arsenm]

llvm/test/CodeGen/ARM/fp16-v3.ll

31

Why were these deleted?

[pratlucas]

llvm/test/CodeGen/ARM/fp16-v3.ll

31

The issue fixed by this patch was preventing the changes from D75169 to be applied for vector arguments such as this one.
With those changes applied, the vector elements are properly passed without the floating point conversion to f32.

[hans]

Pushed to 11.x as ba3413982cbd7a5b5aeaf2ea34e0a91d5561202d. Please let me know if there are any follow-ups.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (NumParts > 1) {
 
     // Assemble the parts into intermediate operands.
     SmallVector<SDValue, 8> Ops(NumIntermediates);
     if (NumIntermediates == NumParts) {
       // If the register was not expanded, truncate or copy the value,
       // as appropriate.
       for (unsigned i = 0; i != NumParts; ++i)
         Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
-                                  PartVT, IntermediateVT, V);
+                                  PartVT, IntermediateVT, V, CallConv);
     } else if (NumParts > 0) {
       // If the intermediate type was expanded, build the intermediate
       // operands from the parts.
       assert(NumParts % NumIntermediates == 0 &&
              "Must expand into a divisible number of parts!");
       unsigned Factor = NumParts / NumIntermediates;
       for (unsigned i = 0; i != NumIntermediates; ++i)
         Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
-                                  PartVT, IntermediateVT, V);
+                                  PartVT, IntermediateVT, V, CallConv);
     }
 
     // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
     // intermediate operands.
     EVT BuiltVectorTy =
         IntermediateVT.isVector()
             ? EVT::getVectorVT(
                   *DAG.getContext(), IntermediateVT.getScalarType(),

llvm/test/CodeGen/ARM/fp16-args.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
-; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
-; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-SOFT
-; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-HARD
-; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
-; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
-; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-SOFT
-; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-HARD
+; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=SOFT
+; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=HARD
+; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-SOFT --check-prefix=FULL-SOFT-LE
+; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-HARD --check-prefix=FULL-HARD-LE
+; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=SOFT
+; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=HARD
+; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-SOFT --check-prefix=FULL-SOFT-BE
+; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-HARD --check-prefix=FULL-HARD-BE
 
 define half @foo(half %a, half %b) {
 ; SOFT-LABEL: foo:
 ; SOFT:       @ %bb.0: @ %entry
 ; SOFT-NEXT:    vmov s0, r0
 ; SOFT-NEXT:    vmov s2, r1
 ; SOFT-NEXT:    vcvtb.f32.f16 s0, s0
 ; SOFT-NEXT:    vcvtb.f32.f16 s2, s2

 ; FULL-HARD-LABEL: foo:
 ; FULL-HARD:       @ %bb.0: @ %entry
 ; FULL-HARD-NEXT:    vadd.f16 s0, s0, s1
 ; FULL-HARD-NEXT:    bx lr
 entry:
   %0 = fadd half %a, %b
   ret half %0
 }
+
+define <4 x half> @foo_vec(<4 x half> %a) {
+; SOFT-LABEL: foo_vec:
+; SOFT:       @ %bb.0: @ %entry
+; SOFT-NEXT:    vmov s0, r3
+; SOFT-NEXT:    vmov s2, r1
+; SOFT-NEXT:    vcvtb.f32.f16 s0, s0
+; SOFT-NEXT:    vmov s4, r0
+; SOFT-NEXT:    vcvtb.f32.f16 s2, s2
+; SOFT-NEXT:    vmov s6, r2
+; SOFT-NEXT:    vcvtb.f32.f16 s4, s4
+; SOFT-NEXT:    vcvtb.f32.f16 s6, s6
+; SOFT-NEXT:    vadd.f32 s0, s0, s0
+; SOFT-NEXT:    vadd.f32 s2, s2, s2
+; SOFT-NEXT:    vcvtb.f16.f32 s0, s0
+; SOFT-NEXT:    vadd.f32 s4, s4, s4
+; SOFT-NEXT:    vcvtb.f16.f32 s2, s2
+; SOFT-NEXT:    vadd.f32 s6, s6, s6
+; SOFT-NEXT:    vcvtb.f16.f32 s4, s4
+; SOFT-NEXT:    vcvtb.f16.f32 s6, s6
+; SOFT-NEXT:    vmov r0, s4
+; SOFT-NEXT:    vmov r1, s2
+; SOFT-NEXT:    vmov r2, s6
+; SOFT-NEXT:    vmov r3, s0
+; SOFT-NEXT:    bx lr
+;
+; HARD-LABEL: foo_vec:
+; HARD:       @ %bb.0: @ %entry
+; HARD-NEXT:    vcvtb.f32.f16 s4, s3
+; HARD-NEXT:    vcvtb.f32.f16 s2, s2
+; HARD-NEXT:    vcvtb.f32.f16 s6, s1
+; HARD-NEXT:    vcvtb.f32.f16 s0, s0
+; HARD-NEXT:    vadd.f32 s2, s2, s2
+; HARD-NEXT:    vadd.f32 s0, s0, s0
+; HARD-NEXT:    vcvtb.f16.f32 s2, s2
+; HARD-NEXT:    vadd.f32 s4, s4, s4
+; HARD-NEXT:    vcvtb.f16.f32 s0, s0
+; HARD-NEXT:    vadd.f32 s6, s6, s6
+; HARD-NEXT:    vcvtb.f16.f32 s3, s4
+; HARD-NEXT:    vcvtb.f16.f32 s1, s6
+; HARD-NEXT:    bx lr
+;
+; FULL-SOFT-LE-LABEL: foo_vec:
+; FULL-SOFT-LE:       @ %bb.0: @ %entry
+; FULL-SOFT-LE-NEXT:    vmov d16, r0, r1
+; FULL-SOFT-LE-NEXT:    vadd.f16 d16, d16, d16
+; FULL-SOFT-LE-NEXT:    vmov r0, r1, d16
+; FULL-SOFT-LE-NEXT:    bx lr
+;
+; FULL-HARD-LE-LABEL: foo_vec:
+; FULL-HARD-LE:       @ %bb.0: @ %entry
+; FULL-HARD-LE-NEXT:    vadd.f16 d0, d0, d0
+; FULL-HARD-LE-NEXT:    bx lr
+;
+; FULL-SOFT-BE-LABEL: foo_vec:
+; FULL-SOFT-BE:       @ %bb.0: @ %entry
+; FULL-SOFT-BE-NEXT:    vmov d16, r1, r0
+; FULL-SOFT-BE-NEXT:    vrev64.16 d16, d16
+; FULL-SOFT-BE-NEXT:    vadd.f16 d16, d16, d16
+; FULL-SOFT-BE-NEXT:    vrev64.16 d16, d16
+; FULL-SOFT-BE-NEXT:    vmov r1, r0, d16
+; FULL-SOFT-BE-NEXT:    bx lr
+;
+; FULL-HARD-BE-LABEL: foo_vec:
+; FULL-HARD-BE:       @ %bb.0: @ %entry
+; FULL-HARD-BE-NEXT:    vrev64.16 d16, d0
+; FULL-HARD-BE-NEXT:    vadd.f16 d16, d16, d16
+; FULL-HARD-BE-NEXT:    vrev64.16 d0, d16
+; FULL-HARD-BE-NEXT:    bx lr
+entry:
+  %0 = fadd <4 x half> %a, %a
+  ret <4 x half> %0
+}

llvm/test/CodeGen/ARM/fp16-v3.ll

define void @test_vec3(<3 x half>* %arr, i32 %i) #0 {
   %1 = insertelement <3 x half> undef, half %S, i32 0
   %2 = insertelement <3 x half> %1, half %S, i32 1
   %3 = insertelement <3 x half> %2, half %S, i32 2
   store <3 x half> %3, <3 x half>* %arr, align 8
   ret void
 }
 
 ; CHECK-LABEL: test_bitcast:
-; CHECK: vcvtb.f16.f32
-; CHECK: vcvtb.f16.f32
-; CHECK: vcvtb.f16.f32
 ; CHECK: pkhbt
 ; CHECK: uxth
 define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 {
   %bc = bitcast <3 x half> %inp to <3 x i16>
   store <3 x i16> %bc, <3 x i16>* %arr, align 8
   ret void
 }
 
 attributes #0 = { nounwind }