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Differential D86656

[IR] Remove noundef from masked store/load/gather/scatter's pointer operands
ClosedPublic

Authored by aqjune on Aug 26 2020, 1:16 PM.

Details

Reviewers
efriedma
jdoerfert
Commits
rG0c55889d8090: [IR] Remove noundef from masked store/load/gather/scatter's pointer operands
Summary

As discussed in D86576, noundef attribute is removed from masked store/load/gather/scatter's
pointer operands.

Diff Detail

Event Timeline

aqjune created this revision.Aug 26 2020, 1:16 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptAug 26 2020, 1:16 PM
Herald added subscribers: llvm-commits, msifontes, jurahul and 13 others. · View Herald Transcript
aqjune requested review of this revision.Aug 26 2020, 1:16 PM
Herald added subscribers: stephenneuendorffer, nicolasvasilache. · View Herald TranscriptAug 26 2020, 1:16 PM
efriedma accepted this revision.Aug 26 2020, 1:48 PM

LGTM

This revision is now accepted and ready to land.Aug 26 2020, 1:48 PM
This revision was landed with ongoing or failed builds.Aug 26 2020, 2:42 PM
Closed by commit rG0c55889d8090: [IR] Remove noundef from masked store/load/gather/scatter's pointer operands (authored by aqjune). · Explain Why
This revision was automatically updated to reflect the committed changes.
aqjune added a commit: rG0c55889d8090: [IR] Remove noundef from masked store/load/gather/scatter's pointer operands.
Harbormaster completed remote builds in B69668: Diff 288094.Aug 26 2020, 2:54 PM

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
10 lines
mlir/
test/
Target/
8 lines

Diff 288094

llvm/include/llvm/IR/Intrinsics.td

Show First 20 Lines • Show All 1,347 Lines • ▼ Show 20 Lines Intrinsic<[llvm_anyvector_ty],
[IntrNoMem, IntrNoSync, IntrWillReturn]>; [IntrNoMem, IntrNoSync, IntrWillReturn]>;
//===-------------------------- Masked Intrinsics -------------------------===// //===-------------------------- Masked Intrinsics -------------------------===//
// //
def int_masked_store : Intrinsic<[], [llvm_anyvector_ty, def int_masked_store : Intrinsic<[], [llvm_anyvector_ty,
LLVMAnyPointerType<LLVMMatchType<0>>, LLVMAnyPointerType<LLVMMatchType<0>>,
llvm_i32_ty, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrArgMemOnly, IntrWillReturn, [IntrArgMemOnly, IntrWillReturn, ImmArg<ArgIndex<2>>]>;
NoUndef<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
def int_masked_load : Intrinsic<[llvm_anyvector_ty], def int_masked_load : Intrinsic<[llvm_anyvector_ty],
[LLVMAnyPointerType<LLVMMatchType<0>>, llvm_i32_ty, [LLVMAnyPointerType<LLVMMatchType<0>>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>],
[IntrReadMem, IntrArgMemOnly, IntrWillReturn, [IntrReadMem, IntrArgMemOnly, IntrWillReturn,
NoUndef<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; ImmArg<ArgIndex<1>>]>;
def int_masked_gather: Intrinsic<[llvm_anyvector_ty], def int_masked_gather: Intrinsic<[llvm_anyvector_ty],
[LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty, [LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<0>], LLVMMatchType<0>],
[IntrReadMem, IntrWillReturn, [IntrReadMem, IntrWillReturn,
NoUndef<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; ImmArg<ArgIndex<1>>]>;
def int_masked_scatter: Intrinsic<[], def int_masked_scatter: Intrinsic<[],
[llvm_anyvector_ty, [llvm_anyvector_ty,
LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty, LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrWillReturn, NoUndef<ArgIndex<1>>, [IntrWillReturn, ImmArg<ArgIndex<2>>]>;
ImmArg<ArgIndex<2>>]>;
def int_masked_expandload: Intrinsic<[llvm_anyvector_ty], def int_masked_expandload: Intrinsic<[llvm_anyvector_ty],
[LLVMPointerToElt<0>, [LLVMPointerToElt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<0>], LLVMMatchType<0>],
[IntrReadMem, IntrWillReturn]>; [IntrReadMem, IntrWillReturn]>;
def int_masked_compressstore: Intrinsic<[], def int_masked_compressstore: Intrinsic<[],
▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines

mlir/test/Target/llvmir-intrinsics.mlir

Show First 20 Lines • Show All 316 Lines • ▼ Show 20 Lines
// CHECK-DAG: declare float @llvm.cos.f32(float) // CHECK-DAG: declare float @llvm.cos.f32(float)
// CHECK-DAG: declare <8 x float> @llvm.cos.v8f32(<8 x float>) #0 // CHECK-DAG: declare <8 x float> @llvm.cos.v8f32(<8 x float>) #0
// CHECK-DAG: declare float @llvm.copysign.f32(float, float) // CHECK-DAG: declare float @llvm.copysign.f32(float, float)
// CHECK-DAG: declare <12 x float> @llvm.matrix.multiply.v12f32.v64f32.v48f32(<64 x float>, <48 x float>, i32 immarg, i32 immarg, i32 immarg) // CHECK-DAG: declare <12 x float> @llvm.matrix.multiply.v12f32.v64f32.v48f32(<64 x float>, <48 x float>, i32 immarg, i32 immarg, i32 immarg)
// CHECK-DAG: declare <48 x float> @llvm.matrix.transpose.v48f32(<48 x float>, i32 immarg, i32 immarg) // CHECK-DAG: declare <48 x float> @llvm.matrix.transpose.v48f32(<48 x float>, i32 immarg, i32 immarg)
// CHECK-DAG: declare <48 x float> @llvm.matrix.column.major.load.v48f32(float* nocapture, i64, i1 immarg, i32 immarg, i32 immarg) // CHECK-DAG: declare <48 x float> @llvm.matrix.column.major.load.v48f32(float* nocapture, i64, i1 immarg, i32 immarg, i32 immarg)
// CHECK-DAG: declare void @llvm.matrix.column.major.store.v48f32(<48 x float>, float* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) // CHECK-DAG: declare void @llvm.matrix.column.major.store.v48f32(<48 x float>, float* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg)
// CHECK-DAG: declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64) // CHECK-DAG: declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64)
// CHECK-DAG: declare <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>* noundef, i32 immarg, <7 x i1>, <7 x float>) // CHECK-DAG: declare <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>*, i32 immarg, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.store.v7f32.p0v7f32(<7 x float>, <7 x float>* noundef, i32 immarg, <7 x i1>) // CHECK-DAG: declare void @llvm.masked.store.v7f32.p0v7f32(<7 x float>, <7 x float>*, i32 immarg, <7 x i1>)
// CHECK-DAG: declare <7 x float> @llvm.masked.gather.v7f32.v7p0f32(<7 x float*> noundef, i32 immarg, <7 x i1>, <7 x float>) // CHECK-DAG: declare <7 x float> @llvm.masked.gather.v7f32.v7p0f32(<7 x float*>, i32 immarg, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.scatter.v7f32.v7p0f32(<7 x float>, <7 x float*> noundef, i32 immarg, <7 x i1>) // CHECK-DAG: declare void @llvm.masked.scatter.v7f32.v7p0f32(<7 x float>, <7 x float*>, i32 immarg, <7 x i1>)
// CHECK-DAG: declare <7 x float> @llvm.masked.expandload.v7f32(float*, <7 x i1>, <7 x float>) // CHECK-DAG: declare <7 x float> @llvm.masked.expandload.v7f32(float*, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.compressstore.v7f32(<7 x float>, float*, <7 x i1>) // CHECK-DAG: declare void @llvm.masked.compressstore.v7f32(<7 x float>, float*, <7 x i1>)
// CHECK-DAG: declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg) // CHECK-DAG: declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg)
// CHECK-DAG: declare void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64 immarg, i1 immarg) // CHECK-DAG: declare void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64 immarg, i1 immarg)