[MC][SVE] Fix data operand for instruction alias of `st1d`.

[fpetrogalli]

Summary

The version of st1d that operates with vector plus immediate
addressing mode uses the alias st1d { <Zn>.d }, <Pg>, [<Za>.d] for
rendering st1d { <Zn>.d }, <Pg>, [<Za>.d, #0]. The disassembler was
generating <Zn>.s instead of <Zn>.d>.

The patch also adds test coverage for the same aliases for the b,
h and w version of the instruction st1<T>.

[paulwalker-arm]

llvm/test/MC/AArch64/SVE/st1d.s

82

Does this mean we're also missing test coverage for st1b, st1h & st1w variants?

Is it worth also testing st1d { z0.d }, p7, [z0.d] directly.

[fpetrogalli]

I have added test coverage for st1[bhwd] for both .s and .d version of the alias for [<Za>.<T>, #0].

llvm/lib/Target/AArch64/SVEInstrFormats.td

multiclass sve_mem_64b_sst_vi_ptrs<bits<3> opc, string asm,
                                    ValueType vt> {
   def _IMM : sve_mem_sst_vi<opc, asm, ZPR64, Z_d, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
                   (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
                   (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME # _IMM) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
 
   def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt),
             (!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
 }
 
 class sve_mem_z_spill<string asm>
 : I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9),
   asm, "\t$Zt, [$Rn, $imm9, mul vl]",

llvm/test/MC/AArch64/SVE/st1d.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 a0 a0 e5 <unknown>
 
 st1d    { z31.d }, p7, [z31.d, #248]
 // CHECK-INST: st1d    { z31.d }, p7, [z31.d, #248]
 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xe5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf df e5 <unknown>
+
+st1d    { z0.d }, p7, [z0.d, #0]
+// CHECK-INST: st1d    { z0.d }, p7, [z0.d]
+// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc c0 e5 <unknown>