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Differential D86633

[MC][SVE] Fix data operand for instruction alias of `st1d`.
ClosedPublic

Authored by fpetrogalli on Aug 26 2020, 8:57 AM.

Details

Reviewers
awarzynski
paulwalker-arm
efriedma
Commits
rG61dfa009579f: [MC][SVE] Fix data operand for instruction alias of `st1d`.
Summary

The version of st1d that operates with vector plus immediate
addressing mode uses the alias st1d { <Zn>.d }, <Pg>, [<Za>.d] for
rendering st1d { <Zn>.d }, <Pg>, [<Za>.d, #0]. The disassembler was
generating <Zn>.s instead of <Zn>.d>.

The patch also adds test coverage for the same aliases for the b,
h and w version of the instruction st1<T>.

Diff Detail

Event Timeline

fpetrogalli created this revision.Aug 26 2020, 8:57 AM
Herald added a reviewer: efriedma. · View Herald TranscriptAug 26 2020, 8:57 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett. · View Herald Transcript
fpetrogalli requested review of this revision.Aug 26 2020, 8:57 AM
paulwalker-arm added inline comments.Aug 26 2020, 9:14 AM
llvm/test/MC/AArch64/SVE/st1d.s
82

Does this mean we're also missing test coverage for st1b, st1h & st1w variants?

Is it worth also testing st1d { z0.d }, p7, [z0.d] directly.

Harbormaster completed remote builds in B69615: Diff 287999.Aug 26 2020, 9:32 AM
fpetrogalli updated this revision to Diff 288030.Aug 26 2020, 10:19 AM

I have added test coverage for st1[bhwd] for both .s and .d version of the alias for [<Za>.<T>, #0].

fpetrogalli edited the summary of this revision. (Show Details)Aug 26 2020, 10:21 AM
fpetrogalli marked an inline comment as done.
paulwalker-arm accepted this revision.Aug 26 2020, 10:42 AM
This revision is now accepted and ready to land.Aug 26 2020, 10:42 AM
Harbormaster completed remote builds in B69632: Diff 288030.Aug 26 2020, 11:10 AM
Closed by commit rG61dfa009579f: [MC][SVE] Fix data operand for instruction alias of `st1d`. (authored by fpetrogalli). · Explain WhyAug 26 2020, 11:23 AM
This revision was automatically updated to reflect the committed changes.
fpetrogalli added a commit: rG61dfa009579f: [MC][SVE] Fix data operand for instruction alias of `st1d`..

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
2 lines
test/
MC/
AArch64/
SVE/
24 lines
12 lines
24 lines
24 lines

Diff 288053

llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,481 Lines • ▼ Show 20 Linesmulticlass sve_mem_64b_sst_vi_ptrs<bits<3> opc, string asm,
ValueType vt> { ValueType vt> {
def _IMM : sve_mem_sst_vi<opc, asm, ZPR64, Z_d, imm_ty>; def _IMM : sve_mem_sst_vi<opc, asm, ZPR64, Z_d, imm_ty>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]", def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
(!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>; (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]", def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
(!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>; (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]", def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
(!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>; (!cast<Instruction>(NAME # _IMM) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt), def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt),
(!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>; (!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
} }
class sve_mem_z_spill<string asm> class sve_mem_z_spill<string asm>
: I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9), : I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9),
asm, "\t$Zt, [$Rn, $imm9, mul vl]", asm, "\t$Zt, [$Rn, $imm9, mul vl]",
▲ Show 20 Lines • Show All 2,427 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/st1b.s

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 7f e4 <unknown> // CHECK-UNKNOWN: ff bf 7f e4 <unknown>
st1b { z31.d }, p7, [z31.d, #31] st1b { z31.d }, p7, [z31.d, #31]
// CHECK-INST: st1b { z31.d }, p7, [z31.d, #31] // CHECK-INST: st1b { z31.d }, p7, [z31.d, #31]
// CHECK-ENCODING: [0xff,0xbf,0x5f,0xe4] // CHECK-ENCODING: [0xff,0xbf,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 5f e4 <unknown> // CHECK-UNKNOWN: ff bf 5f e4 <unknown>
st1b { z0.s }, p7, [z0.s, #0]
// CHECK-INST: st1b { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 60 e4 <unknown>
st1b { z0.s }, p7, [z0.s]
// CHECK-INST: st1b { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 60 e4 <unknown>
st1b { z0.d }, p7, [z0.d, #0]
// CHECK-INST: st1b { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 40 e4 <unknown>
st1b { z0.d }, p7, [z0.d]
// CHECK-INST: st1b { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 40 e4 <unknown>

llvm/test/MC/AArch64/SVE/st1d.s

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 a0 e5 <unknown> // CHECK-UNKNOWN: 00 a0 a0 e5 <unknown>
st1d { z31.d }, p7, [z31.d, #248] st1d { z31.d }, p7, [z31.d, #248]
// CHECK-INST: st1d { z31.d }, p7, [z31.d, #248] // CHECK-INST: st1d { z31.d }, p7, [z31.d, #248]
// CHECK-ENCODING: [0xff,0xbf,0xdf,0xe5] // CHECK-ENCODING: [0xff,0xbf,0xdf,0xe5]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf df e5 <unknown> // CHECK-UNKNOWN: ff bf df e5 <unknown>
st1d { z0.d }, p7, [z0.d, #0]
paulwalker-armUnsubmitted
Done
ReplyInline Actions

Does this mean we're also missing test coverage for st1b, st1h & st1w variants?

Is it worth also testing st1d { z0.d }, p7, [z0.d] directly.

paulwalker-arm: Does this mean we're also missing test coverage for st1b, st1h & st1w variants? Is it worth…
// CHECK-INST: st1d { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc c0 e5 <unknown>
st1d { z0.d }, p7, [z0.d]
// CHECK-INST: st1d { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc c0 e5 <unknown>

llvm/test/MC/AArch64/SVE/st1h.s

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf ff e4 <unknown> // CHECK-UNKNOWN: ff bf ff e4 <unknown>
st1h { z31.d }, p7, [z31.d, #62] st1h { z31.d }, p7, [z31.d, #62]
// CHECK-INST: st1h { z31.d }, p7, [z31.d, #62] // CHECK-INST: st1h { z31.d }, p7, [z31.d, #62]
// CHECK-ENCODING: [0xff,0xbf,0xdf,0xe4] // CHECK-ENCODING: [0xff,0xbf,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf df e4 <unknown> // CHECK-UNKNOWN: ff bf df e4 <unknown>
st1h { z0.s }, p7, [z0.s, #0]
// CHECK-INST: st1h { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc e0 e4 <unknown>
st1h { z0.s }, p7, [z0.s]
// CHECK-INST: st1h { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc e0 e4 <unknown>
st1h { z0.d }, p7, [z0.d, #0]
// CHECK-INST: st1h { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc c0 e4 <unknown>
st1h { z0.d }, p7, [z0.d]
// CHECK-INST: st1h { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc c0 e4 <unknown>

llvm/test/MC/AArch64/SVE/st1w.s

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 7f e5 <unknown> // CHECK-UNKNOWN: ff bf 7f e5 <unknown>
st1w { z31.d }, p7, [z31.d, #124] st1w { z31.d }, p7, [z31.d, #124]
// CHECK-INST: st1w { z31.d }, p7, [z31.d, #124] // CHECK-INST: st1w { z31.d }, p7, [z31.d, #124]
// CHECK-ENCODING: [0xff,0xbf,0x5f,0xe5] // CHECK-ENCODING: [0xff,0xbf,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 5f e5 <unknown> // CHECK-UNKNOWN: ff bf 5f e5 <unknown>
st1w { z0.s }, p7, [z0.s, #0]
// CHECK-INST: st1w { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0x60,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 60 e5 <unknown>
st1w { z0.s }, p7, [z0.s]
// CHECK-INST: st1w { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0x60,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 60 e5 <unknown>
st1w { z0.d }, p7, [z0.d, #0]
// CHECK-INST: st1w { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0x40,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 40 e5 <unknown>
st1w { z0.d }, p7, [z0.d]
// CHECK-INST: st1w { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0x40,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 40 e5 <unknown>