AMDGPU: Correct definitions for global saddr instructions

[arsenm]

Summary

The VGPR component is a 32-bit offset, not 64-bits.

I'm not sure what the correct syntax is for this. This maintains the
vaddr position and leaves saddr in the end "off" position. This is
particularly terrible for stores, since the operand order is now <vgpr
offset>, <data>, <sgpr base>, splitting the pointer operands. I
suppose this is a logical consequence from the mistake of not putting
the data operand first. I'm not sure what sp3 does.

[arsenm]

Fix disassembler tests

[rampitec]

LGTM.

[dp]

LGTM.
The syntax is terrible but at least it is sp3-compatible.

[dp]

This change fixes bug 35436.
https://bugs.llvm.org/show_bug.cgi?id=35436

[arsenm]

47af1ac69af90f87ad6e365310db6d1e2b28be9e

llvm/lib/Target/AMDGPU/FLATInstructions.td

 // saddr is 32-bit (which isn't handled here yet).
 class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
   bit HasTiedOutput = 0,
   bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
   opName,
   (outs regClass:$vdst),
   !con(
     !con(
-      !con((ins VReg_64:$vaddr),
-        !if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
-          (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
-          !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
+      !if(EnableSaddr,
+        (ins SReg_64:$saddr, VGPR_32:$vaddr),
+        (ins VReg_64:$vaddr)),
   " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
   let has_data = 0;
   let mayLoad = 1;
   let has_saddr = HasSaddr;
   let enabled_saddr = EnableSaddr;
   let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
   let maybeAtomic = 1;
 
   let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
   let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
 }
 
 class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
   bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
   opName,
   (outs),
   !con(
-    !con((ins VReg_64:$vaddr, vdataClass:$vdata),
-      !if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
-        (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
+    !if(EnableSaddr,
+      (ins VGPR_32:$vaddr, vdataClass:$vdata, SReg_64:$saddr),
+      (ins VReg_64:$vaddr, vdataClass:$vdata)),
   " $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
   let mayLoad  = 0;
   let mayStore = 1;
   let has_vdst = 0;
   let has_saddr = HasSaddr;
   let enabled_saddr = EnableSaddr;
   let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
   let maybeAtomic = 1;

llvm/test/CodeGen/AMDGPU/sdwa-ops.mir

bb.0:
     %1:sgpr_64 = COPY $sgpr0_sgpr1
     %0:vgpr_32 = COPY $vgpr0
     %22:sreg_32_xm0 = S_MOV_B32 255
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %30:vreg_64 = COPY $sgpr0_sgpr1
     %63:vgpr_32, %65:sreg_64_xexec = nsw V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     %64:vgpr_32, dead %66:sreg_64_xexec = nuw V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
     %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec
     %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
     %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
     %171:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %173:vgpr_32, %175:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %171, 0, implicit $exec
     %174:vgpr_32, dead %176:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %175, 0, implicit $exec
     %172:vreg_64 = REG_SEQUENCE %173, %subreg.sub0, %174, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %172, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %172, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 ...
 
 # test for VCC interference on sdwa, should generate 1 xform only
 # GFX9-LABEL: name:            test2_add_co_sdwa
 # GFX9: V_ADD_CO_U32_sdwa
 # GFX9: V_ADDC_U32_e32
 # GFX9-NOT: V_ADD_CO_U32_sdwa
bb.0:
 
     %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec
     %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
     %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
 
     %64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
     %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec
     %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
     %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 ...
 
 # test for CarryOut used, should reject
 # GFX9-LABEL: name:            test3_add_co_sdwa
 # GFX9: V_ADD_CO_U32_e64
 # GFX9: V_ADDC_U32_e64
 # GFX9-NOT: V_ADD_CO_U32_sdwa
bb.0:
     %1:sgpr_64 = COPY $sgpr0_sgpr1
     %0:vgpr_32 = COPY $vgpr0
     %22:sreg_32_xm0 = S_MOV_B32 255
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %30:vreg_64 = COPY $sgpr0_sgpr1
     %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %66, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 ...
 
 # test for CarryIn used more than once, should reject
 # GFX9-LABEL: name:            test4_add_co_sdwa
 # GFX9: V_ADD_CO_U32_e64
 # GFX9: V_ADDC_U32_e64
 # GFX9-NOT: V_ADD_CO_U32_sdwa
bb.0:
     %1:sgpr_64 = COPY $sgpr0_sgpr1
     %0:vgpr_32 = COPY $vgpr0
     %22:sreg_32_xm0 = S_MOV_B32 255
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %30:vreg_64 = COPY $sgpr0_sgpr1
     %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %65, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 
 ...
 
 # test for simple example, should generate sdwa
 # GFX9-LABEL: name:            test5_add_co_sdwa
 # GFX9: V_ADD_CO_U32_sdwa
 # GFX9: V_ADDC_U32_e32
bb.0:
     %1:sgpr_64 = COPY $sgpr0_sgpr1
     %0:vgpr_32 = COPY $vgpr0
     %22:sreg_32_xm0 = S_MOV_B32 255
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %30:vreg_64 = COPY $sgpr0_sgpr1
     %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 
 ...
 
 # test for V_ADD_CO_U32_e64 only, should reject
 # GFX9-LABEL: name:            test6_add_co_sdwa
 # GFX9: V_ADD_CO_U32_e64
 # GFX9-NOT: V_ADD_CO_U32_sdwa
bb.0:
 
     %1:sgpr_64 = COPY $sgpr0_sgpr1
     %0:vgpr_32 = COPY $vgpr0
     %22:sreg_32_xm0 = S_MOV_B32 255
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %30:vreg_64 = COPY $sgpr0_sgpr1
     %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %23, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 
 ...
 
 # test for V_ADDC_U32_e64 only, should reject
 # GFX9-LABEL: name:            test7_add_co_sdwa
 # GFX9: V_ADDC_U32_e64
 # GFX9-NOT: V_ADD_CO_U32_sdwa
bb.0:
     %0:vgpr_32 = COPY $vgpr0
     %22:sreg_32_xm0 = S_MOV_B32 255
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %24:sreg_64_xexec = COPY $sgpr0_sgpr1
 
     %30:vreg_64 = COPY $sgpr0_sgpr1
     %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %24, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %23, %subreg.sub0, %23, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 
 ...
 
 # test for $vcc defined between two adds, should not generate
 # GFX9-LABEL: name:            test8_add_co_sdwa
 # GFX9-NOT: V_ADD_CO_U32_sdwa
 # GFX9: V_ADDC_U32_e64
bb.0:
     %22:sreg_32_xm0 = S_MOV_B32 255
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %30:vreg_64 = COPY $sgpr0_sgpr1
     %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     $vcc = COPY %30
     %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
     %31:vreg_64 = COPY $vcc
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 
 ...
 
 # test for non dead $vcc, should not generate
 # GFX9-LABEL: name:            test9_add_co_sdwa
 # GFX9-NOT: V_ADD_CO_U32_sdwa
 # GFX9: V_ADDC_U32_e64
bb.0:
     %22:sreg_32_xm0 = S_MOV_B32 255
     %30:vreg_64 = COPY $sgpr0_sgpr1
     $vcc = COPY %30
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
     %31:vreg_64 = COPY $vcc
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 ...
 
 # test for def $vcc_lo, should not generate
 # GFX9-LABEL: name:            test10_add_co_sdwa
 # GFX9-NOT: V_ADD_CO_U32_sdwa
 # GFX9: V_ADDC_U32_e64
 ---
bb.0:
     %30:vreg_64 = COPY $sgpr0_sgpr1
     $vcc_lo = COPY %30.sub0
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     %31:vgpr_32 = COPY $vcc_lo
     %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1
     %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %32.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 ...
 
 # test for read $vcc_hi, should not generate
 # GFX9-LABEL: name:            test11_add_co_sdwa
 # GFX9-NOT: V_ADD_CO_U32_sdwa
 # GFX9: V_ADDC_U32_e64
 ---
bb.0:
     %30:vreg_64 = COPY $sgpr0_sgpr1
     $vcc_hi = COPY %30.sub0
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     %31:vgpr_32 = COPY $vcc_hi
     %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1
     %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %32.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 
 ...
 
 # test for $vcc defined and used between adds, should not generate
 # GFX9-LABEL: name:            test12_add_co_sdwa
 # GFX9-NOT: V_ADD_CO_U32_sdwa
 # GFX9: V_ADDC_U32_e64
 ---
bb.0:
     %22:sreg_32_xm0 = S_MOV_B32 255
     %30:vreg_64 = COPY $sgpr0_sgpr1
     %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
     %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
     $vcc = COPY %30
     %31:vreg_64 = COPY killed $vcc
     %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
     %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
-    GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
+    GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
 

llvm/test/MC/AMDGPU/flat-global.s

 global_store_dwordx4 v[3:4], v[1:4], off dlc
 // GFX10: encoding: [0x00,0x90,0x78,0xdc,0x03,0x01,0x7d,0x00]
 // GFX9-ERR: error: failed parsing operand
 // VI-ERR: error: invalid operand for instruction
 
 global_store_dword v[3:4], v1, off offset:12
 // GFX10: encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00]
 // GFX9: global_store_dword v[3:4], v1, off offset:12 ; encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x7f,0x00]
-// VI-ERR: :36: error: not a valid operand
+// VI-ERR: [[@LINE-3]]:36: error: not a valid operand
 
-global_load_dword v1, v[3:4], s[2:3]
+global_load_dword v1, v3, s[2:3]
 // GFX10: encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x02,0x01]
-// GFX9: global_load_dword v1, v[3:4], s[2:3] ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x02,0x01]
-// VI-ERR: instruction not supported on this GPU
+// GFX9: global_load_dword v1, v3, s[2:3] ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x02,0x01]
+// VI-ERR: [[@LINE-3]]:1: error: instruction not supported on this GPU
 
-global_load_dword v1, v[3:4], s[2:3] offset:24
+global_load_dword v1, v3, s[2:3] offset:24
 // GFX10: encoding: [0x18,0x80,0x30,0xdc,0x03,0x00,0x02,0x01]
-// GFX9: global_load_dword v1, v[3:4], s[2:3] offset:24 ; encoding: [0x18,0x80,0x50,0xdc,0x03,0x00,0x02,0x01]
-// VI-ERR: :38: error: not a valid operand.
+// GFX9: global_load_dword v1, v3, s[2:3] offset:24 ; encoding: [0x18,0x80,0x50,0xdc,0x03,0x00,0x02,0x01]
+// VI-ERR: [[@LINE-3]]:34: error: not a valid operand.
 
-global_load_dword v1, v[3:4], s[2:3] offset:-8
+global_load_dword v1, v3, s[2:3] offset:-8
 // GFX10: encoding: [0xf8,0x8f,0x30,0xdc,0x03,0x00,0x02,0x01]
-// GFX9: global_load_dword v1, v[3:4], s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x50,0xdc,0x03,0x00,0x02,0x01]
-// VI-ERR: :38: error: not a valid operand.
+// GFX9: global_load_dword v1, v3, s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x50,0xdc,0x03,0x00,0x02,0x01]
+// VI-ERR: [[@LINE-3]]:34: error: not a valid operand.
 
-global_store_dword v[3:4], v1, s[2:3]
+global_store_dword v3, v1, s[2:3]
 // GFX10: encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
-// GFX9: global_store_dword v[3:4], v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
+// GFX9: global_store_dword v3, v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
 // VI-ERR: instruction not supported on this GPU
 
-global_store_dword v[3:4], v1, s[2:3] offset:24
+global_store_dword v3, v1, s[2:3] offset:24
 // GFX10: encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
-// GFX9: global_store_dword v[3:4], v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
-// VI-ERR: :39: error: not a valid operand.
+// GFX9: global_store_dword v3, v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
+// VI-ERR: [[@LINE-3]]:35: error: not a valid operand.
 
-global_store_dword v[3:4], v1, s[2:3] offset:-8
+global_store_dword v3, v1, s[2:3] offset:-8
 // GFX10: encoding: [0xf8,0x8f,0x70,0xdc,0x03,0x01,0x02,0x00]
-// GFX9: global_store_dword v[3:4], v1, s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x70,0xdc,0x03,0x01,0x02,0x00]
-// VI-ERR: :39: error: not a valid operand.
+// GFX9: global_store_dword v3, v1, s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x70,0xdc,0x03,0x01,0x02,0x00]
+// VI-ERR: :35: error: not a valid operand.
 
 // XXX: Is this valid?
-global_store_dword v[3:4], v1, exec
+global_store_dword v3, v1, exec
 // GFX10: encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00]
-// GFX9: global_store_dword v[3:4], v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00]
+// GFX9: global_store_dword v3, v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00]
 // VI-ERR: instruction not supported on this GPU
 
 global_load_dword v1, v[3:4], s2
 // GFX10-ERR: error: invalid operand for instruction
 // GFX9-ERR: :31: error: invalid operand for instruction
 // VI-ERR: :31: error: invalid operand for instruction
 
 global_load_dword v1, v[3:4], exec_hi

llvm/test/MC/AMDGPU/gfx1030_new.s

 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1031 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
 
 global_load_dword_addtid v1, s[2:3] offset:16
 // GFX10: encoding: [0x10,0x80,0x58,0xdc,0x00,0x00,0x02,0x01]
 
 global_load_dword_addtid v1, s[2:3] offset:16 glc slc dlc
 // GFX10: encoding: [0x10,0x90,0x5b,0xdc,0x00,0x00,0x02,0x01]
 
 global_store_dword_addtid v1, s[2:3] offset:16 glc slc dlc
 // GFX10: encoding: [0x10,0x90,0x5f,0xdc,0x00,0x01,0x02,0x00]
 
-global_store_dword v[254:255], v1, s[2:3] offset:16
+global_store_dword v254, v1, s[2:3] offset:16
 // GFX10: encoding: [0x10,0x80,0x70,0xdc,0xfe,0x01,0x02,0x00]
 
 global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc
 // GFX10: encoding: [0x64,0x80,0xd3,0xdc,0x00,0x02,0x7d,0x02]
 
 global_atomic_csub v2, v[0:1], v2, off
 // GFX10: encoding: [0x00,0x80,0xd1,0xdc,0x00,0x02,0x7d,0x02]
 

llvm/test/MC/Disassembler/AMDGPU/flat_gfx9.txt

 0xff,0x8f,0x08,0xdd,0x02,0x04,0x00,0x00
 
 # CHECK: global_atomic_add v[2:3], v4, s[0:1] offset:-4096    ; encoding: [0x00,0x90,0x08,0xdd,0x02,0x04,0x00,0x00]
 0x00,0x90,0x08,0xdd,0x02,0x04,0x00,0x00
 
 # CHECK: global_atomic_add v0, v[2:3], v4, s[0:1] offset:-1 glc    ; encoding: [0xff,0x9f,0x09,0xdd,0x02,0x04,0x00,0x00]
 0xff,0x9f,0x09,0xdd,0x02,0x04,0x00,0x00
 
-# CHECK: global_load_sbyte v0, v[2:3], s[0:1]    ; encoding: [0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00]
+# CHECK: global_load_sbyte v0, v2, s[0:1]    ; encoding: [0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00]
 0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00
 
-# CHECK: global_load_sbyte v0, v[2:3], s[0:1] offset:4095    ; encoding: [0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00]
+# CHECK: global_load_sbyte v0, v2, s[0:1] offset:4095    ; encoding: [0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00]
 0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00
 
-# CHECK: global_load_sbyte v0, v[2:3], s[0:1] offset:-4096    ; encoding: [0x00,0x90,0x44,0xdc,0x02,0x00,0x00,0x00]
+# CHECK: global_load_sbyte v0, v2, s[0:1] offset:-4096    ; encoding: [0x00,0x90,0x44,0xdc,0x02,0x00,0x00,0x00]
 0x00,0x90,0x44,0xdc,0x02,0x00,0x00,0x00
 
-# CHECK: global_store_dwordx2 v[2:3], v[4:5], s[0:1]    ; encoding: [0x00,0x80,0x74,0xdc,0x02,0x04,0x00,0x00]
+# CHECK: global_store_dwordx2 v2, v[4:5], s[0:1]    ; encoding: [0x00,0x80,0x74,0xdc,0x02,0x04,0x00,0x00]
 0x00,0x80,0x74,0xdc,0x02,0x04,0x00,0x00
 
-# CHECK: global_store_dwordx2 v[2:3], v[4:5], s[0:1] offset:4095    ; encoding: [0xff,0x8f,0x74,0xdc,0x02,0x04,0x00,0x00]
+# CHECK: global_store_dwordx2 v2, v[4:5], s[0:1] offset:4095    ; encoding: [0xff,0x8f,0x74,0xdc,0x02,0x04,0x00,0x00]
 0xff,0x8f,0x74,0xdc,0x02,0x04,0x00,0x00
 
-# CHECK: global_store_dwordx2 v[2:3], v[4:5], s[0:1] offset:-4096    ; encoding: [0x00,0x90,0x74,0xdc,0x02,0x04,0x00,0x00]
+# CHECK: global_store_dwordx2 v2, v[4:5], s[0:1] offset:-4096    ; encoding: [0x00,0x90,0x74,0xdc,0x02,0x04,0x00,0x00]
 0x00,0x90,0x74,0xdc,0x02,0x04,0x00,0x00
 
 # CHECK: scratch_load_dword v0, v0, off offset:-1    ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x7f,0x00]
 0xff,0x5f,0x50,0xdc,0x00,0x00,0x7f,0x00
 
 # CHECK: scratch_load_dword v0, off, s0    ; encoding: [0x00,0x40,0x50,0xdc,0x00,0x00,0x00,0x00]
 0x00,0x40,0x50,0xdc,0x00,0x00,0x00,0x00
 

llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt

 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx1031 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
 
 # GFX10: global_load_dword_addtid v1, s[2:3] offset:16
 0x10,0x80,0x58,0xdc,0x00,0x00,0x02,0x01
 
 # GFX10: global_load_dword_addtid v1, s[2:3] offset:16 glc slc dlc
 0x10,0x90,0x5b,0xdc,0x00,0x00,0x02,0x01
 
 # GFX10: global_store_dword_addtid v1, s[2:3] offset:16 glc slc dlc
 0x10,0x90,0x5f,0xdc,0x00,0x01,0x02,0x00
 
-# GFX10: global_store_dword v[254:255], v1, s[2:3] offset:16
+# GFX10: global_store_dword v254, v1, s[2:3] offset:16
 0x10,0x80,0x70,0xdc,0xfe,0x01,0x02,0x00
 
 # GFX10: global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc
 0x64,0x80,0xd3,0xdc,0x00,0x02,0x7d,0x02
 
 # GFX10: global_atomic_csub v2, v[0:1], v2, off glc
 0x00,0x80,0xd1,0xdc,0x00,0x02,0x7d,0x02
 

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 0x00,0x80,0x30,0xdc,0x03,0x00,0x7d,0x01
 
 # GFX10: global_load_dword v1, v[3:4], off dlc ; encoding: [0x00,0x90,0x30,0xdc,0x03,0x00,0x7d,0x01]
 0x00,0x90,0x30,0xdc,0x03,0x00,0x7d,0x01
 
 # GFX10: global_load_dword v1, v[3:4], off offset:2047 ; encoding: [0xff,0x87,0x30,0xdc,0x03,0x00,0x7d,0x01]
 0xff,0x87,0x30,0xdc,0x03,0x00,0x7d,0x01
 
-# GFX10: global_load_dword v1, v[3:4], s[2:3] ; encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x02,0x01]
+# GFX10: global_load_dword v1, v3, s[2:3] ; encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x02,0x01]
 0x00,0x80,0x30,0xdc,0x03,0x00,0x02,0x01
 
-# GFX10: global_load_dword v1, v[3:4], s[2:3] offset:2040 ; encoding: [0xf8,0x87,0x30,0xdc,0x03,0x00,0x02,0x01]
+# GFX10: global_load_dword v1, v3, s[2:3] offset:2040 ; encoding: [0xf8,0x87,0x30,0xdc,0x03,0x00,0x02,0x01]
 0xf8,0x87,0x30,0xdc,0x03,0x00,0x02,0x01
 
-# GFX10: global_load_dword v1, v[3:4], s[2:3] offset:24 ; encoding: [0x18,0x80,0x30,0xdc,0x03,0x00,0x02,0x01]
+# GFX10: global_load_dword v1, v3, s[2:3] offset:24 ; encoding: [0x18,0x80,0x30,0xdc,0x03,0x00,0x02,0x01]
 0x18,0x80,0x30,0xdc,0x03,0x00,0x02,0x01
 
 # GFX10: global_load_dwordx2 v[1:2], v[3:4], off ; encoding: [0x00,0x80,0x34,0xdc,0x03,0x00,0x7d,0x01]
 0x00,0x80,0x34,0xdc,0x03,0x00,0x7d,0x01
 
 # GFX10: global_load_dwordx2 v[1:2], v[3:4], off dlc ; encoding: [0x00,0x90,0x34,0xdc,0x03,0x00,0x7d,0x01]
 0x00,0x90,0x34,0xdc,0x03,0x00,0x7d,0x01
 

 0x00,0x80,0x60,0xdc,0x03,0x01,0x7d,0x00
 
 # GFX10: global_store_byte v[3:4], v1, off dlc ; encoding: [0x00,0x90,0x60,0xdc,0x03,0x01,0x7d,0x00]
 0x00,0x90,0x60,0xdc,0x03,0x01,0x7d,0x00
 
 # GFX10: global_store_byte_d16_hi v[3:4], v1, off ; encoding: [0x00,0x80,0x64,0xdc,0x03,0x01,0x7d,0x00]
 0x00,0x80,0x64,0xdc,0x03,0x01,0x7d,0x00
 
-# GFX10: global_store_dword v[3:4], v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00]
+# GFX10: global_store_dword v3, v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00]
 0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00
 
 # GFX10: global_store_dword v[3:4], v1, off ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00]
 0x00,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00
 
 # GFX10: global_store_dword v[3:4], v1, off dlc ; encoding: [0x00,0x90,0x70,0xdc,0x03,0x01,0x7d,0x00]
 0x00,0x90,0x70,0xdc,0x03,0x01,0x7d,0x00
 
 # GFX10: global_store_dword v[3:4], v1, off offset:12 ; encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00]
 0x0c,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00
 
-# GFX10: global_store_dword v[3:4], v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
+# GFX10: global_store_dword v3, v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
 0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00
 
-# GFX10: global_store_dword v[3:4], v1, s[2:3] offset:2040 ; encoding: [0xf8,0x87,0x70,0xdc,0x03,0x01,0x02,0x00]
+# GFX10: global_store_dword v3, v1, s[2:3] offset:2040 ; encoding: [0xf8,0x87,0x70,0xdc,0x03,0x01,0x02,0x00]
 0xf8,0x87,0x70,0xdc,0x03,0x01,0x02,0x00
 
-# GFX10: global_store_dword v[3:4], v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
+# GFX10: global_store_dword v3, v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
 0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00
 
 # GFX10: global_store_dwordx2 v[3:4], v[1:2], off ; encoding: [0x00,0x80,0x74,0xdc,0x03,0x01,0x7d,0x00]
 0x00,0x80,0x74,0xdc,0x03,0x01,0x7d,0x00
 
 # GFX10: global_store_dwordx2 v[3:4], v[1:2], off dlc ; encoding: [0x00,0x90,0x74,0xdc,0x03,0x01,0x7d,0x00]
 0x00,0x90,0x74,0xdc,0x03,0x01,0x7d,0x00