[PowerPC] Add option to control PCRel GOT indirect linker optimization

[stefanp]

Summary

Add a hidden option to the compiler to control a the PC Relative GOT indirect
linker optimization.

If this option is set to false the compiler will no loger produce the
relocations required by the linker to perform the optimization.

[NeHuang]

Overall LGTM. I only have some nits comment/question for the test case and clang-format related issue.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

42

nit: clang-format

llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll

4

nit: can we use -mcpu=pwr10 here?

7

ditto

10

ditto

15

nit: Do we need to keep #0 and attributes #0 = { nounwind } below?

[nemanjai]

I agree with Victor, please remove uses of future and use pwr10. All of this can be addressed when committing - another round of review is not required. LGTM.

llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll

15

Yeah, this doesn't get a stack frame so we gain nothing by having this. Please remove it in this case.

[stefanp]

Fixed the mcpu=future to make it mcpu=pwr10.

[stefanp]

Removed the attribute nounwind as it is not needed in the test case.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

42

I would rather not do clang-format here. I want to have this option look the same as the other one after it.

I can clang-format both options in an NFC patch later.

llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll

4

Thank you for catching that.
That's a copy-paste. :)

[NeHuang]

Thanks! LGTM.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

 //===--------- PPCPreEmitPeephole.cpp - Late peephole optimizations -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // A pre-emit peephole for catching opportunities introduced by late passes such

 STATISTIC(NumRemovedInPreEmit,
           "Number of instructions deleted in pre-emit peephole");
 STATISTIC(NumberOfSelfCopies,
           "Number of self copy instructions eliminated");
 STATISTIC(NumFrameOffFoldInPreEmit,
           "Number of folding frame offset by using r+r in pre-emit peephole");
 
 static cl::opt<bool>
+EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true),
+                     cl::desc("enable PC Relative linker optimization"));
+
+static cl::opt<bool>
 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
                    cl::desc("Run pre-emit peephole optimizations."));
 
 namespace {
 
 static bool hasPCRelativeForm(MachineInstr &Use) {
   switch (Use.getOpcode()) {
   default:
bool isGOTPLDpc(MachineInstr &Instr) {
         return false;
 
       // Finally return true only if the GOT flag is present.
       return (SymbolOp.getTargetFlags() & PPCII::MO_GOT_FLAG);
     }
 
     bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) {
       MachineFunction *MF = MBB.getParent();
+      // If the linker opt is disabled then just return.
+      if (!EnablePCRelLinkerOpt)
+        return false;
+
       // Add this linker opt only if we are using PC Relative memops.
       if (!MF->getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls())
         return false;
 
       // Struct to keep track of one def/use pair for a GOT indirect access.
       struct GOTDefUsePair {
         MachineBasicBlock::iterator DefInst;
         MachineBasicBlock::iterator UseInst;

llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s --check-prefix=DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-pcrel-linker-opt=true < %s | FileCheck %s --check-prefix=ON
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-pcrel-linker-opt=false < %s | FileCheck %s --check-prefix=OFF
+
+@input8 = external local_unnamed_addr global i8, align 1
+
+define dso_local i8 @Read8() local_unnamed_addr {
+; DEFAULT-LABEL: Read8:
+; DEFAULT:       # %bb.0: # %entry
+; DEFAULT-NEXT:    pld r3, input8@got@pcrel(0), 1
+; DEFAULT-NEXT:  .Lpcrel:
+; DEFAULT-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; DEFAULT-NEXT:    lbz r3, 0(r3)
+; DEFAULT-NEXT:    blr
+;
+; ON-LABEL: Read8:
+; ON:       # %bb.0: # %entry
+; ON-NEXT:    pld r3, input8@got@pcrel(0), 1
+; ON-NEXT:  .Lpcrel:
+; ON-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; ON-NEXT:    lbz r3, 0(r3)
+; ON-NEXT:    blr
+;
+; OFF-LABEL: Read8:
+; OFF:       # %bb.0: # %entry
+; OFF-NEXT:    pld r3, input8@got@pcrel(0), 1
+; OFF-NEXT:    lbz r3, 0(r3)
+; OFF-NEXT:    blr
+entry:
+  %0 = load i8, i8* @input8, align 1
+  ret i8 %0
+}