Refactor: Simplify boolean expressions in AArch64 target

[LegalizeAdulthood]

Summary

Simplify boolean expressions using true and false with clang-tidy

[rengolin]

On all three instances, please, keep the parenthesis, to avoid future problems with order of operators.

[alexfh]

In D8525#144898, @rengolin wrote:

On all three instances, please, keep the parenthesis, to avoid future problems with order of operators.

Do you find the order of operations unclear as it is now or do you expect confusion later if the code is changed?

I personally find return a < b; nicer and more consistent with existing code than return (a < b);.

[rengolin]

I guess you're right. Let it be for whomever change this to make sure operator precedence is followed. LGTM, Thanks!

[LegalizeAdulthood]

Can someone commit this for me, please? I don't have commit access.

Patch by Richard Thomson

[LegalizeAdulthood]

Can someone commit this for me, please? I don't have commit access.

Patch by Richard Thomson

[dblaikie]

Committed in r233089

lib/Target/AArch64/AArch64FastISel.cpp

bool AArch64FastISel::selectShift(const Instruction *I) {
 
   if (RetVT.isVector())
     return selectOperator(I, I->getOpcode());
 
   if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
     unsigned ResultReg = 0;
     uint64_t ShiftVal = C->getZExtValue();
     MVT SrcVT = RetVT;
-    bool IsZExt = (I->getOpcode() == Instruction::AShr) ? false : true;
+    bool IsZExt = I->getOpcode() != Instruction::AShr;
     const Value *Op0 = I->getOperand(0);
     if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
       if (!isIntExtFree(ZExt)) {
         MVT TmpVT;
         if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), TmpVT)) {
           SrcVT = TmpVT;
           IsZExt = true;
           Op0 = ZExt->getOperand(0);

lib/Target/AArch64/AArch64ISelLowering.cpp

getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
   case ISD::USUBO:
     Opc = AArch64ISD::SUBS;
     CC = AArch64CC::LO;
     break;
   // Multiply needs a little bit extra work.
   case ISD::SMULO:
   case ISD::UMULO: {
     CC = AArch64CC::NE;
-    bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
+    bool IsSigned = Op.getOpcode() == ISD::SMULO;
     if (Op.getValueType() == MVT::i32) {
       unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
       // For a 32 bit multiply with overflow check we want the instruction
       // selector to generate a widening multiply (SMADDL/UMADDL). For that we
       // need to generate the following pattern:
       // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
       LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
       RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
   if ((int64_t)Val < 0)
     Val = ~Val;
   if (BitSize == 32)
     Val &= (1LL << 32) - 1;
 
   unsigned LZ = countLeadingZeros((uint64_t)Val);
   unsigned Shift = (63 - LZ) / 16;
   // MOVZ is free so return true for one or fewer MOVK.
-  return (Shift < 3) ? true : false;
+  return Shift < 3;
 }
 
 // Generate SUBS and CSEL for integer abs.
 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
   EVT VT = N->getValueType(0);
 
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);