[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.

[HsiangKai]

Summary

Implement vmsge{u}.vx pseudo instruction.

According to RISC-V V specification, there are different scenarios for this pseudo instruction. I list them below.

unmasked va >= x

  pseudoinstruction: vmsge{u}.vx vd, va, x
  expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd

masked va >= x, vd != v0

  pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
  expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0

masked va >= x, vd == v0

  pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
  expansion: vmslt{u}.vx vt, va, x;  vmandnot.mm vd, vd, vt

Use pseudo instruction to model vmsge{u}.vx. The pseudo instruction will convert to different expansion according to the condition.

[HsiangKai]

Fix problems when rebasing.

[HsiangKai]

Apply clang-format.

[HsiangKai]

Ping.

[rogfer01]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

239

This assertion can be triggered by assembling the following instruction using llvm-mc --triple riscv64 -mattr +experimental-v --filetype=obj

vmsge.vx v0, v1, x10, v0.t

perhaps we could consider having a specific operand VRegOpNoV0 (or similar) which rejects v0 here?

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

653

I was confused by the fact that this seems an unnecessary inst alias. However if we remove it, then vmsgeu.vx $vd, $va, $rs1 gets parsed as PseudoVMSGEU_VX_M but without a mask (according to llvm-mc --show-inst)

# <MCInst #253 PseudoVMSGEU_VX_M
#  <MCOperand Reg:5>
#  <MCOperand Reg:6>
#  <MCOperand Reg:45>
#  <MCOperand Reg:0>>

however the pseudo PseudoVMSGEU_VX is explicitly unmasked.

I suggest to add a comment like this

// This apparently unnecessary alias prevents matching `vmsgeu.vx vd, vsrc2, rsrc1`
// as if it were an umasked  (i.e. $vm = RISCV::NoRegister) PseudoVMSGEU_VX_M.

655

And a comment here, something like

See comment above. This avoids matching an unmasked `PseudoVMSGE_VX_M`

[HsiangKai]

Add VRNoV0 register class.

[HsiangKai]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

239

I added a new register class for it and added test cases.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

653

If we have no such alias. How do we match vmsge{v}.vx v0, v1, x10? It may match to PseudoVMSGE_VX_M with NoRegister mask. However, the register class for the destination operand is VRNoV0 now. There is no way to match it under the VRNoV0 register class restriction.

[rogfer01]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

165 ↗

(On Diff #287294)

We don't want this now as we are never going to disassemble a vmsge{u}.vx instruction.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

632

These are for the assembler parser only, I think it makes sense to mark them with isAsmParserOnly = 1 as well.

What do you think?

653

Sorry I wasn't clear.

I'm not saying we don't need the InstAlias. We do. The reason is that masked versions need a scratch operand if the destination register is v0.

I suggested a comment because at a first glance the InstAlias seems unnecessary, as if it were only forwarding its operands to the pseudo instruction.

I'm happy if you think there is no need for such a comment here.

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

632

It makes sense. Thanks.

653

Sorry, I misunderstood you. It makes sense to add such comments.

[HsiangKai]

Update according to @rogfer01's comments.

[evandro]

LGTM

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

public:
   void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
                           SmallVectorImpl<MCFixup> &Fixups,
                           const MCSubtargetInfo &STI) const;
 
   void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
                       SmallVectorImpl<MCFixup> &Fixups,
                       const MCSubtargetInfo &STI) const;
 
+  void expandVMSGE(const MCInst &MI, raw_ostream &OS,
+                   SmallVectorImpl<MCFixup> &Fixups,
+                   const MCSubtargetInfo &STI) const;
+
   /// TableGen'erated function for getting the binary encoding for an
   /// instruction.
   uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
 
   /// Return binary encoding of operand. If the machine operand requires
   /// relocation, record the relocation and return zero.
void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
   MCInst TmpInst = MCInstBuilder(RISCV::ADD)
                        .addOperand(DestReg)
                        .addOperand(SrcReg)
                        .addOperand(TPReg);
   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
   support::endian::write(OS, Binary, support::little);
 }
 
+void RISCVMCCodeEmitter::expandVMSGE(const MCInst &MI, raw_ostream &OS,
+                                     SmallVectorImpl<MCFixup> &Fixups,
+                                     const MCSubtargetInfo &STI) const {
+  MCInst TmpInst;
+  uint32_t Binary;
+  unsigned Opcode;
+  switch (MI.getOpcode()) {
+  default:
+    llvm_unreachable("Unexpacted opcode. It should be vmsgeu.vx or vmsge.vx.");
+  case RISCV::PseudoVMSGEU_VX:
+  case RISCV::PseudoVMSGEU_VX_M:
+  case RISCV::PseudoVMSGEU_VX_M_T:
+    Opcode = RISCV::VMSLTU_VX;
+    break;
+  case RISCV::PseudoVMSGE_VX:
+  case RISCV::PseudoVMSGE_VX_M:
+  case RISCV::PseudoVMSGE_VX_M_T:
+    Opcode = RISCV::VMSLT_VX;
+    break;
+  }
+  if (MI.getNumOperands() == 3) {
+    // unmasked va >= x
+    //
+    //  pseudoinstruction: vmsge{u}.vx vd, va, x
+    //  expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
+    TmpInst = MCInstBuilder(Opcode)
+                  .addOperand(MI.getOperand(0))
+                  .addOperand(MI.getOperand(1))
+                  .addOperand(MI.getOperand(2))
+                  .addReg(RISCV::NoRegister);
+    Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+    support::endian::write(OS, Binary, support::little);
+
+    TmpInst = MCInstBuilder(RISCV::VMNAND_MM)
+                  .addOperand(MI.getOperand(0))
+                  .addOperand(MI.getOperand(0))
+                  .addOperand(MI.getOperand(0));
+    Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+    support::endian::write(OS, Binary, support::little);
+  } else if (MI.getNumOperands() == 4) {
+    // masked va >= x, vd != v0
+    //
+    //  pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
+    //  expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
+    assert(MI.getOperand(0).getReg() != RISCV::V0 &&
+           "The destination register should not be V0.");
+    TmpInst = MCInstBuilder(Opcode)
+                  .addOperand(MI.getOperand(0))
+                  .addOperand(MI.getOperand(1))
+                  .addOperand(MI.getOperand(2))
+                  .addOperand(MI.getOperand(3));
+    Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+    support::endian::write(OS, Binary, support::little);
+
+    TmpInst = MCInstBuilder(RISCV::VMXOR_MM)
+                  .addOperand(MI.getOperand(0))
+                  .addOperand(MI.getOperand(0))
+                  .addReg(RISCV::V0);
+    Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+    support::endian::write(OS, Binary, support::little);
+  } else if (MI.getNumOperands() == 5) {
+    // masked va >= x, vd == v0
+    //
+    //  pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
+    //  expansion: vmslt{u}.vx vt, va, x;  vmandnot.mm vd, vd, vt
+    assert(MI.getOperand(0).getReg() == RISCV::V0 &&
+           "The destination register should be V0.");
+    assert(MI.getOperand(1).getReg() != RISCV::V0 &&
+           "The temporary vector register should not be V0.");
+    TmpInst = MCInstBuilder(Opcode)
+                  .addOperand(MI.getOperand(1))
+                  .addOperand(MI.getOperand(2))
+                  .addOperand(MI.getOperand(3))
+                  .addOperand(MI.getOperand(4));
+    Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+    support::endian::write(OS, Binary, support::little);
+
+    TmpInst = MCInstBuilder(RISCV::VMANDNOT_MM)
+                  .addOperand(MI.getOperand(0))
+                  .addOperand(MI.getOperand(0))
+                  .addOperand(MI.getOperand(1));
+    Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+    support::endian::write(OS, Binary, support::little);
+  }
+}
+
 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
   verifyInstructionPredicates(MI,
                               computeAvailableFeatures(STI.getFeatureBits()));
 
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   // Get byte count of instruction.
void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
   }
 
   if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
     expandAddTPRel(MI, OS, Fixups, STI);
     MCNumEmitted += 1;
     return;
   }
 
+  if (MI.getOpcode() == RISCV::PseudoVMSGEU_VX ||
+      MI.getOpcode() == RISCV::PseudoVMSGE_VX ||
+      MI.getOpcode() == RISCV::PseudoVMSGEU_VX_M ||
+      MI.getOpcode() == RISCV::PseudoVMSGE_VX_M ||
+      MI.getOpcode() == RISCV::PseudoVMSGEU_VX_M_T ||
+      MI.getOpcode() == RISCV::PseudoVMSGE_VX_M_T) {
+    expandVMSGE(MI, OS, Fixups, STI);
+    return;
+  }
+
   switch (Size) {
   default:
     llvm_unreachable("Unhandled encodeInstruction length!");
   case 2: {
     uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
     support::endian::write<uint16_t>(OS, Bits, support::little);
     break;
   }

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

def : InstAlias<"vmslt.vi $vd, $va, $imm$vm",
                  VMaskOp:$vm), 0>;
 def : InstAlias<"vmsgeu.vi $vd, $va, $imm$vm",
                 (VMSGTU_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
                  VMaskOp:$vm), 0>;
 def : InstAlias<"vmsge.vi $vd, $va, $imm$vm",
                 (VMSGT_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
                  VMaskOp:$vm), 0>;
 
+let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def PseudoVMSGEU_VX : Pseudo<(outs VRegOp:$vd),
+                             (ins VRegOp:$vs2, GPR:$rs1),
+                             [], "vmsgeu.vx", "$vd, $vs2, $rs1">;
+def PseudoVMSGE_VX : Pseudo<(outs VRegOp:$vd),
+                            (ins VRegOp:$vs2, GPR:$rs1),
+                            [], "vmsge.vx", "$vd, $vs2, $rs1">;
+def PseudoVMSGEU_VX_M : Pseudo<(outs VRNoV0:$vd),
+                               (ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
+                               [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm">;
+def PseudoVMSGE_VX_M : Pseudo<(outs VRNoV0:$vd),
+                              (ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
+                              [], "vmsge.vx", "$vd, $vs2, $rs1$vm">;
+def PseudoVMSGEU_VX_M_T : Pseudo<(outs VMV0:$vd, VRegOp:$scratch),
+                                 (ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
+                                 [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">;
+def PseudoVMSGE_VX_M_T : Pseudo<(outs VMV0:$vd, VRegOp:$scratch),
+                                (ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
+                                [], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">;
+}
+
+// This apparently unnecessary alias prevents matching `vmsge{u}.vx vd, vs2, vs1` as if
+// it were an unmasked (i.e. $vm = RISCV::NoRegister) PseudoVMSGE{U}_VX_M.
+def : InstAlias<"vmsgeu.vx $vd, $va, $rs1",
+                (PseudoVMSGEU_VX VRegOp:$vd, VRegOp:$va, GPR:$rs1), 0>;
+def : InstAlias<"vmsge.vx $vd, $va, $rs1",
+                (PseudoVMSGE_VX VRegOp:$vd, VRegOp:$va, GPR:$rs1), 0>;
+def : InstAlias<"vmsgeu.vx v0, $va, $rs1, $vm, $vt",
+                (PseudoVMSGEU_VX_M_T V0, VRegOp:$vt, VRegOp:$va, GPR:$rs1,
+                                     VMaskOp:$vm), 0>;
+def : InstAlias<"vmsge.vx v0, $va, $rs1, $vm, $vt",
+                (PseudoVMSGE_VX_M_T V0, VRegOp:$vt, VRegOp:$va, GPR:$rs1,
+                                    VMaskOp:$vm), 0>;
+def : InstAlias<"vmsgeu.vx $vd, $va, $rs1, $vm",
+                (PseudoVMSGEU_VX_M VRNoV0:$vd, VRegOp:$va, GPR:$rs1,
+                                   VMaskOp:$vm), 0>;
+def : InstAlias<"vmsge.vx $vd, $va, $rs1, $vm",
+                (PseudoVMSGE_VX_M VRNoV0:$vd, VRegOp:$va, GPR:$rs1,
+                                  VMaskOp:$vm), 0>;
+
 // Vector Integer Min/Max Instructions
 defm VMINU_V : VALU_IV_V_X<"vminu", 0b000100>;
 defm VMIN_V : VALU_IV_V_X<"vmin", 0b000101>;
 defm VMAXU_V : VALU_IV_V_X<"vmaxu", 0b000110>;
 defm VMAX_V : VALU_IV_V_X<"vmax", 0b000111>;
 
 // Vector Single-Width Integer Multiply Instructions
 defm VMUL_V : VALU_MV_V_X<"vmul", 0b100101>;

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 
 class RegisterTypes<list<ValueType> reg_types> {
   list<ValueType> types = reg_types;
 }
 
 // The order of registers represents the preferred allocation sequence,
 // meaning caller-save regs are listed before callee-save.
 def VR : RegisterClass<"RISCV", [nxv8i8, nxv4i16, nxv2i32, nxv1i64],
-                         64, (add
     (sequence "V%u", 25, 31),
     (sequence "V%u", 8, 24),
     (sequence "V%u", 0, 7)
   )> {
   let Size = 64;
 }
 
+def VRNoV0 : RegisterClass<"RISCV", [nxv8i8, nxv4i16, nxv2i32, nxv1i64],
+                           64, (add
+    (sequence "V%u", 25, 31),
+    (sequence "V%u", 8, 24),
+    (sequence "V%u", 1, 7)
+  )> {
+  let Size = 64;
+}
+
 def VRM2 : RegisterClass<"RISCV", [nxv16i8, nxv8i16, nxv4i32, nxv2i64], 64,
                          (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2,
                               V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2)> {
   let Size = 128;
 }
 
 def VRM4 : RegisterClass<"RISCV", [nxv32i8, nxv16i16, nxv8i32, nxv4i64], 64,
                          (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4)> {

llvm/test/MC/RISCV/rvv/compare.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d --mattr=+experimental-v - \
 # RUN:        | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 

 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 b4 47 7c <unknown>
 
 vmsge.vi v8, v4, 16
 # CHECK-INST: vmsgt.vi v8, v4, 15
 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 b4 47 7e <unknown>
+
+vmsgeu.vx v8, v4, a0
+# CHECK-INST: vmsltu.vx v8, v4, a0
+# CHECK-INST: vmnot.m v8, v8
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6a,0x57,0x24,0x84,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 6a <unknown>
+# CHECK-UNKNOWN: 57 24 84 76 <unknown>
+
+vmsge.vx v0, v4, a0
+# CHECK-INST: vmslt.vx v0, v4, a0
+# CHECK-INST: vmnot.m v0, v0
+# CHECK-ENCODING: [0x57,0x40,0x45,0x6e,0x57,0x20,0x00,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 40 45 6e <unknown>
+# CHECK-UNKNOWN: 57 20 00 76 <unknown>
+
+vmsge.vx v8, v4, a0
+# CHECK-INST: vmslt.vx v8, v4, a0
+# CHECK-INST: vmnot.m v8, v8
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6e,0x57,0x24,0x84,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 6e <unknown>
+# CHECK-UNKNOWN: 57 24 84 76 <unknown>
+
+vmsgeu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsltu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmxor.mm v8, v8, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x68,0x57,0x24,0x80,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 68 <unknown>
+# CHECK-UNKNOWN: 57 24 80 6e <unknown>
+
+vmsge.vx v8, v4, a0, v0.t
+# CHECK-INST: vmslt.vx v8, v4, a0, v0.t
+# CHECK-INST: vmxor.mm v8, v8, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6c,0x57,0x24,0x80,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 6c <unknown>
+# CHECK-UNKNOWN: 57 24 80 6e <unknown>
+
+vmsgeu.vx v0, v4, a0, v0.t, v2
+# CHECK-INST: vmsltu.vx v2, v4, a0, v0.t
+# CHECK-INST: vmandnot.mm v0, v0, v2
+# CHECK-ENCODING: [0x57,0x41,0x45,0x68,0x57,0x20,0x01,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 41 45 68 <unknown>
+# CHECK-UNKNOWN: 57 20 01 62 <unknown>
+
+vmsge.vx v0, v4, a0, v0.t, v2
+# CHECK-INST: vmslt.vx v2, v4, a0, v0.t
+# CHECK-INST: vmandnot.mm v0, v0, v2
+# CHECK-ENCODING: [0x57,0x41,0x45,0x6c,0x57,0x20,0x01,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 41 45 6c <unknown>
+# CHECK-UNKNOWN: 57 20 01 62 <unknown>

llvm/test/MC/RISCV/rvv/invalid.s

 
 vadd.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vadd.vx v0, v2, a0, v0.t
 
 vadd.vi v0, v2, 1, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vadd.vi v0, v2, 1, v0.t
+
+vmsge.vx v0, v4, a0, v0.t
+# CHECK-ERROR: too few operands for instruction
+# CHECK-ERROR-LABEL: vmsge.vx v0, v4, a0, v0.t
+
+vmsge.vx v8, v4, a0, v0.t, v2
+# CHECK-ERROR: invalid operand for instruction
+# CHECK-ERROR-LABEL: vmsge.vx v8, v4, a0, v0.t, v2