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Differential D84518

[AMDGPU] Propagate fast math flags in frem lowering
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Authored by foad on Jul 24 2020, 5:02 AM.

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Reviewers
arsenm
Petar.Avramovic
Commits
rG8cbf4a17ac57: [AMDGPU] Propagate fast math flags in frem lowering

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Event Timeline

foad created this revision.Jul 24 2020, 5:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 24 2020, 5:02 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 8 others. · View Herald Transcript
Harbormaster failed remote builds in B65540: Diff 280412!Jul 24 2020, 5:03 AM
foad added a parent revision: D84517: [AMDGPU] Lower frem f16.Jul 24 2020, 5:03 AM
foad updated this revision to Diff 280533.Jul 24 2020, 11:47 AM

Rebase.

Harbormaster completed remote builds in B65610: Diff 280533.Jul 24 2020, 12:43 PM
arsenm accepted this revision.Jul 29 2020, 5:03 PM
This revision is now accepted and ready to land.Jul 29 2020, 5:03 PM
Closed by commit rG8cbf4a17ac57: [AMDGPU] Propagate fast math flags in frem lowering (authored by foad). · Explain WhyAug 5 2020, 1:10 AM
This revision was automatically updated to reflect the committed changes.
foad mentioned this in rG1bb07e1b91c1: [AMDGPU] Precommit tests for D84518 Propagate fast math flags in frem lowering.
foad added a commit: rG8cbf4a17ac57: [AMDGPU] Propagate fast math flags in frem lowering.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
11 lines
test/
CodeGen/
AMDGPU/
308 lines

Diff 280412

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 2,078 Lines • ▼ Show 20 LinesSDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
}; };
return DAG.getMergeValues(Res, DL); return DAG.getMergeValues(Res, DL);
} }
// (frem x, y) -> (fma (fneg (ftrunc (fdiv x, y))), y, x) // (frem x, y) -> (fma (fneg (ftrunc (fdiv x, y))), y, x)
SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const { SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
SDLoc SL(Op); SDLoc SL(Op);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
auto Flags = Op->getFlags();
SDValue X = Op.getOperand(0); SDValue X = Op.getOperand(0);
SDValue Y = Op.getOperand(1); SDValue Y = Op.getOperand(1);
// TODO: Should this propagate fast-math-flags? SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags);
SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags);
SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y); SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Floor, Flags);
SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div); return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X, Flags);
SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Floor);
return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X);
} }
SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const { SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
SDLoc SL(Op); SDLoc SL(Op);
SDValue Src = Op.getOperand(0); SDValue Src = Op.getOperand(0);
// result = trunc(src) // result = trunc(src)
// if (src > 0.0 && src != result) // if (src > 0.0 && src != result)
▲ Show 20 Lines • Show All 2,637 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/frem.ll

Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
%gep2 = getelementptr half, half addrspace(1)* %in2, i32 4 %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
%r0 = load half, half addrspace(1)* %in1, align 4 %r0 = load half, half addrspace(1)* %in1, align 4
%r1 = load half, half addrspace(1)* %gep2, align 4 %r1 = load half, half addrspace(1)* %gep2, align 4
%r2 = frem half %r0, %r1 %r2 = frem half %r0, %r1
store half %r2, half addrspace(1)* %out, align 4 store half %r2, half addrspace(1)* %out, align 4
ret void ret void
} }
define amdgpu_kernel void @fast_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
; SI-LABEL: fast_frem_f16:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:8
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_rcp_f32_e32 v2, v1
; SI-NEXT: v_mul_f32_e32 v2, v0, v2
; SI-NEXT: v_trunc_f32_e32 v2, v2
; SI-NEXT: v_fma_f32 v0, -v2, v1, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; CI-LABEL: fast_frem_f16:
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; CI-NEXT: s_mov_b32 s11, 0xf000
; CI-NEXT: s_mov_b32 s10, -1
; CI-NEXT: s_mov_b32 s2, s10
; CI-NEXT: s_mov_b32 s3, s11
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:8
; CI-NEXT: s_mov_b32 s8, s4
; CI-NEXT: s_mov_b32 s9, s5
; CI-NEXT: s_mov_b32 s4, s6
; CI-NEXT: s_mov_b32 s5, s7
; CI-NEXT: s_mov_b32 s6, s10
; CI-NEXT: s_mov_b32 s7, s11
; CI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_rcp_f32_e32 v2, v1
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_mul_f32_e32 v2, v0, v2
; CI-NEXT: v_trunc_f32_e32 v2, v2
; CI-NEXT: v_fma_f32 v0, -v2, v1, v0
; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: buffer_store_short v0, off, s[8:11], 0
; CI-NEXT: s_endpgm
;
; VI-LABEL: fast_frem_f16:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s4
; VI-NEXT: s_mov_b32 s9, s5
; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:8
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_rcp_f16_e32 v2, v1
; VI-NEXT: v_mul_f16_e32 v2, v0, v2
; VI-NEXT: v_trunc_f16_e32 v2, v2
; VI-NEXT: v_fma_f16 v0, -v2, v1, v0
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
; VI-NEXT: s_endpgm
half addrspace(1)* %in2) #0 {
%gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
%r0 = load half, half addrspace(1)* %in1, align 4
%r1 = load half, half addrspace(1)* %gep2, align 4
%r2 = frem fast half %r0, %r1
store half %r2, half addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @unsafe_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1, define amdgpu_kernel void @unsafe_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
; SI-LABEL: unsafe_frem_f16: ; SI-LABEL: unsafe_frem_f16:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
%gep2 = getelementptr float, float addrspace(1)* %in2, i32 4 %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
%r0 = load float, float addrspace(1)* %in1, align 4 %r0 = load float, float addrspace(1)* %in1, align 4
%r1 = load float, float addrspace(1)* %gep2, align 4 %r1 = load float, float addrspace(1)* %gep2, align 4
%r2 = frem float %r0, %r1 %r2 = frem float %r0, %r1
store float %r2, float addrspace(1)* %out, align 4 store float %r2, float addrspace(1)* %out, align 4
ret void ret void
} }
define amdgpu_kernel void @fast_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
; SI-LABEL: fast_frem_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
; SI-NEXT: buffer_load_dword v1, off, s[8:11], 0 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_rcp_f32_e32 v2, v1
; SI-NEXT: v_mul_f32_e32 v2, v0, v2
; SI-NEXT: v_trunc_f32_e32 v2, v2
; SI-NEXT: v_fma_f32 v0, -v2, v1, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; CI-LABEL: fast_frem_f32:
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; CI-NEXT: s_mov_b32 s11, 0xf000
; CI-NEXT: s_mov_b32 s10, -1
; CI-NEXT: s_mov_b32 s2, s10
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b32 s8, s4
; CI-NEXT: s_mov_b32 s9, s5
; CI-NEXT: s_mov_b32 s4, s6
; CI-NEXT: s_mov_b32 s5, s7
; CI-NEXT: s_mov_b32 s6, s10
; CI-NEXT: s_mov_b32 s7, s11
; CI-NEXT: s_mov_b32 s3, s11
; CI-NEXT: buffer_load_dword v0, off, s[4:7], 0
; CI-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:16
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_rcp_f32_e32 v2, v1
; CI-NEXT: v_mul_f32_e32 v2, v0, v2
; CI-NEXT: v_trunc_f32_e32 v2, v2
; CI-NEXT: v_fma_f32 v0, -v2, v1, v0
; CI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; CI-NEXT: s_endpgm
;
; VI-LABEL: fast_frem_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s4
; VI-NEXT: s_mov_b32 s9, s5
; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0
; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_rcp_f32_e32 v2, v1
; VI-NEXT: v_mul_f32_e32 v2, v0, v2
; VI-NEXT: v_trunc_f32_e32 v2, v2
; VI-NEXT: v_fma_f32 v0, -v2, v1, v0
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: s_endpgm
float addrspace(1)* %in2) #0 {
%gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
%r0 = load float, float addrspace(1)* %in1, align 4
%r1 = load float, float addrspace(1)* %gep2, align 4
%r2 = frem fast float %r0, %r1
store float %r2, float addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1, define amdgpu_kernel void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
; SI-LABEL: unsafe_frem_f32: ; SI-LABEL: unsafe_frem_f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 200 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
double addrspace(1)* %in2) #0 { double addrspace(1)* %in2) #0 {
%r0 = load double, double addrspace(1)* %in1, align 8 %r0 = load double, double addrspace(1)* %in1, align 8
%r1 = load double, double addrspace(1)* %in2, align 8 %r1 = load double, double addrspace(1)* %in2, align 8
%r2 = frem double %r0, %r1 %r2 = frem double %r0, %r1
store double %r2, double addrspace(1)* %out, align 8 store double %r2, double addrspace(1)* %out, align 8
ret void ret void
} }
define amdgpu_kernel void @fast_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
; SI-LABEL: fast_frem_f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s8
; SI-NEXT: s_mov_b32 s5, s9
; SI-NEXT: s_mov_b32 s0, s10
; SI-NEXT: s_mov_b32 s1, s11
; SI-NEXT: s_mov_b32 s2, s6
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: s_mov_b32 s14, s6
; SI-NEXT: s_mov_b32 s15, s7
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[12:15], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
; SI-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; SI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; SI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; SI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT: v_div_scale_f64 v[8:9], s[0:1], v[0:1], v[2:3], v[0:1]
; SI-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7]
; SI-NEXT: v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
; SI-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5
; SI-NEXT: v_cmp_eq_u32_e64 s[0:1], v1, v9
; SI-NEXT: s_xor_b64 vcc, s[0:1], vcc
; SI-NEXT: s_nop 0
; SI-NEXT: s_nop 0
; SI-NEXT: v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
; SI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_bfe_u32 v6, v5, 20, 11
; SI-NEXT: v_add_i32_e32 v8, vcc, 0xfffffc01, v6
; SI-NEXT: s_mov_b32 s1, 0xfffff
; SI-NEXT: s_mov_b32 s0, s6
; SI-NEXT: v_lshr_b64 v[6:7], s[0:1], v8
; SI-NEXT: v_not_b32_e32 v6, v6
; SI-NEXT: v_and_b32_e32 v6, v4, v6
; SI-NEXT: v_not_b32_e32 v7, v7
; SI-NEXT: v_and_b32_e32 v7, v5, v7
; SI-NEXT: v_and_b32_e32 v9, 0x80000000, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v8
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; SI-NEXT: v_cmp_lt_i32_e64 s[0:1], 51, v8
; SI-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; SI-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[0:1]
; SI-NEXT: v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; CI-LABEL: fast_frem_f64:
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; CI-NEXT: s_mov_b32 s11, 0xf000
; CI-NEXT: s_mov_b32 s10, -1
; CI-NEXT: s_mov_b32 s2, s10
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b32 s8, s4
; CI-NEXT: s_mov_b32 s9, s5
; CI-NEXT: s_mov_b32 s4, s6
; CI-NEXT: s_mov_b32 s5, s7
; CI-NEXT: s_mov_b32 s6, s10
; CI-NEXT: s_mov_b32 s7, s11
; CI-NEXT: s_mov_b32 s3, s11
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
; CI-NEXT: buffer_load_dwordx2 v[2:3], off, s[0:3], 0
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
; CI-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; CI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; CI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; CI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; CI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; CI-NEXT: v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
; CI-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7]
; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; CI-NEXT: s_nop 1
; CI-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; CI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; CI-NEXT: v_trunc_f64_e32 v[4:5], v[4:5]
; CI-NEXT: v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; CI-NEXT: s_endpgm
;
; VI-LABEL: fast_frem_f64:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s4
; VI-NEXT: s_mov_b32 s9, s5
; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: buffer_load_dwordx2 v[2:3], off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
; VI-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; VI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; VI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; VI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; VI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; VI-NEXT: v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
; VI-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7]
; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; VI-NEXT: s_nop 1
; VI-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; VI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; VI-NEXT: v_trunc_f64_e32 v[4:5], v[4:5]
; VI-NEXT: v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; VI-NEXT: s_endpgm
double addrspace(1)* %in2) #0 {
%r0 = load double, double addrspace(1)* %in1, align 8
%r1 = load double, double addrspace(1)* %in2, align 8
%r2 = frem fast double %r0, %r1
store double %r2, double addrspace(1)* %out, align 8
ret void
}
define amdgpu_kernel void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1, define amdgpu_kernel void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
; SI-LABEL: unsafe_frem_f64: ; SI-LABEL: unsafe_frem_f64:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s15, 0xf000 ; SI-NEXT: s_mov_b32 s15, 0xf000
; SI-NEXT: s_mov_b32 s14, -1 ; SI-NEXT: s_mov_b32 s14, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
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