AMDGPU/GlobalISel: Fix assert on copy to vcc

[arsenm]

Summary

This was trying to constrain a physical register. By the verifier's
understanding, it's impossible to have a 1-bit copy to vcc/vcc_lo so
don't try to handle physregs.

[arsenm]

ping

[arsenm]

ping

[nhaehnle]

LGTM

[arsenm]

53162567090251e98b14f979ee2f69669cec3ddd

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 void AMDGPUInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits &KB,
                                         CodeGenCoverage &CoverageInfo) {
   MRI = &MF.getRegInfo();
   InstructionSelector::setupMF(MF, KB, CoverageInfo);
 }
 
 bool AMDGPUInstructionSelector::isVCC(Register Reg,
                                       const MachineRegisterInfo &MRI) const {
-  if (Register::isPhysicalRegister(Reg))
-    return Reg == TRI.getVCC();
+  // The verifier is oblivious to s1 being a valid value for wavesize registers.
+  if (Reg.isPhysical())
+    return false;
 
   auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
   const TargetRegisterClass *RC =
       RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
   if (RC) {
     const LLT Ty = MRI.getType(Reg);
     return RC->hasSuperClassEq(TRI.getBoolRC()) &&
            Ty.isValid() && Ty.getSizeInBits() == 1;

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

bb.0:
     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY]]
     ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:vcc(s1) = G_TRUNC %0
     %2:vcc(s1) = COPY %1
     S_ENDPGM 0, implicit %2
 
 ...
+
+---
+
+name:            copy_s64_to_vcc
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; WAVE64-LABEL: name: copy_s64_to_vcc
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+    ; WAVE64: $vcc = COPY [[COPY]]
+    ; WAVE64: S_ENDPGM 0, implicit $vcc
+    ; WAVE32-LABEL: name: copy_s64_to_vcc
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+    ; WAVE32: $vcc = COPY [[COPY]]
+    ; WAVE32: S_ENDPGM 0, implicit $vcc_lo
+    %0:sgpr(s64) = COPY $sgpr0_sgpr1
+    $vcc = COPY %0
+    S_ENDPGM 0, implicit $vcc
+
+...
+
+---
+
+name:            copy_s32_to_vcc_lo
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; WAVE64-LABEL: name: copy_s32_to_vcc_lo
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE64: $vcc_lo = COPY [[COPY]]
+    ; WAVE64: S_ENDPGM 0, implicit $vcc
+    ; WAVE32-LABEL: name: copy_s32_to_vcc_lo
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE32: $vcc_lo = COPY [[COPY]]
+    ; WAVE32: S_ENDPGM 0, implicit $vcc_lo
+    %0:sgpr(s32) = COPY $sgpr0
+    $vcc_lo = COPY %0
+    S_ENDPGM 0, implicit $vcc
+
+...