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Differential D84163

AMDGPU/GlobalISel: Fix trying to widen <3 x s1> boolean ops
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Authored by arsenm on Jul 20 2020, 5:34 AM.

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Reviewers
kerbowa
nhaehnle
foad
Petar.Avramovic
mbrkusanin

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arsenm created this revision.Jul 20 2020, 5:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 20 2020, 5:34 AM
Herald added subscribers: hiraditya, t-tye, tpr and 6 others. · View Herald Transcript
foad added inline comments.Jul 20 2020, 5:46 AM
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
66

Perhaps add a comment that "small" doesn't include s1 here?

76

getSizeInBits will be (an odd number) * (a number less than 32), so I don't think it can ever be a multiple of 32. But I suppose it's harmless.

arsenm updated this revision to Diff 279215.Jul 20 2020, 6:04 AM

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arsenm added a comment.Jul 27 2020, 11:23 AM

ping

arsenm added a comment.Aug 4 2020, 12:28 PM

ping

kerbowa accepted this revision.Aug 5 2020, 8:06 PM

LGTM

This revision is now accepted and ready to land.Aug 5 2020, 8:06 PM
arsenm closed this revision.Aug 6 2020, 7:14 AM

c015cbc68b80e02b651988855b61b588f5069ef6

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
13 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
77 lines
49 lines
67 lines
12 lines
77 lines
145 lines
77 lines

Diff 279215

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
// Round the number of bits to the next power of two bits // Round the number of bits to the next power of two bits
static LLT getPow2ScalarType(LLT Ty) { static LLT getPow2ScalarType(LLT Ty) {
unsigned Bits = Ty.getSizeInBits(); unsigned Bits = Ty.getSizeInBits();
unsigned Pow2Bits = 1 << Log2_32_Ceil(Bits); unsigned Pow2Bits = 1 << Log2_32_Ceil(Bits);
return LLT::scalar(Pow2Bits); return LLT::scalar(Pow2Bits);
} }
/// \returs true if this is an odd sized vector which should widen by adding an
/// additional element. This is mostly to handle <3 x s16> -> <4 x s16>. This
/// excludes s1 vectors, which should always be scalarized.
static LegalityPredicate isSmallOddVector(unsigned TypeIdx) { static LegalityPredicate isSmallOddVector(unsigned TypeIdx) {
foadUnsubmitted
Not Done
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Perhaps add a comment that "small" doesn't include s1 here?

foad: Perhaps add a comment that "small" doesn't include s1 here?
return [=](const LegalityQuery &Query) { return [=](const LegalityQuery &Query) {
const LLT Ty = Query.Types[TypeIdx]; const LLT Ty = Query.Types[TypeIdx];
return Ty.isVector() && if (!Ty.isVector())
Ty.getNumElements() % 2 != 0 && return false;
Ty.getElementType().getSizeInBits() < 32 &&
const LLT EltTy = Ty.getElementType();
const unsigned EltSize = EltTy.getSizeInBits();
return Ty.getNumElements() % 2 != 0 &&
EltSize > 1 && EltSize < 32 &&
Ty.getSizeInBits() % 32 != 0; Ty.getSizeInBits() % 32 != 0;
foadUnsubmitted
Not Done
ReplyInline Actions

getSizeInBits will be (an odd number) * (a number less than 32), so I don't think it can ever be a multiple of 32. But I suppose it's harmless.

foad: getSizeInBits will be (an odd number) * (a number less than 32), so I don't think it can ever…
}; };
} }
static LegalityPredicate isWideVec16(unsigned TypeIdx) { static LegalityPredicate isWideVec16(unsigned TypeIdx) {
return [=](const LegalityQuery &Query) { return [=](const LegalityQuery &Query) {
const LLT Ty = Query.Types[TypeIdx]; const LLT Ty = Query.Types[TypeIdx];
const LLT EltTy = Ty.getScalarType(); const LLT EltTy = Ty.getScalarType();
return EltTy.getSizeInBits() == 16 && Ty.getNumElements() > 2; return EltTy.getSizeInBits() == 16 && Ty.getNumElements() > 2;
▲ Show 20 Lines • Show All 4,270 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir

Show All 33 Lines bb.0:
%2:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(ne), %0, %2 %3:_(s1) = G_ICMP intpred(ne), %0, %2
%4:_(s1) = G_ICMP intpred(ne), %1, %2 %4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(s32) = G_AND %0, %1 %5:_(s32) = G_AND %0, %1
S_NOP 0, implicit %5 S_NOP 0, implicit %5
... ...
--- ---
name: test_and_v2s1
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: test_and_v2s1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV4]](s32), [[UV6]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV5]](s32), [[UV7]]
; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP]], [[ICMP2]]
; CHECK: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s1)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = COPY $vgpr4_vgpr5
%3:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%4:_(<2 x s1>) = G_ICMP intpred(ne), %0, %2
%5:_(<2 x s1>) = G_AND %3, %4
%6:_(<2 x s32>) = G_ANYEXT %5
$vgpr0_vgpr1 = COPY %6
...
---
name: test_and_v3s1
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_and_v3s1
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV6]](s32), [[UV9]]
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV7]](s32), [[UV10]]
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV8]](s32), [[UV11]]
; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP]], [[ICMP3]]
; CHECK: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP4]]
; CHECK: [[AND2:%[0-9]+]]:_(s1) = G_AND [[ICMP2]], [[ICMP5]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND2]](s1)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
%3:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %2
%5:_(<3 x s1>) = G_AND %3, %4
%6:_(<3 x s32>) = G_ANYEXT %5
$vgpr0_vgpr1_vgpr2 = COPY %6
...
---
name: test_and_s64 name: test_and_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_and_s64 ; CHECK-LABEL: name: test_and_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
▲ Show 20 Lines • Show All 626 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir

Show First 20 Lines • Show All 550 Lines • ▼ Show 20 Lines bb.0:
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: extract_s8_v5s1_offset4 name: extract_s8_v5s1_offset4
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_s8_v5s1_offset4 ; CHECK-LABEL: name: extract_s8_v5s1_offset4
; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<5 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s1>) = G_TRUNC [[DEF]](<6 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<5 x s32>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s1>) = G_EXTRACT [[TRUNC]](<6 x s1>), 0 ; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1), [[UV2:%[0-9]+]]:_(s1), [[UV3:%[0-9]+]]:_(s1), [[UV4:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[EXTRACT]](<5 x s1>) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s1) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[UV3]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s1) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV4]](s32), [[DEF1]](s32)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s1) ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s1) ; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s1) ; CHECK: [[TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR2]](<2 x s32>)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ANYEXT]](s16) ; CHECK: [[DEF2:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ANYEXT1]](s16) ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<2 x s16>), [[TRUNC1]](<2 x s16>), [[TRUNC2]](<2 x s16>), [[DEF2]](<2 x s16>), [[DEF2]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<10 x s16>), 0
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) ; CHECK: [[DEF3:%[0-9]+]]:_(<6 x s16>) = G_IMPLICIT_DEF
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] ; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[DEF3]], [[EXTRACT]](<5 x s16>), 0
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[INSERT]](<6 x s16>), 64
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ANYEXT2]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT1]](s16)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ANYEXT3]](s16) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[ANYEXT4]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL2]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[DEF1]], [[EXTRACT1]](<5 x s16>), 0
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s16) = G_EXTRACT [[INSERT]](<6 x s16>), 64
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT2]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT5]](s32)
%0:_(<5 x s1>) = G_IMPLICIT_DEF %0:_(<5 x s1>) = G_IMPLICIT_DEF
%1:_(s1) = G_EXTRACT %0, 4 %1:_(s1) = G_EXTRACT %0, 4
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: extract_v2s16_v4s16_offset32 name: extract_v2s16_v4s16_offset32
▲ Show 20 Lines • Show All 539 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir

Show First 20 Lines • Show All 459 Lines • ▼ Show 20 Lines bb.0:
%1:_(<64 x s32>) = G_FREEZE %0 %1:_(<64 x s32>) = G_FREEZE %0
S_NOP 0, implicit %1 S_NOP 0, implicit %1
... ...
--- ---
name: test_freeze_v2s1 name: test_freeze_v2s1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_freeze_v2s1 ; CHECK-LABEL: name: test_freeze_v2s1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>) ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE [[COPY]] ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[FREEZE]](<2 x s32>) ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY1]](<2 x s32>) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]]
%0:_(<2 x s1>) = G_IMPLICIT_DEF ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
%1:_(<2 x s1>) = G_FREEZE %0 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
%2:_(<2 x s32>) = G_ANYEXT %1 ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
$vgpr0_vgpr1 = COPY %2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE [[BUILD_VECTOR]]
; CHECK: [[COPY4:%[0-9]+]]:_(<2 x s32>) = COPY [[FREEZE]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%3:_(<2 x s1>) = G_FREEZE %2
%4:_(<2 x s32>) = G_ANYEXT %3
$vgpr0_vgpr1 = COPY %4
... ...
--- ---
name: test_freeze_v3s1 name: test_freeze_v3s1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; CHECK-LABEL: name: test_freeze_v3s1 ; CHECK-LABEL: name: test_freeze_v3s1
; CHECK: [[DEF:%[0-9]+]]:_(<3 x s1>) = G_IMPLICIT_DEF ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s1>) = G_IMPLICIT_DEF ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s1>) = G_INSERT [[DEF1]], [[DEF]](<3 x s1>), 0 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[INSERT]](<4 x s1>) ; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[FREEZE:%[0-9]+]]:_(<4 x s32>) = G_FREEZE [[ANYEXT]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[FREEZE]](<4 x s32>) ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s1>) = G_EXTRACT [[TRUNC]](<4 x s1>), 0 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(<3 x s32>) = G_ANYEXT [[EXTRACT]](<3 x s1>) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[ANYEXT1]](<3 x s32>) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
%0:_(<3 x s1>) = G_IMPLICIT_DEF ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
%1:_(<3 x s1>) = G_FREEZE %0 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
%2:_(<3 x s32>) = G_ANYEXT %1 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
$vgpr0_vgpr1_vgpr2 = COPY %2 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(<3 x s32>) = G_FREEZE [[BUILD_VECTOR]]
; CHECK: [[COPY5:%[0-9]+]]:_(<3 x s32>) = COPY [[FREEZE]](<3 x s32>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY5]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%3:_(<3 x s1>) = G_FREEZE %2
%4:_(<3 x s32>) = G_ANYEXT %3
$vgpr0_vgpr1_vgpr2 = COPY %4
... ...
--- ---
name: test_freeze_v2s8 name: test_freeze_v2s8
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_freeze_v2s8 ; CHECK-LABEL: name: test_freeze_v2s8
▲ Show 20 Lines • Show All 361 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir

Show First 20 Lines • Show All 369 Lines • ▼ Show 20 Lines
... ...
--- ---
name: test_implicit_def_v3s1 name: test_implicit_def_v3s1
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_implicit_def_v3s1 ; CHECK-LABEL: name: test_implicit_def_v3s1
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[DEF]](<4 x s32>) ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF]](<3 x s32>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s1>) = G_EXTRACT [[TRUNC]](<4 x s1>), 0 ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1), [[UV2:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s1>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s1)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s1>) = G_IMPLICIT_DEF %0:_(<3 x s1>) = G_IMPLICIT_DEF
%1:_(<3 x s32>) = G_ANYEXT %0 %1:_(<3 x s32>) = G_ANYEXT %0
$vgpr0_vgpr1_vgpr2 = COPY %1 $vgpr0_vgpr1_vgpr2 = COPY %1
... ...
--- ---
name: test_implicit_def_v2s8 name: test_implicit_def_v2s8
body: | body: |
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir

Show All 33 Lines bb.0:
%2:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(ne), %0, %2 %3:_(s1) = G_ICMP intpred(ne), %0, %2
%4:_(s1) = G_ICMP intpred(ne), %1, %2 %4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(s32) = G_OR %0, %1 %5:_(s32) = G_OR %0, %1
S_NOP 0, implicit %5 S_NOP 0, implicit %5
... ...
--- ---
name: test_or_v2s1
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: test_or_v2s1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV4]](s32), [[UV6]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV5]](s32), [[UV7]]
; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP2]]
; CHECK: [[OR1:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s1)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = COPY $vgpr4_vgpr5
%3:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%4:_(<2 x s1>) = G_ICMP intpred(ne), %0, %2
%5:_(<2 x s1>) = G_OR %3, %4
%6:_(<2 x s32>) = G_ANYEXT %5
$vgpr0_vgpr1 = COPY %6
...
---
name: test_or_v3s1
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_or_v3s1
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV6]](s32), [[UV9]]
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV7]](s32), [[UV10]]
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV8]](s32), [[UV11]]
; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP3]]
; CHECK: [[OR1:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP4]]
; CHECK: [[OR2:%[0-9]+]]:_(s1) = G_OR [[ICMP2]], [[ICMP5]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s1)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
%3:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %2
%5:_(<3 x s1>) = G_OR %3, %4
%6:_(<3 x s32>) = G_ANYEXT %5
$vgpr0_vgpr1_vgpr2 = COPY %6
...
---
name: test_or_s64 name: test_or_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_or_s64 ; CHECK-LABEL: name: test_or_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
▲ Show 20 Lines • Show All 464 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

Show First 20 Lines • Show All 1,296 Lines • ▼ Show 20 Lines bb.0:
%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1 %4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%5:_(<3 x s16>) = G_TRUNC %2 %5:_(<3 x s16>) = G_TRUNC %2
%6:_(<3 x s16>) = G_TRUNC %3 %6:_(<3 x s16>) = G_TRUNC %3
%7:_(<3 x s16>) = G_SELECT %4, %5, %6 %7:_(<3 x s16>) = G_SELECT %4, %5, %6
%8:_(<3 x s32>) = G_ANYEXT %7 %8:_(<3 x s32>) = G_ANYEXT %7
$vgpr0_vgpr1_vgpr2 = COPY %8 $vgpr0_vgpr1_vgpr2 = COPY %8
... ...
---
name: test_select_s1
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_select_s1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[C]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP2]](s1)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
%3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %0, %3
%5:_(s1) = G_ICMP intpred(ne), %1, %3
%6:_(s1) = G_ICMP intpred(ne), %2, %3
%7:_(s1) = G_SELECT %4, %5, %6
%8:_(s32) = G_ZEXT %7
$vgpr0 = COPY %8
...
---
name: test_select_v2s1
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
; CHECK-LABEL: name: test_select_v2s1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr6_vgpr7
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV4]](s32), [[UV6]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV5]](s32), [[UV7]]
; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV8]](s32), [[UV10]]
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV9]](s32), [[UV11]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP2]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP4]](s1)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP3]](s1)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP5]](s1)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = COPY $vgpr4_vgpr5
%3:_(<2 x s32>) = COPY $vgpr6_vgpr7
%4:_(<2 x s1>) = G_ICMP intpred(ne), %0, %3
%5:_(<2 x s1>) = G_ICMP intpred(ne), %1, %3
%6:_(<2 x s1>) = G_ICMP intpred(ne), %2, %3
%7:_(<2 x s1>) = G_SELECT %4, %5, %6
%8:_(<2 x s32>) = G_ZEXT %7
$vgpr0_vgpr1 = COPY %8
...
---
name: test_select_v3s1
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8, $vgpr9_vgpr10_vgpr11
; CHECK-LABEL: name: test_select_v3s1
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
; CHECK: [[COPY3:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<3 x s32>)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV6]](s32), [[UV9]]
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV7]](s32), [[UV10]]
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV8]](s32), [[UV11]]
; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<3 x s32>)
; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV12]](s32), [[UV15]]
; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV13]](s32), [[UV16]]
; CHECK: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV14]](s32), [[UV17]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP3]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP6]](s1)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP4]](s1)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP7]](s1)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP5]](s1)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP8]](s1)
; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP2]](s1), [[ANYEXT4]], [[ANYEXT5]]
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT8]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
%3:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %3
%5:_(<3 x s1>) = G_ICMP intpred(ne), %1, %3
%6:_(<3 x s1>) = G_ICMP intpred(ne), %2, %3
%7:_(<3 x s1>) = G_SELECT %4, %5, %6
%8:_(<3 x s32>) = G_ZEXT %7
$vgpr0_vgpr1_vgpr2 = COPY %8
...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir

Show All 33 Lines bb.0:
%2:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(ne), %0, %2 %3:_(s1) = G_ICMP intpred(ne), %0, %2
%4:_(s1) = G_ICMP intpred(ne), %1, %2 %4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(s32) = G_XOR %0, %1 %5:_(s32) = G_XOR %0, %1
S_NOP 0, implicit %5 S_NOP 0, implicit %5
... ...
--- ---
name: test_xor_v2s1
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: test_xor_v2s1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV4]](s32), [[UV6]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV5]](s32), [[UV7]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP2]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = COPY $vgpr4_vgpr5
%3:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%4:_(<2 x s1>) = G_ICMP intpred(ne), %0, %2
%5:_(<2 x s1>) = G_XOR %3, %4
%6:_(<2 x s32>) = G_ANYEXT %5
$vgpr0_vgpr1 = COPY %6
...
---
name: test_xor_v3s1
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_xor_v3s1
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV6]](s32), [[UV9]]
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV7]](s32), [[UV10]]
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV8]](s32), [[UV11]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP3]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP4]]
; CHECK: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP5]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR2]](s1)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
%3:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %2
%5:_(<3 x s1>) = G_XOR %3, %4
%6:_(<3 x s32>) = G_ANYEXT %5
$vgpr0_vgpr1_vgpr2 = COPY %6
...
---
name: test_xor_s64 name: test_xor_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_xor_s64 ; CHECK-LABEL: name: test_xor_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
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