GlobalISel: Define InvalidRegBankID enum value

[arsenm]

Make enum unsigned to match getID

[arsenm]

ping

[paquette]

llvm/utils/TableGen/RegisterBankEmitter.cpp

136

Why 0 when it was -1 before?

[arsenm]

llvm/utils/TableGen/RegisterBankEmitter.cpp

136

This is still -1, just the unsigned interpretation. All of the code treats this as unsigned, so to avoid fixing up everywhere that uses these to use int, the enum needs to be switched to unsigned.

[arsenm]

ping

[paquette]

LGTM

[arsenm]

34040a4f61fecaa8e901ca2e5e587df13d7097ac

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

 }
 
 
 static unsigned regBankUnion(unsigned RB0, unsigned RB1) {
   return (RB0 == AMDGPU::SGPRRegBankID && RB1 == AMDGPU::SGPRRegBankID) ?
     AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
 }
 
-static int regBankBoolUnion(int RB0, int RB1) {
-  if (RB0 == -1)
+static unsigned regBankBoolUnion(unsigned RB0, unsigned RB1) {
+  if (RB0 == AMDGPU::InvalidRegBankID)
     return RB1;
-  if (RB1 == -1)
+  if (RB1 == AMDGPU::InvalidRegBankID)
     return RB0;
 
   // vcc, vcc -> vcc
   // vcc, sgpr -> vcc
   // vcc, vgpr -> vcc
   if (RB0 == AMDGPU::VCCRegBankID || RB1 == AMDGPU::VCCRegBankID)
     return AMDGPU::VCCRegBankID;
 
return getInstructionMapping(
         /*OperandsMapping*/ getOperandsMapping({&ValMap}), 1);
   }
 
   // The default handling is broken and doesn't handle illegal SGPR->VGPR copies
   // properly.
   //
   // TODO: There are additional exec masking dependencies to analyze.
   if (MI.getOpcode() == TargetOpcode::G_PHI) {
-    // TODO: Generate proper invalid bank enum.
-    int ResultBank = -1;
+    unsigned ResultBank = AMDGPU::InvalidRegBankID;
     Register DstReg = MI.getOperand(0).getReg();
 
     // Sometimes the result may have already been assigned a bank.
     if (const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI))
       ResultBank = DstBank->getID();
 
     for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
       Register Reg = MI.getOperand(I).getReg();
       const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
 
       // FIXME: Assuming VGPR for any undetermined inputs.
       if (!Bank || Bank->getID() == AMDGPU::VGPRRegBankID) {
         ResultBank = AMDGPU::VGPRRegBankID;
         break;
       }
 
       // FIXME: Need to promote SGPR case to s32
       unsigned OpBank = Bank->getID();
       ResultBank = regBankBoolUnion(ResultBank, OpBank);
     }
 
-    assert(ResultBank != -1);
+    assert(ResultBank != AMDGPU::InvalidRegBankID);
 
     unsigned Size = MRI.getType(DstReg).getSizeInBits();
 
     const ValueMapping &ValMap =
         getValueMapping(0, Size, getRegBank(ResultBank));
     return getInstructionMapping(
         1, /*Cost*/ 1,
         /*OperandsMapping*/ getOperandsMapping({&ValMap}), 1);
AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case AMDGPU::G_AND:
   case AMDGPU::G_OR:
   case AMDGPU::G_XOR: {
     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
     if (Size == 1) {
       const RegisterBank *DstBank
         = getRegBank(MI.getOperand(0).getReg(), MRI, *TRI);
 
-      unsigned TargetBankID = -1;
-      unsigned BankLHS = -1;
-      unsigned BankRHS = -1;
+      unsigned TargetBankID = AMDGPU::InvalidRegBankID;
+      unsigned BankLHS = AMDGPU::InvalidRegBankID;
+      unsigned BankRHS = AMDGPU::InvalidRegBankID;
       if (DstBank) {
         TargetBankID = DstBank->getID();
         if (DstBank == &AMDGPU::VCCRegBank) {
           TargetBankID = AMDGPU::VCCRegBankID;
           BankLHS = AMDGPU::VCCRegBankID;
           BankRHS = AMDGPU::VCCRegBankID;
         } else {
           BankLHS = getRegBankID(MI.getOperand(1).getReg(), MRI,

llvm/utils/TableGen/RegisterBankEmitter.cpp

 /// Emit code to declare the ID enumeration and external global instance
 /// variables.
 void RegisterBankEmitter::emitHeader(raw_ostream &OS,
                                      const StringRef TargetName,
                                      const std::vector<RegisterBank> &Banks) {
   // <Target>RegisterBankInfo.h
   OS << "namespace llvm {\n"
      << "namespace " << TargetName << " {\n"
-     << "enum {\n";
+     << "enum : unsigned {\n";
+
+  OS << "InvalidRegBankID = ~0u,\n";
+  unsigned ID = 0;
   for (const auto &Bank : Banks)
-    OS << "  " << Bank.getEnumeratorName() << ",\n";
+    OS << "  " << Bank.getEnumeratorName() << " = " << ID++ << ",\n";
   OS << "  NumRegisterBanks,\n"
      << "};\n"
      << "} // end namespace " << TargetName << "\n"
      << "} // end namespace llvm\n";
 }
 
 /// Emit declarations of the <Target>GenRegisterBankInfo class.
 void RegisterBankEmitter::emitBaseClassDefinition(