[Power] Set the mayRaiseFPException for FCMPUS/FCMPUD

[steven.zhang]

Summary

From ISA, fcmpu will raise the Floating-Point Invalid Operation Exception (SNaN) if either of the operands is a Signaling NaN by setting the bit VXSNAN. But the instruction description didn't set the mayRaiseFPException which might have impact on the scheduling or some backend optimization.

[qiucf]

Can we add test to show the effect? Something like

%a = call double @llvm.experimental.constrained.fadd.f64(...)
; Insert the instruction here
%b = call double @llvm.experimental.constrained.fdiv.f64(...)

I think instruction with side effect should prevent fdiv from scheduled upwards.

[qiucf]

define i32 @test(double %a, double %b) {
entry:
  %r = fcmp ogt double %a, %b
  %g = zext i1 %r to i32
  ret i32 %g
}

Print MIR:

renamable $cr0 = FCMPUD killed renamable $f1, killed renamable $f2 # Without mayRaise set
renamable $cr0 = nofpexcept FCMPUD killed renamable $f1, killed renamable $f2 # With mayRaise set

You can create a dedicated test file for fp-exception bit, so that we can re-check all fp-exception bits in instruction definitions.

[steven.zhang]

In D83937#2251316, @qiucf wrote:

define i32 @test(double %a, double %b) {
entry:
  %r = fcmp ogt double %a, %b
  %g = zext i1 %r to i32
  ret i32 %g
}

Print MIR:

renamable $cr0 = FCMPUD killed renamable $f1, killed renamable $f2 # Without mayRaise set
renamable $cr0 = nofpexcept FCMPUD killed renamable $f1, killed renamable $f2 # With mayRaise set

You can create a dedicated test file for fp-exception bit, so that we can re-check all fp-exception bits in instruction definitions.

Thanks for the comments. I will update it.

[steven.zhang]

Add test.

[qiucf]

LGTM

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 let isCompare = 1, hasSideEffects = 0 in {
   def CMPW   : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
                             "cmpw $crD, $rA, $rB", IIC_IntCompare>;
   def CMPLW  : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
                             "cmplw $crD, $rA, $rB", IIC_IntCompare>;
 }
 }
 let PPC970_Unit = 3, Predicates = [HasFPU] in {  // FPU Operations.
-let isCompare = 1, hasSideEffects = 0 in {
+let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in {
   def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
                         "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
   def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
                         "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
     def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
                           "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
     def FCMPOD : XForm_17<63, 32, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),

llvm/test/CodeGen/PowerPC/nofpexcept.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:   -stop-after=finalize-isel -verify-machineinstrs | FileCheck %s 
+
+; Verify if the mayRaiseFPException is set for FCMPD/FCMPS
+define i32 @fcmpu(double %a, double %b) {
+  ; CHECK-LABEL: name: fcmpu
+  ; CHECK: bb.0.entry:
+  ; CHECK:   liveins: $f1, $f2
+  ; CHECK:   [[COPY:%[0-9]+]]:f8rc = COPY $f2
+  ; CHECK:   [[COPY1:%[0-9]+]]:f8rc = COPY $f1
+  ; CHECK:   %2:crrc = nofpexcept FCMPUD [[COPY1]], [[COPY]]
+  ; CHECK:   [[COPY2:%[0-9]+]]:crbitrc = COPY %2.sub_gt
+  ; CHECK:   [[LI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 0
+  ; CHECK:   [[LI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 1
+  ; CHECK:   [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 [[LI8_1]], [[LI8_]], [[COPY2]]
+  ; CHECK:   $x3 = COPY [[ISEL8_]]
+  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
+entry:
+  %r = fcmp ogt double %a, %b
+  %g = zext i1 %r to i32
+  ret i32 %g
+}