[X86] Add a generic 32-bit CPU with sse2 with modern tuning flags to be used as the default for the 32-bit targets instead of pentium4

[craig.topper]

Summary

Currently our default 32-bit CPU on Linux and Windows is "pentium4" which comes with pentium4 tuning settings and almost non-existent scheduler.

This patch proposes to add a 32-bit CPU with sse2, but with more modern tuning settings to replace the default pentium4. I've chosen this way so that -march=pentium4 behavior doesn't change. Alternatively we can just change the pentium4 settings and assume no one cares about truly tuning for pentium4 these days.

This would be unnecessary if -mtune were supported, but this is a lot less effort than plumbing mtune.

[echristo]

Did you want to just change the pentium4 tuning? Otherwise naming things is hard and this feels awkward, but I don't have any better ideas :)

clang/lib/Basic/Targets/X86.cpp

case CK_C3_2:
     Builder.defineMacro("__tune_pentium2__");
     LLVM_FALLTHROUGH;
   case CK_PentiumPro:
   case CK_i686:
     defineCPUMacros(Builder, "i686");
     defineCPUMacros(Builder, "pentiumpro");
     break;
   case CK_Pentium4:
+  case CK_x86_32_sse2:
     defineCPUMacros(Builder, "pentium4");
     break;
   case CK_Yonah:
   case CK_Prescott:
   case CK_Nocona:
     defineCPUMacros(Builder, "nocona");
     break;
   case CK_Core2:
switch (CPU) {
     case CK_K6_2:
     case CK_K6_3:
     // Geode
     case CK_Geode:
       return 32;
 
     // Netburst
     case CK_Pentium4:
+    case CK_x86_32_sse2:
     case CK_Prescott:
     case CK_Nocona:
     // Atom
     case CK_Bonnell:
     case CK_Silvermont:
     case CK_Goldmont:
     case CK_GoldmontPlus:
     case CK_Tremont:

clang/lib/Driver/ToolChains/Arch/X86.cpp

const char *x86::getX86TargetCPU(const ArgList &Args,
   if (const Arg *A = Args.getLastArgNoClaim(options::OPT__SLASH_arch)) {
     // Mapping built by looking at lib/Basic's X86TargetInfo::initFeatureMap().
     StringRef Arch = A->getValue();
     const char *CPU = nullptr;
     if (Triple.getArch() == llvm::Triple::x86) {  // 32-bit-only /arch: flags.
       CPU = llvm::StringSwitch<const char *>(Arch)
                 .Case("IA32", "i386")
                 .Case("SSE", "pentium3")
-                .Case("SSE2", "pentium4")
+                .Case("SSE2", "x86-32-sse2")
                 .Default(nullptr);
     }
     if (CPU == nullptr) {  // 32-bit and 64-bit /arch: flags.
       CPU = llvm::StringSwitch<const char *>(Arch)
                 .Case("AVX", "sandybridge")
                 .Case("AVX2", "haswell")
                 .Case("AVX512F", "knl")
                 .Case("AVX512", "skylake-avx512")
const char *x86::getX86TargetCPU(const ArgList &Args,
   case llvm::Triple::FreeBSD:
     return "i686";
   case llvm::Triple::NetBSD:
   case llvm::Triple::OpenBSD:
     return "i486";
   case llvm::Triple::Haiku:
     return "i586";
   default:
-    // Fallback to p4.
-    return "pentium4";
+    // Fallback to generic 32-bit CPU with sse2.
+    // FIXME: If we supported mtune this should just be pentium4 with generic
+    // tuning.
+    return "x86-32-sse2";
   }
 }
 
 void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple,
                                const ArgList &Args,
                                std::vector<StringRef> &Features) {
   // If -march=native, autodetect the feature list.
   if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_march_EQ)) {

clang/test/Driver/nacl-direct.c

 // Test clang changes for NaCl Support including:
 //    include paths, library paths, emulation, default static
 //
 // RUN: %clang -no-canonical-prefixes -### -o %t.o %s \
 // RUN:     -target i686-unknown-nacl -resource-dir foo 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-I686 %s
 // CHECK-I686: {{.*}}clang{{.*}}" "-cc1"
 // CHECK-I686-NOT: "-fno-use-init-array"
-// CHECK-I686: "-target-cpu" "pentium4"
+// CHECK-I686: "-target-cpu" "x86-32-sse2"
 // CHECK-I686: "-resource-dir" "foo"
 // CHECK-I686: "-internal-isystem" "foo{{/|\\\\}}include"
 // CHECK-I686: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}i686-nacl{{/|\\\\}}usr{{/|\\\\}}include"
 // CHECK-I686: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include"
 // CHECK-I686: as{{(.exe)?}}" "--32"
 // CHECK-I686: ld{{(.exe)?}}"
 // CHECK-I686: "--build-id"
 // CHECK-I686: "-m" "elf_i386_nacl"

clang/test/Driver/x86_features.c

 // RUN: %clang -target i386-unknown-unknown -### -S %s -msse -msse4 -mno-sse -mno-mmx -msse  2>&1 | FileCheck %s
-// CHECK: "pentium4" "-target-feature" "+sse4.2" "-target-feature" "-mmx" "-target-feature" "+sse"
+// CHECK: "x86-32-sse2" "-target-feature" "+sse4.2" "-target-feature" "-mmx" "-target-feature" "+sse"
 // Note that we filter out all but the last -m(no)sse.
 
 // Test that we don't produce an error with -mieee-fp.
 // RUN: %clang -### %s -mieee-fp -S 2>&1 | FileCheck --check-prefix=IEEE %s
 // IEEE-NOT: error: unknown argument

clang/test/Misc/target-invalid-cpu-note.c

 // X86-SAME: pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott,
 // X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
 // X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
 // X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
 // X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, knl, knm, lakemont, k6, k6-2, k6-3,
 // X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
 // X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
 // X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2,
-// X86-SAME: x86-64, geode
+// X86-SAME: x86-64, x86-32-sse2, geode
 
 // RUN: not %clang_cc1 -triple x86_64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86_64
 // X86_64: error: unknown target CPU 'not-a-cpu'
 // X86_64: note: valid target CPU values are: nocona, core2, penryn, bonnell,
 // X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere,
 // X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell,
 // X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake,
 // X86_64-SAME: icelake-client, icelake-server, tigerlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,

llvm/include/llvm/Support/X86TargetParser.h

enum CPUKind {
   CK_BTVER2,
   CK_BDVER1,
   CK_BDVER2,
   CK_BDVER3,
   CK_BDVER4,
   CK_ZNVER1,
   CK_ZNVER2,
   CK_x86_64,
+  CK_x86_32_sse2,
   CK_Geode,
 };
 
 /// Parse \p CPU string into a CPUKind. Will only accept 64-bit capable CPUs if
 /// \p Only64Bit is true.
 CPUKind parseArchX86(StringRef CPU, bool Only64Bit = false);
 
 /// Provide a list of valid CPU names. If \p Only64Bit is true, the list will

llvm/lib/Support/X86TargetParser.cpp

static constexpr ProcInfo Processors[] = {
   { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
   { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
   { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
   // Zen architecture processors.
   { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
   { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
   // Generic 64-bit processor.
   { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
+  // Generic 32-bit processor.
+  { {"x86-32-sse2"}, CK_x86_32_sse2, ~0U, FeaturesPentium4 },
   // Geode processors.
   { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
 };
 
 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
   for (const auto &P : Processors)
     if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
       return P.Kind;

llvm/lib/Target/X86/X86.td

def : ProcessorModel<"x86-64", SandyBridgeModel, [
   Feature64Bit,
   FeatureSlow3OpsLEA,
   FeatureSlowDivide64,
   FeatureSlowIncDec,
   FeatureMacroFusion,
   FeatureInsertVZEROUPPER
 ]>;
 
+// Provide a generic 32-bit sse2 CPU with modern tuning settings. This is the
+// default for 32-bit mode.
+// FIXME: If we supported mtune we could have generic tuning for modern with
+// arch as pentium4.
+def : ProcessorModel<"x86-32-sse2", SandyBridgeModel, [
+  FeatureX87,
+  FeatureCMPXCHG8B,
+  FeatureCMOV,
+  FeatureMMX,
+  FeatureSSE2,
+  FeatureFXSR,
+  FeatureNOPL,
+  FeatureSlow3OpsLEA,
+  FeatureSlowDivide64,
+  FeatureSlowIncDec,
+  FeatureMacroFusion,
+  FeatureInsertVZEROUPPER
+]>;
+
 //===----------------------------------------------------------------------===//
 // Calling Conventions
 //===----------------------------------------------------------------------===//
 
 include "X86CallingConv.td"
 
 
 //===----------------------------------------------------------------------===//