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Differential D83891

AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub
ClosedPublic

Authored by arsenm on Jul 15 2020, 10:58 AM.

Details

Reviewers
foad
kerbowa
Petar.Avramovic
mbrkusanin
Summary

This produces worse results right now for i8 vectors, but that should
be addressed when we actually try to optimize packed vectors.

Diff Detail

Event Timeline

arsenm created this revision.Jul 15 2020, 10:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 15 2020, 10:58 AM
Herald added subscribers: hiraditya, t-tye, tpr and 7 others. · View Herald Transcript
arsenm added parent revisions: D73051: [GlobalISel][AMDGPU] Legalize saturating add/subtract, D83715: AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat.Jul 15 2020, 10:58 AM
arsenm added a comment.Aug 4 2020, 5:49 AM

ping

foad added a comment.Aug 6 2020, 2:46 AM

Looks OK technically, but...

This produces worse results right now for i8 vectors

So is there any benefit to committing this now?

arsenm added a comment.Aug 6 2020, 6:44 AM
In D83891#2199198, @foad wrote:

Looks OK technically, but...

This produces worse results right now for i8 vectors

So is there any benefit to committing this now?

So I don't have another random patch hanging around to handle this one obscure case that I'm sure will get forgotten. This isn't a unique problem, all of the code that legalizes to packed operations is garbage until we have some vector and bit op combines

foad accepted this revision.Aug 6 2020, 6:47 AM
This revision is now accepted and ready to land.Aug 6 2020, 6:47 AM
arsenm closed this revision.Aug 6 2020, 8:08 AM

63c4be53cf5569369e67b5cd7958e5eb1bfcd85a

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
40 lines
40 lines
40 lines
40 lines
321 lines
321 lines
321 lines
321 lines

Diff 278245

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 426 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
.legalFor({S32, S16, V2S16}) .legalFor({S32, S16, V2S16})
.clampScalar(0, S16, S32) .clampScalar(0, S16, S32)
.clampMaxNumElements(0, S16, 2) .clampMaxNumElements(0, S16, 2)
.scalarize(0) .scalarize(0)
.widenScalarToNextPow2(0, 32); .widenScalarToNextPow2(0, 32);
getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT, G_SADDSAT, G_SSUBSAT}) getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT, G_SADDSAT, G_SSUBSAT})
.legalFor({S32, S16, V2S16}) // Clamp modifier .legalFor({S32, S16, V2S16}) // Clamp modifier
.minScalar(0, S16) .minScalarOrElt(0, S16)
.clampMaxNumElements(0, S16, 2) .clampMaxNumElements(0, S16, 2)
.scalarize(0) .scalarize(0)
.widenScalarToNextPow2(0, 32) .widenScalarToNextPow2(0, 32)
.lower(); .lower();
} else if (ST.has16BitInsts()) { } else if (ST.has16BitInsts()) {
assert(ST.hasIntClamp() && "all targets with 16-bit should support clamp"); assert(ST.hasIntClamp() && "all targets with 16-bit should support clamp");
// Technically the saturating operations require clamp bit support, but this // Technically the saturating operations require clamp bit support, but this
▲ Show 20 Lines • Show All 3,945 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir

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; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) ; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32) ; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32) ; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY6]](s32)
; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]] ; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C3]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[SHL]], [[SHL1]]
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SADDSAT]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[ASHR]](<2 x s16>)
; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX9: [[SADDSAT1:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL2]], [[SHL3]] ; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT1]], [[C3]](s16) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR]](s16) ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C4]]
; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16) ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]] ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C4]]
; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16) ; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]] ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(<2 x s8>) = G_BITCAST %2 %4:_(<2 x s8>) = G_BITCAST %2
%5:_(<2 x s8>) = G_BITCAST %3 %5:_(<2 x s8>) = G_BITCAST %3
▲ Show 20 Lines • Show All 841 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir

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; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) ; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32) ; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32) ; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY6]](s32)
; GFX9: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL]], [[SHL1]] ; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT]], [[C3]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[SSUBSAT:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[SHL]], [[SHL1]]
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SSUBSAT]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[ASHR]](<2 x s16>)
; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX9: [[SSUBSAT1:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL2]], [[SHL3]] ; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT1]], [[C3]](s16) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR]](s16) ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C4]]
; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16) ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]] ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C4]]
; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16) ; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]] ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(<2 x s8>) = G_BITCAST %2 %4:_(<2 x s8>) = G_BITCAST %2
%5:_(<2 x s8>) = G_BITCAST %3 %5:_(<2 x s8>) = G_BITCAST %3
▲ Show 20 Lines • Show All 841 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir

Show First 20 Lines • Show All 198 Lines • ▼ Show 20 Lines bb.0:
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) ; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32) ; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32) ; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY6]](s32)
; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]] ; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C3]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[UADDSAT:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[SHL]], [[SHL1]]
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX9: [[LSHR6:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[UADDSAT]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[LSHR6]](<2 x s16>)
; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX9: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL2]], [[SHL3]] ; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT1]], [[C3]](s16) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16) ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C4]]
; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16) ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]] ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C4]]
; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16) ; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]] ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(<2 x s8>) = G_BITCAST %2 %4:_(<2 x s8>) = G_BITCAST %2
%5:_(<2 x s8>) = G_BITCAST %3 %5:_(<2 x s8>) = G_BITCAST %3
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Lines bb.0:
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) ; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32) ; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32) ; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY6]](s32)
; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]] ; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C3]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[USUBSAT:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[SHL]], [[SHL1]]
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX9: [[LSHR6:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[USUBSAT]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[LSHR6]](<2 x s16>)
; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX9: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL2]], [[SHL3]] ; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT1]], [[C3]](s16) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16) ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C4]]
; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16) ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]] ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C4]]
; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16) ; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]] ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(<2 x s8>) = G_BITCAST %2 %4:_(<2 x s8>) = G_BITCAST %2
%5:_(<2 x s8>) = G_BITCAST %3 %5:_(<2 x s8>) = G_BITCAST %3
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llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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; GFX8-NEXT: v_and_b32_sdwa v1, sext(v1), v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, sext(v1), v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_saddsat_v2i8: ; GFX9-LABEL: v_saddsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8 ; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_and_or_b32 v0, v0, v4, v2
; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: v_and_or_b32 v1, v1, v4, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX9-NEXT: v_pk_add_i16 v0, v0, v1 clamp
; GFX9-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX9-NEXT: s_movk_i32 s4, 0xff ; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_add_i16 v1, v2, v3 clamp ; GFX9-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_saddsat_v2i8: ; GFX10-LABEL: v_saddsat_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b16_e64 v3, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, v2, v3
; GFX10-NEXT: v_and_or_b32 v1, v1, v2, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX10-NEXT: v_pk_add_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX10-NEXT: s_movk_i32 s4, 0xff ; GFX10-NEXT: s_movk_i32 s4, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_add_nc_i16 v1, v2, v1 clamp ; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_add_nc_i16 v0, v0, v3 clamp
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8> %lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8> %rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs) %result = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; GFX8-NEXT: s_and_b32 s1, s1, s2 ; GFX8-NEXT: s_and_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s0, s0, s2 ; GFX8-NEXT: s_and_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s4 ; GFX8-NEXT: s_lshl_b32 s1, s1, s4
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_v2i8: ; GFX9-LABEL: s_saddsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
; GFX9-NEXT: s_lshr_b32 s2, s0, 8 ; GFX9-NEXT: s_lshr_b32 s2, s0, 8
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_pack_ll_b32_b16 s2, 8, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-NEXT: s_lshr_b32 s4, s2, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s3, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s4 ; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshl_b32 s1, s3, s4 ; GFX9-NEXT: v_pk_ashrrev_i16 v0, s2, v0
; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshl_b32 s0, s2, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_add_i16 v1, s0, v1 clamp
; GFX9-NEXT: s_movk_i32 s0, 0xff ; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_and_b32_sdwa v0, sext(v0), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_saddsat_v2i8: ; GFX10-LABEL: s_saddsat_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s2, s0, 8 ; GFX10-NEXT: s_lshr_b32 s2, s0, 8
; GFX10-NEXT: s_bfe_u32 s3, 8, 0x100000 ; GFX10-NEXT: s_lshr_b32 s3, s1, 8
; GFX10-NEXT: s_lshr_b32 s4, s1, 8 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s0, s0, s3 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX10-NEXT: s_lshl_b32 s1, s1, s3 ; GFX10-NEXT: s_pack_ll_b32_b16 s2, 8, 8
; GFX10-NEXT: s_lshl_b32 s2, s2, s3 ; GFX10-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-NEXT: s_lshl_b32 s3, s4, s3 ; GFX10-NEXT: s_lshr_b32 s4, s2, 16
; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp ; GFX10-NEXT: s_lshr_b32 s5, s1, 16
; GFX10-NEXT: v_add_nc_i16 v1, s2, s3 clamp ; GFX10-NEXT: s_lshl_b32 s3, s3, s4
; GFX10-NEXT: s_movk_i32 s0, 0xff ; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
; GFX10-NEXT: s_lshl_b32 s4, s5, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_pk_add_i16 v0, s0, s1 clamp
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-NEXT: v_pk_ashrrev_i16 v0, s2, v0
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8> %lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8> %rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs) %result = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_and_b32_sdwa v1, sext(v3), v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, sext(v3), v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_saddsat_v4i8: ; GFX9-LABEL: v_saddsat_v4i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8 ; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1 ; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_and_or_b32 v0, v0, v8, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp ; GFX9-NEXT: v_and_or_b32 v2, v3, v8, v2
; GFX9-NEXT: v_add_i16 v1, v2, v5 clamp ; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6 ; GFX9-NEXT: v_and_or_b32 v1, v1, v8, v5
; GFX9-NEXT: v_and_or_b32 v3, v6, v8, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX9-NEXT: v_pk_lshlrev_b16 v2, s4, v2
; GFX9-NEXT: v_pk_lshlrev_b16 v3, s4, v3
; GFX9-NEXT: v_pk_add_i16 v0, v0, v1 clamp
; GFX9-NEXT: v_pk_add_i16 v1, v2, v3 clamp
; GFX9-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX9-NEXT: v_pk_ashrrev_i16 v1, s4, v1
; GFX9-NEXT: s_movk_i32 s4, 0xff ; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_sdwa v2, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_add_i16 v2, v2, v3 clamp ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4 ; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7 ; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_add_i16 v3, v3, v4 clamp ; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v2), s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v2, sext(v3), s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_saddsat_v4i8: ; GFX10-LABEL: v_saddsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b16_e64 v5, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v6, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshlrev_b16_e64 v6, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: s_mov_b32 s5, 16 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX10-NEXT: s_mov_b32 s4, 24 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX10-NEXT: v_add_nc_i16 v2, v2, v3 clamp ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_and_or_b32 v0, v0, v5, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v6
; GFX10-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX10-NEXT: v_and_or_b32 v3, v3, v5, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX10-NEXT: v_and_or_b32 v2, v8, v5, v2
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX10-NEXT: s_movk_i32 s5, 0xff ; GFX10-NEXT: s_movk_i32 s5, 0xff
; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_pk_lshlrev_b16 v3, s4, v3
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v2, sext(v2), s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_add_nc_i16 v5, v5, v6 clamp
; GFX10-NEXT: v_add_nc_i16 v3, v4, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp ; GFX10-NEXT: v_pk_add_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v2
; GFX10-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX10-NEXT: v_pk_add_i16 v1, v3, v1 clamp
; GFX10-NEXT: v_and_b32_sdwa v2, v0, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_pk_ashrrev_i16 v1, s4, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX10-NEXT: v_ashrrev_i16_e64 v4, 8, v5 ; GFX10-NEXT: v_and_b32_e32 v3, s5, v1
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v3), s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_and_b32_sdwa v1, v1, s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v2
; GFX10-NEXT: v_and_or_b32 v2, v4, s5, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0 ; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8> %lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8> %rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs) %result = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32 %cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result ret i32 %cast.result
} }
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s3, s4 ; GFX8-NEXT: s_and_b32 s1, s3, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 24 ; GFX8-NEXT: s_lshl_b32 s1, s1, 24
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_v4i8: ; GFX9-LABEL: s_saddsat_v4i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s8, 8, 0x100000 ; GFX9-NEXT: s_lshr_b32 s2, s0, 8
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-NEXT: s_lshr_b32 s4, s0, 24
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s4
; GFX9-NEXT: s_lshr_b32 s5, s1, 8 ; GFX9-NEXT: s_lshr_b32 s5, s1, 8
; GFX9-NEXT: s_lshr_b32 s6, s1, 16 ; GFX9-NEXT: s_lshr_b32 s6, s1, 16
; GFX9-NEXT: s_lshr_b32 s7, s1, 24 ; GFX9-NEXT: s_lshr_b32 s7, s1, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s8 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s6, s7
; GFX9-NEXT: s_lshr_b32 s5, s0, 16
; GFX9-NEXT: s_lshr_b32 s6, s4, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s5
; GFX9-NEXT: s_lshr_b32 s5, s2, 16
; GFX9-NEXT: s_lshl_b32 s2, s2, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5
; GFX9-NEXT: s_lshr_b32 s5, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX9-NEXT: s_lshr_b32 s5, s3, 16
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s1, s5, s8 ; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_lshr_b32 s2, s0, 8 ; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_lshr_b32 s3, s0, 16 ; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshr_b32 s4, s0, 24 ; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s5
; GFX9-NEXT: s_lshl_b32 s0, s0, s8 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp ; GFX9-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_lshl_b32 s0, s2, s8
; GFX9-NEXT: s_lshl_b32 s1, s6, s8
; GFX9-NEXT: v_add_i16 v1, s0, v1 clamp
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: s_lshl_b32 s0, s3, s8
; GFX9-NEXT: s_lshl_b32 s1, s7, s8
; GFX9-NEXT: v_add_i16 v2, s0, v2 clamp
; GFX9-NEXT: s_lshl_b32 s0, s4, s8
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_i16 v3, s0, v3 clamp
; GFX9-NEXT: s_movk_i32 s0, 0xff ; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_pk_add_i16 v1, s2, v1 clamp
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 ; GFX9-NEXT: v_and_b32_sdwa v2, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v1 ; GFX9-NEXT: v_pk_ashrrev_i16 v1, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v2), s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v2
; GFX9-NEXT: v_and_b32_sdwa v2, sext(v3), s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_e32 v2, s0, v1
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_saddsat_v4i8: ; GFX10-LABEL: s_saddsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s5, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s2, s0, 8 ; GFX10-NEXT: s_lshr_b32 s2, s0, 8
; GFX10-NEXT: s_lshr_b32 s6, s1, 8
; GFX10-NEXT: s_lshl_b32 s2, s2, s5
; GFX10-NEXT: s_lshl_b32 s6, s6, s5
; GFX10-NEXT: s_lshr_b32 s3, s0, 16 ; GFX10-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-NEXT: v_add_nc_i16 v1, s2, s6 clamp
; GFX10-NEXT: s_lshr_b32 s4, s0, 24 ; GFX10-NEXT: s_lshr_b32 s4, s0, 24
; GFX10-NEXT: s_movk_i32 s2, 0xff ; GFX10-NEXT: s_lshr_b32 s5, s1, 8
; GFX10-NEXT: s_lshl_b32 s0, s0, s5 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s7, s1, s5 ; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s4
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: s_lshr_b32 s6, s1, 16
; GFX10-NEXT: v_add_nc_i16 v0, s0, s7 clamp ; GFX10-NEXT: s_lshr_b32 s7, s1, 24
; GFX10-NEXT: s_lshr_b32 s0, s1, 16 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX10-NEXT: s_lshr_b32 s1, s1, 24 ; GFX10-NEXT: s_pack_ll_b32_b16 s3, 8, 8
; GFX10-NEXT: s_lshl_b32 s3, s3, s5 ; GFX10-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s5 ; GFX10-NEXT: s_lshr_b32 s5, s3, 16
; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s7
; GFX10-NEXT: s_lshr_b32 s7, s1, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshl_b32 s4, s4, s5 ; GFX10-NEXT: s_lshl_b32 s4, s4, s5
; GFX10-NEXT: s_lshl_b32 s1, s1, s5 ; GFX10-NEXT: s_lshl_b32 s1, s1, s3
; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0 ; GFX10-NEXT: s_lshl_b32 s7, s7, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX10-NEXT: v_add_nc_i16 v2, s3, s0 clamp ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s7
; GFX10-NEXT: v_add_nc_i16 v3, s4, s1 clamp ; GFX10-NEXT: s_lshr_b32 s4, s2, 16
; GFX10-NEXT: s_lshr_b32 s7, s6, 16
; GFX10-NEXT: v_pk_add_i16 v0, s0, s1 clamp
; GFX10-NEXT: s_lshl_b32 s2, s2, s3
; GFX10-NEXT: s_lshl_b32 s4, s4, s5
; GFX10-NEXT: s_lshl_b32 s0, s6, s3
; GFX10-NEXT: s_lshl_b32 s1, s7, s5
; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX10-NEXT: v_pk_ashrrev_i16 v0, s3, v0
; GFX10-NEXT: v_pk_add_i16 v1, s2, s0 clamp
; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, s2, v1 ; GFX10-NEXT: v_and_b32_sdwa v2, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v2), s2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_pk_ashrrev_i16 v1, s3, v1
; GFX10-NEXT: v_and_b32_sdwa v2, sext(v3), s2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX10-NEXT: v_and_b32_e32 v3, s0, v1
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_or_b32 v0, v0, s0, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8> %lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8> %rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs) %result = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32 %cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result ret i32 %cast.result
} }
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llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

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; GFX8-NEXT: v_and_b32_sdwa v1, sext(v1), v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, sext(v1), v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_ssubsat_v2i8: ; GFX9-LABEL: v_ssubsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8 ; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_and_or_b32 v0, v0, v4, v2
; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: v_and_or_b32 v1, v1, v4, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX9-NEXT: s_movk_i32 s4, 0xff ; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_sub_i16 v1, v2, v3 clamp ; GFX9-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_v2i8: ; GFX10-LABEL: v_ssubsat_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b16_e64 v3, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, v2, v3
; GFX10-NEXT: v_and_or_b32 v1, v1, v2, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX10-NEXT: s_movk_i32 s4, 0xff ; GFX10-NEXT: s_movk_i32 s4, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_sub_nc_i16 v1, v2, v1 clamp ; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_sub_nc_i16 v0, v0, v3 clamp
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8> %lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8> %rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs) %result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
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; GFX8-NEXT: s_and_b32 s1, s1, s2 ; GFX8-NEXT: s_and_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s0, s0, s2 ; GFX8-NEXT: s_and_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s4 ; GFX8-NEXT: s_lshl_b32 s1, s1, s4
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v2i8: ; GFX9-LABEL: s_ssubsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
; GFX9-NEXT: s_lshr_b32 s2, s0, 8 ; GFX9-NEXT: s_lshr_b32 s2, s0, 8
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_pack_ll_b32_b16 s2, 8, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-NEXT: s_lshr_b32 s4, s2, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s3, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s4 ; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshl_b32 s1, s3, s4 ; GFX9-NEXT: v_pk_ashrrev_i16 v0, s2, v0
; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshl_b32 s0, s2, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_sub_i16 v1, s0, v1 clamp
; GFX9-NEXT: s_movk_i32 s0, 0xff ; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_and_b32_sdwa v0, sext(v0), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_ssubsat_v2i8: ; GFX10-LABEL: s_ssubsat_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s2, s0, 8 ; GFX10-NEXT: s_lshr_b32 s2, s0, 8
; GFX10-NEXT: s_bfe_u32 s3, 8, 0x100000 ; GFX10-NEXT: s_lshr_b32 s3, s1, 8
; GFX10-NEXT: s_lshr_b32 s4, s1, 8 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s0, s0, s3 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX10-NEXT: s_lshl_b32 s1, s1, s3 ; GFX10-NEXT: s_pack_ll_b32_b16 s2, 8, 8
; GFX10-NEXT: s_lshl_b32 s2, s2, s3 ; GFX10-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-NEXT: s_lshl_b32 s3, s4, s3 ; GFX10-NEXT: s_lshr_b32 s4, s2, 16
; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp ; GFX10-NEXT: s_lshr_b32 s5, s1, 16
; GFX10-NEXT: v_sub_nc_i16 v1, s2, s3 clamp ; GFX10-NEXT: s_lshl_b32 s3, s3, s4
; GFX10-NEXT: s_movk_i32 s0, 0xff ; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
; GFX10-NEXT: s_lshl_b32 s4, s5, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-NEXT: v_pk_ashrrev_i16 v0, s2, v0
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8> %lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8> %rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs) %result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
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; GFX8-NEXT: v_and_b32_sdwa v1, sext(v3), v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, sext(v3), v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_ssubsat_v4i8: ; GFX9-LABEL: v_ssubsat_v4i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8 ; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1 ; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_and_or_b32 v0, v0, v8, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp ; GFX9-NEXT: v_and_or_b32 v2, v3, v8, v2
; GFX9-NEXT: v_sub_i16 v1, v2, v5 clamp ; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6 ; GFX9-NEXT: v_and_or_b32 v1, v1, v8, v5
; GFX9-NEXT: v_and_or_b32 v3, v6, v8, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX9-NEXT: v_pk_lshlrev_b16 v2, s4, v2
; GFX9-NEXT: v_pk_lshlrev_b16 v3, s4, v3
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: v_pk_sub_i16 v1, v2, v3 clamp
; GFX9-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX9-NEXT: v_pk_ashrrev_i16 v1, s4, v1
; GFX9-NEXT: s_movk_i32 s4, 0xff ; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_sdwa v2, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_sub_i16 v2, v2, v3 clamp ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4 ; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7 ; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_sub_i16 v3, v3, v4 clamp ; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v2), s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v2, sext(v3), s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_v4i8: ; GFX10-LABEL: v_ssubsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b16_e64 v5, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v6, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshlrev_b16_e64 v6, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: s_mov_b32 s5, 16 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX10-NEXT: s_mov_b32 s4, 24 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX10-NEXT: v_sub_nc_i16 v2, v2, v3 clamp ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_and_or_b32 v0, v0, v5, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v6
; GFX10-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX10-NEXT: v_and_or_b32 v3, v3, v5, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX10-NEXT: v_and_or_b32 v2, v8, v5, v2
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX10-NEXT: s_movk_i32 s5, 0xff ; GFX10-NEXT: s_movk_i32 s5, 0xff
; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_pk_lshlrev_b16 v3, s4, v3
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v2, sext(v2), s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_sub_nc_i16 v5, v5, v6 clamp
; GFX10-NEXT: v_sub_nc_i16 v3, v4, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp ; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v2
; GFX10-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX10-NEXT: v_pk_sub_i16 v1, v3, v1 clamp
; GFX10-NEXT: v_and_b32_sdwa v2, v0, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_pk_ashrrev_i16 v1, s4, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX10-NEXT: v_ashrrev_i16_e64 v4, 8, v5 ; GFX10-NEXT: v_and_b32_e32 v3, s5, v1
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v3), s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_and_b32_sdwa v1, v1, s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v2
; GFX10-NEXT: v_and_or_b32 v2, v4, s5, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0 ; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8> %lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8> %rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs) %result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32 %cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result ret i32 %cast.result
} }
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s3, s4 ; GFX8-NEXT: s_and_b32 s1, s3, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 24 ; GFX8-NEXT: s_lshl_b32 s1, s1, 24
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v4i8: ; GFX9-LABEL: s_ssubsat_v4i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s8, 8, 0x100000 ; GFX9-NEXT: s_lshr_b32 s2, s0, 8
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-NEXT: s_lshr_b32 s4, s0, 24
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s4
; GFX9-NEXT: s_lshr_b32 s5, s1, 8 ; GFX9-NEXT: s_lshr_b32 s5, s1, 8
; GFX9-NEXT: s_lshr_b32 s6, s1, 16 ; GFX9-NEXT: s_lshr_b32 s6, s1, 16
; GFX9-NEXT: s_lshr_b32 s7, s1, 24 ; GFX9-NEXT: s_lshr_b32 s7, s1, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s8 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s6, s7
; GFX9-NEXT: s_lshr_b32 s5, s0, 16
; GFX9-NEXT: s_lshr_b32 s6, s4, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s5
; GFX9-NEXT: s_lshr_b32 s5, s2, 16
; GFX9-NEXT: s_lshl_b32 s2, s2, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5
; GFX9-NEXT: s_lshr_b32 s5, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX9-NEXT: s_lshr_b32 s5, s3, 16
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s1, s5, s8 ; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_lshr_b32 s2, s0, 8 ; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_lshr_b32 s3, s0, 16 ; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshr_b32 s4, s0, 24 ; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s5
; GFX9-NEXT: s_lshl_b32 s0, s0, s8 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp ; GFX9-NEXT: v_pk_ashrrev_i16 v0, s4, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_lshl_b32 s0, s2, s8
; GFX9-NEXT: s_lshl_b32 s1, s6, s8
; GFX9-NEXT: v_sub_i16 v1, s0, v1 clamp
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: s_lshl_b32 s0, s3, s8
; GFX9-NEXT: s_lshl_b32 s1, s7, s8
; GFX9-NEXT: v_sub_i16 v2, s0, v2 clamp
; GFX9-NEXT: s_lshl_b32 s0, s4, s8
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_sub_i16 v3, s0, v3 clamp
; GFX9-NEXT: s_movk_i32 s0, 0xff ; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_pk_sub_i16 v1, s2, v1 clamp
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 ; GFX9-NEXT: v_and_b32_sdwa v2, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v1 ; GFX9-NEXT: v_pk_ashrrev_i16 v1, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v2), s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v2
; GFX9-NEXT: v_and_b32_sdwa v2, sext(v3), s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_e32 v2, s0, v1
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_ssubsat_v4i8: ; GFX10-LABEL: s_ssubsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s5, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s2, s0, 8 ; GFX10-NEXT: s_lshr_b32 s2, s0, 8
; GFX10-NEXT: s_lshr_b32 s6, s1, 8
; GFX10-NEXT: s_lshl_b32 s2, s2, s5
; GFX10-NEXT: s_lshl_b32 s6, s6, s5
; GFX10-NEXT: s_lshr_b32 s3, s0, 16 ; GFX10-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-NEXT: v_sub_nc_i16 v1, s2, s6 clamp
; GFX10-NEXT: s_lshr_b32 s4, s0, 24 ; GFX10-NEXT: s_lshr_b32 s4, s0, 24
; GFX10-NEXT: s_movk_i32 s2, 0xff ; GFX10-NEXT: s_lshr_b32 s5, s1, 8
; GFX10-NEXT: s_lshl_b32 s0, s0, s5 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s7, s1, s5 ; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s4
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: s_lshr_b32 s6, s1, 16
; GFX10-NEXT: v_sub_nc_i16 v0, s0, s7 clamp ; GFX10-NEXT: s_lshr_b32 s7, s1, 24
; GFX10-NEXT: s_lshr_b32 s0, s1, 16 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX10-NEXT: s_lshr_b32 s1, s1, 24 ; GFX10-NEXT: s_pack_ll_b32_b16 s3, 8, 8
; GFX10-NEXT: s_lshl_b32 s3, s3, s5 ; GFX10-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s5 ; GFX10-NEXT: s_lshr_b32 s5, s3, 16
; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s7
; GFX10-NEXT: s_lshr_b32 s7, s1, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshl_b32 s4, s4, s5 ; GFX10-NEXT: s_lshl_b32 s4, s4, s5
; GFX10-NEXT: s_lshl_b32 s1, s1, s5 ; GFX10-NEXT: s_lshl_b32 s1, s1, s3
; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0 ; GFX10-NEXT: s_lshl_b32 s7, s7, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX10-NEXT: v_sub_nc_i16 v2, s3, s0 clamp ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s7
; GFX10-NEXT: v_sub_nc_i16 v3, s4, s1 clamp ; GFX10-NEXT: s_lshr_b32 s4, s2, 16
; GFX10-NEXT: s_lshr_b32 s7, s6, 16
; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp
; GFX10-NEXT: s_lshl_b32 s2, s2, s3
; GFX10-NEXT: s_lshl_b32 s4, s4, s5
; GFX10-NEXT: s_lshl_b32 s0, s6, s3
; GFX10-NEXT: s_lshl_b32 s1, s7, s5
; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX10-NEXT: v_pk_ashrrev_i16 v0, s3, v0
; GFX10-NEXT: v_pk_sub_i16 v1, s2, s0 clamp
; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, s2, v1 ; GFX10-NEXT: v_and_b32_sdwa v2, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v1, sext(v2), s2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_pk_ashrrev_i16 v1, s3, v1
; GFX10-NEXT: v_and_b32_sdwa v2, sext(v3), s2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX10-NEXT: v_and_b32_e32 v3, s0, v1
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_or_b32 v0, v0, s0, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8> %lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8> %rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs) %result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32 %cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result ret i32 %cast.result
} }
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llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

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; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_uaddsat_v2i8: ; GFX9-LABEL: v_uaddsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8 ; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_and_or_b32 v0, v0, v4, v2
; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: v_and_or_b32 v1, v1, v4, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX9-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX9-NEXT: s_movk_i32 s4, 0xff ; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_add_u16_e64 v1, v2, v3 clamp ; GFX9-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_uaddsat_v2i8: ; GFX10-LABEL: v_uaddsat_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b16_e64 v3, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, v2, v3
; GFX10-NEXT: v_and_or_b32 v1, v1, v2, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX10-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX10-NEXT: s_movk_i32 s4, 0xff ; GFX10-NEXT: s_movk_i32 s4, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_add_nc_u16_e64 v1, v2, v1 clamp ; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v3 clamp
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8> %lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8> %rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs) %result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
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; GFX8-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_uaddsat_v2i8: ; GFX9-LABEL: s_uaddsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
; GFX9-NEXT: s_lshr_b32 s2, s0, 8 ; GFX9-NEXT: s_lshr_b32 s2, s0, 8
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_pack_ll_b32_b16 s2, 8, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-NEXT: s_lshr_b32 s4, s2, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s3, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s4 ; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshl_b32 s1, s3, s4 ; GFX9-NEXT: v_pk_lshrrev_b16 v0, s2, v0
; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp
; GFX9-NEXT: s_lshl_b32 s0, s2, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_add_u16_e64 v1, s0, v1 clamp
; GFX9-NEXT: s_movk_i32 s0, 0xff ; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_uaddsat_v2i8: ; GFX10-LABEL: s_uaddsat_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s2, s0, 8 ; GFX10-NEXT: s_lshr_b32 s2, s0, 8
; GFX10-NEXT: s_bfe_u32 s3, 8, 0x100000 ; GFX10-NEXT: s_lshr_b32 s3, s1, 8
; GFX10-NEXT: s_lshr_b32 s4, s1, 8 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s0, s0, s3 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX10-NEXT: s_lshl_b32 s1, s1, s3 ; GFX10-NEXT: s_pack_ll_b32_b16 s2, 8, 8
; GFX10-NEXT: s_lshl_b32 s2, s2, s3 ; GFX10-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-NEXT: s_lshl_b32 s3, s4, s3 ; GFX10-NEXT: s_lshr_b32 s4, s2, 16
; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s1 clamp ; GFX10-NEXT: s_lshr_b32 s5, s1, 16
; GFX10-NEXT: v_add_nc_u16_e64 v1, s2, s3 clamp ; GFX10-NEXT: s_lshl_b32 s3, s3, s4
; GFX10-NEXT: s_movk_i32 s0, 0xff ; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
; GFX10-NEXT: s_lshl_b32 s4, s5, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_pk_add_u16 v0, s0, s1 clamp
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-NEXT: v_pk_lshrrev_b16 v0, s2, v0
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8> %lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8> %rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs) %result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
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; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_uaddsat_v4i8: ; GFX9-LABEL: v_uaddsat_v4i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8 ; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1 ; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_and_or_b32 v0, v0, v8, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: v_and_or_b32 v2, v3, v8, v2
; GFX9-NEXT: v_add_u16_e64 v1, v2, v5 clamp ; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6 ; GFX9-NEXT: v_and_or_b32 v1, v1, v8, v5
; GFX9-NEXT: v_and_or_b32 v3, v6, v8, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX9-NEXT: v_pk_lshlrev_b16 v2, s4, v2
; GFX9-NEXT: v_pk_lshlrev_b16 v3, s4, v3
; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX9-NEXT: v_pk_add_u16 v1, v2, v3 clamp
; GFX9-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshrrev_b16 v1, s4, v1
; GFX9-NEXT: s_movk_i32 s4, 0xff ; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_sdwa v2, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_add_u16_e64 v2, v2, v3 clamp ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4 ; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7 ; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_add_u16_e64 v3, v3, v4 clamp ; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, v2, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v2, v3, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_uaddsat_v4i8: ; GFX10-LABEL: v_uaddsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b16_e64 v5, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v6, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshlrev_b16_e64 v6, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: s_mov_b32 s5, 16 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX10-NEXT: s_mov_b32 s4, 24 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX10-NEXT: v_add_nc_u16_e64 v2, v2, v3 clamp ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_and_or_b32 v0, v0, v5, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v6
; GFX10-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX10-NEXT: v_and_or_b32 v3, v3, v5, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX10-NEXT: v_and_or_b32 v2, v8, v5, v2
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX10-NEXT: s_movk_i32 s5, 0xff ; GFX10-NEXT: s_movk_i32 s5, 0xff
; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_pk_lshlrev_b16 v3, s4, v3
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v2, v2, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_add_nc_u16_e64 v5, v5, v6 clamp
; GFX10-NEXT: v_add_nc_u16_e64 v3, v4, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 clamp ; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX10-NEXT: v_pk_add_u16 v1, v3, v1 clamp
; GFX10-NEXT: v_and_b32_sdwa v2, v0, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_pk_lshrrev_b16 v1, s4, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX10-NEXT: v_lshrrev_b16_e64 v4, 8, v5 ; GFX10-NEXT: v_and_b32_e32 v3, s5, v1
; GFX10-NEXT: v_and_b32_sdwa v1, v3, s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_and_b32_sdwa v1, v1, s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v2
; GFX10-NEXT: v_and_or_b32 v2, v4, s5, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0 ; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8> %lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8> %rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs) %result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32 %cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result ret i32 %cast.result
} }
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_uaddsat_v4i8: ; GFX9-LABEL: s_uaddsat_v4i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s8, 8, 0x100000 ; GFX9-NEXT: s_lshr_b32 s2, s0, 8
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-NEXT: s_lshr_b32 s4, s0, 24
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s4
; GFX9-NEXT: s_lshr_b32 s5, s1, 8 ; GFX9-NEXT: s_lshr_b32 s5, s1, 8
; GFX9-NEXT: s_lshr_b32 s6, s1, 16 ; GFX9-NEXT: s_lshr_b32 s6, s1, 16
; GFX9-NEXT: s_lshr_b32 s7, s1, 24 ; GFX9-NEXT: s_lshr_b32 s7, s1, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s8 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s6, s7
; GFX9-NEXT: s_lshr_b32 s5, s0, 16
; GFX9-NEXT: s_lshr_b32 s6, s4, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s5
; GFX9-NEXT: s_lshr_b32 s5, s2, 16
; GFX9-NEXT: s_lshl_b32 s2, s2, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5
; GFX9-NEXT: s_lshr_b32 s5, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX9-NEXT: s_lshr_b32 s5, s3, 16
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s1, s5, s8 ; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_lshr_b32 s2, s0, 8 ; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_lshr_b32 s3, s0, 16 ; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshr_b32 s4, s0, 24 ; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s5
; GFX9-NEXT: s_lshl_b32 s0, s0, s8 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp ; GFX9-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_lshl_b32 s0, s2, s8
; GFX9-NEXT: s_lshl_b32 s1, s6, s8
; GFX9-NEXT: v_add_u16_e64 v1, s0, v1 clamp
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: s_lshl_b32 s0, s3, s8
; GFX9-NEXT: s_lshl_b32 s1, s7, s8
; GFX9-NEXT: v_add_u16_e64 v2, s0, v2 clamp
; GFX9-NEXT: s_lshl_b32 s0, s4, s8
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_u16_e64 v3, s0, v3 clamp
; GFX9-NEXT: s_movk_i32 s0, 0xff ; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_pk_add_u16 v1, s2, v1 clamp
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_and_b32_sdwa v2, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v1 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, v2, s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v2
; GFX9-NEXT: v_and_b32_sdwa v2, v3, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_e32 v2, s0, v1
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_uaddsat_v4i8: ; GFX10-LABEL: s_uaddsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s5, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s2, s0, 8 ; GFX10-NEXT: s_lshr_b32 s2, s0, 8
; GFX10-NEXT: s_lshr_b32 s6, s1, 8
; GFX10-NEXT: s_lshl_b32 s2, s2, s5
; GFX10-NEXT: s_lshl_b32 s6, s6, s5
; GFX10-NEXT: s_lshr_b32 s3, s0, 16 ; GFX10-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-NEXT: v_add_nc_u16_e64 v1, s2, s6 clamp
; GFX10-NEXT: s_lshr_b32 s4, s0, 24 ; GFX10-NEXT: s_lshr_b32 s4, s0, 24
; GFX10-NEXT: s_movk_i32 s2, 0xff ; GFX10-NEXT: s_lshr_b32 s5, s1, 8
; GFX10-NEXT: s_lshl_b32 s0, s0, s5 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s7, s1, s5 ; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s4
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: s_lshr_b32 s6, s1, 16
; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s7 clamp ; GFX10-NEXT: s_lshr_b32 s7, s1, 24
; GFX10-NEXT: s_lshr_b32 s0, s1, 16 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX10-NEXT: s_lshr_b32 s1, s1, 24 ; GFX10-NEXT: s_pack_ll_b32_b16 s3, 8, 8
; GFX10-NEXT: s_lshl_b32 s3, s3, s5 ; GFX10-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s5 ; GFX10-NEXT: s_lshr_b32 s5, s3, 16
; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s7
; GFX10-NEXT: s_lshr_b32 s7, s1, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshl_b32 s4, s4, s5 ; GFX10-NEXT: s_lshl_b32 s4, s4, s5
; GFX10-NEXT: s_lshl_b32 s1, s1, s5 ; GFX10-NEXT: s_lshl_b32 s1, s1, s3
; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: s_lshl_b32 s7, s7, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX10-NEXT: v_add_nc_u16_e64 v2, s3, s0 clamp ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s7
; GFX10-NEXT: v_add_nc_u16_e64 v3, s4, s1 clamp ; GFX10-NEXT: s_lshr_b32 s4, s2, 16
; GFX10-NEXT: s_lshr_b32 s7, s6, 16
; GFX10-NEXT: v_pk_add_u16 v0, s0, s1 clamp
; GFX10-NEXT: s_lshl_b32 s2, s2, s3
; GFX10-NEXT: s_lshl_b32 s4, s4, s5
; GFX10-NEXT: s_lshl_b32 s0, s6, s3
; GFX10-NEXT: s_lshl_b32 s1, s7, s5
; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX10-NEXT: v_pk_lshrrev_b16 v0, s3, v0
; GFX10-NEXT: v_pk_add_u16 v1, s2, s0 clamp
; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, s2, v1 ; GFX10-NEXT: v_and_b32_sdwa v2, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v1, v2, s2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_pk_lshrrev_b16 v1, s3, v1
; GFX10-NEXT: v_and_b32_sdwa v2, v3, s2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX10-NEXT: v_and_b32_e32 v3, s0, v1
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_or_b32 v0, v0, s0, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8> %lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8> %rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs) %result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32 %cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result ret i32 %cast.result
} }
▲ Show 20 Lines • Show All 3,286 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

Show First 20 Lines • Show All 221 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_usubsat_v2i8: ; GFX9-LABEL: v_usubsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8 ; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_and_or_b32 v0, v0, v4, v2
; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: v_and_or_b32 v1, v1, v4, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX9-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX9-NEXT: s_movk_i32 s4, 0xff ; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_sub_u16_e64 v1, v2, v3 clamp ; GFX9-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_usubsat_v2i8: ; GFX10-LABEL: v_usubsat_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b16_e64 v3, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, v2, v3
; GFX10-NEXT: v_and_or_b32 v1, v1, v2, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX10-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX10-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX10-NEXT: s_movk_i32 s4, 0xff ; GFX10-NEXT: s_movk_i32 s4, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_sub_nc_u16_e64 v1, v2, v1 clamp ; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v3 clamp
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8> %lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8> %rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs) %result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
Show All 38 Lines
; GFX8-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_usubsat_v2i8: ; GFX9-LABEL: s_usubsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
; GFX9-NEXT: s_lshr_b32 s2, s0, 8 ; GFX9-NEXT: s_lshr_b32 s2, s0, 8
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_pack_ll_b32_b16 s2, 8, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-NEXT: s_lshr_b32 s4, s2, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s3, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s4 ; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshl_b32 s1, s3, s4 ; GFX9-NEXT: v_pk_lshrrev_b16 v0, s2, v0
; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
; GFX9-NEXT: s_lshl_b32 s0, s2, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_sub_u16_e64 v1, s0, v1 clamp
; GFX9-NEXT: s_movk_i32 s0, 0xff ; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_usubsat_v2i8: ; GFX10-LABEL: s_usubsat_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s2, s0, 8 ; GFX10-NEXT: s_lshr_b32 s2, s0, 8
; GFX10-NEXT: s_bfe_u32 s3, 8, 0x100000 ; GFX10-NEXT: s_lshr_b32 s3, s1, 8
; GFX10-NEXT: s_lshr_b32 s4, s1, 8 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s0, s0, s3 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX10-NEXT: s_lshl_b32 s1, s1, s3 ; GFX10-NEXT: s_pack_ll_b32_b16 s2, 8, 8
; GFX10-NEXT: s_lshl_b32 s2, s2, s3 ; GFX10-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-NEXT: s_lshl_b32 s3, s4, s3 ; GFX10-NEXT: s_lshr_b32 s4, s2, 16
; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s1 clamp ; GFX10-NEXT: s_lshr_b32 s5, s1, 16
; GFX10-NEXT: v_sub_nc_u16_e64 v1, s2, s3 clamp ; GFX10-NEXT: s_lshl_b32 s3, s3, s4
; GFX10-NEXT: s_movk_i32 s0, 0xff ; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
; GFX10-NEXT: s_lshl_b32 s4, s5, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_pk_sub_u16 v0, s0, s1 clamp
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-NEXT: v_pk_lshrrev_b16 v0, s2, v0
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8> %lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8> %rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs) %result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
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; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_usubsat_v4i8: ; GFX9-LABEL: v_usubsat_v4i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8 ; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1 ; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_and_or_b32 v0, v0, v8, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: v_and_or_b32 v2, v3, v8, v2
; GFX9-NEXT: v_sub_u16_e64 v1, v2, v5 clamp ; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6 ; GFX9-NEXT: v_and_or_b32 v1, v1, v8, v5
; GFX9-NEXT: v_and_or_b32 v3, v6, v8, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX9-NEXT: v_pk_lshlrev_b16 v2, s4, v2
; GFX9-NEXT: v_pk_lshlrev_b16 v3, s4, v3
; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX9-NEXT: v_pk_sub_u16 v1, v2, v3 clamp
; GFX9-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX9-NEXT: v_pk_lshrrev_b16 v1, s4, v1
; GFX9-NEXT: s_movk_i32 s4, 0xff ; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_sdwa v2, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_sub_u16_e64 v2, v2, v3 clamp ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4 ; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7 ; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_sub_u16_e64 v3, v3, v4 clamp ; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, v2, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v2, v3, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_usubsat_v4i8: ; GFX10-LABEL: v_usubsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b16_e64 v5, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_sdwa v6, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshlrev_b16_e64 v6, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: s_mov_b32 s5, 16 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX10-NEXT: s_mov_b32 s4, 24 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, v3 clamp ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_and_or_b32 v0, v0, v5, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v6
; GFX10-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX10-NEXT: v_and_or_b32 v3, v3, v5, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, s4, v0
; GFX10-NEXT: v_and_or_b32 v2, v8, v5, v2
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v1
; GFX10-NEXT: s_movk_i32 s5, 0xff ; GFX10-NEXT: s_movk_i32 s5, 0xff
; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_pk_lshlrev_b16 v3, s4, v3
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v2, v2, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_sub_nc_u16_e64 v5, v5, v6 clamp
; GFX10-NEXT: v_sub_nc_u16_e64 v3, v4, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 clamp ; GFX10-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX10-NEXT: v_pk_lshlrev_b16 v1, s4, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX10-NEXT: v_pk_sub_u16 v1, v3, v1 clamp
; GFX10-NEXT: v_and_b32_sdwa v2, v0, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_pk_lshrrev_b16 v1, s4, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX10-NEXT: v_lshrrev_b16_e64 v4, 8, v5 ; GFX10-NEXT: v_and_b32_e32 v3, s5, v1
; GFX10-NEXT: v_and_b32_sdwa v1, v3, s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_and_b32_sdwa v1, v1, s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v2
; GFX10-NEXT: v_and_or_b32 v2, v4, s5, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0 ; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8> %lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8> %rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs) %result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32 %cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result ret i32 %cast.result
} }
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_usubsat_v4i8: ; GFX9-LABEL: s_usubsat_v4i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s8, 8, 0x100000 ; GFX9-NEXT: s_lshr_b32 s2, s0, 8
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-NEXT: s_lshr_b32 s4, s0, 24
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s4
; GFX9-NEXT: s_lshr_b32 s5, s1, 8 ; GFX9-NEXT: s_lshr_b32 s5, s1, 8
; GFX9-NEXT: s_lshr_b32 s6, s1, 16 ; GFX9-NEXT: s_lshr_b32 s6, s1, 16
; GFX9-NEXT: s_lshr_b32 s7, s1, 24 ; GFX9-NEXT: s_lshr_b32 s7, s1, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s8 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, 8, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s6, s7
; GFX9-NEXT: s_lshr_b32 s5, s0, 16
; GFX9-NEXT: s_lshr_b32 s6, s4, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s5
; GFX9-NEXT: s_lshr_b32 s5, s2, 16
; GFX9-NEXT: s_lshl_b32 s2, s2, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5
; GFX9-NEXT: s_lshr_b32 s5, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX9-NEXT: s_lshr_b32 s5, s3, 16
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s1, s5, s8 ; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_lshr_b32 s2, s0, 8 ; GFX9-NEXT: s_lshl_b32 s5, s5, s6
; GFX9-NEXT: s_lshr_b32 s3, s0, 16 ; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
; GFX9-NEXT: s_lshr_b32 s4, s0, 24 ; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s5
; GFX9-NEXT: s_lshl_b32 s0, s0, s8 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp ; GFX9-NEXT: v_pk_lshrrev_b16 v0, s4, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_lshl_b32 s0, s2, s8
; GFX9-NEXT: s_lshl_b32 s1, s6, s8
; GFX9-NEXT: v_sub_u16_e64 v1, s0, v1 clamp
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: s_lshl_b32 s0, s3, s8
; GFX9-NEXT: s_lshl_b32 s1, s7, s8
; GFX9-NEXT: v_sub_u16_e64 v2, s0, v2 clamp
; GFX9-NEXT: s_lshl_b32 s0, s4, s8
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_sub_u16_e64 v3, s0, v3 clamp
; GFX9-NEXT: s_movk_i32 s0, 0xff ; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_pk_sub_u16 v1, s2, v1 clamp
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_and_b32_sdwa v2, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v1 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, v2, s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v2
; GFX9-NEXT: v_and_b32_sdwa v2, v3, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX9-NEXT: v_and_b32_e32 v2, s0, v1
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_usubsat_v4i8: ; GFX10-LABEL: s_usubsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s5, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s2, s0, 8 ; GFX10-NEXT: s_lshr_b32 s2, s0, 8
; GFX10-NEXT: s_lshr_b32 s6, s1, 8
; GFX10-NEXT: s_lshl_b32 s2, s2, s5
; GFX10-NEXT: s_lshl_b32 s6, s6, s5
; GFX10-NEXT: s_lshr_b32 s3, s0, 16 ; GFX10-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-NEXT: v_sub_nc_u16_e64 v1, s2, s6 clamp
; GFX10-NEXT: s_lshr_b32 s4, s0, 24 ; GFX10-NEXT: s_lshr_b32 s4, s0, 24
; GFX10-NEXT: s_movk_i32 s2, 0xff ; GFX10-NEXT: s_lshr_b32 s5, s1, 8
; GFX10-NEXT: s_lshl_b32 s0, s0, s5 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s7, s1, s5 ; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s4
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: s_lshr_b32 s6, s1, 16
; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s7 clamp ; GFX10-NEXT: s_lshr_b32 s7, s1, 24
; GFX10-NEXT: s_lshr_b32 s0, s1, 16 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX10-NEXT: s_lshr_b32 s1, s1, 24 ; GFX10-NEXT: s_pack_ll_b32_b16 s3, 8, 8
; GFX10-NEXT: s_lshl_b32 s3, s3, s5 ; GFX10-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s5 ; GFX10-NEXT: s_lshr_b32 s5, s3, 16
; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s7
; GFX10-NEXT: s_lshr_b32 s7, s1, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshl_b32 s4, s4, s5 ; GFX10-NEXT: s_lshl_b32 s4, s4, s5
; GFX10-NEXT: s_lshl_b32 s1, s1, s5 ; GFX10-NEXT: s_lshl_b32 s1, s1, s3
; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: s_lshl_b32 s7, s7, s5
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX10-NEXT: v_sub_nc_u16_e64 v2, s3, s0 clamp ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s7
; GFX10-NEXT: v_sub_nc_u16_e64 v3, s4, s1 clamp ; GFX10-NEXT: s_lshr_b32 s4, s2, 16
; GFX10-NEXT: s_lshr_b32 s7, s6, 16
; GFX10-NEXT: v_pk_sub_u16 v0, s0, s1 clamp
; GFX10-NEXT: s_lshl_b32 s2, s2, s3
; GFX10-NEXT: s_lshl_b32 s4, s4, s5
; GFX10-NEXT: s_lshl_b32 s0, s6, s3
; GFX10-NEXT: s_lshl_b32 s1, s7, s5
; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX10-NEXT: v_pk_lshrrev_b16 v0, s3, v0
; GFX10-NEXT: v_pk_sub_u16 v1, s2, s0 clamp
; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, s2, v1 ; GFX10-NEXT: v_and_b32_sdwa v2, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v1, v2, s2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_pk_lshrrev_b16 v1, s3, v1
; GFX10-NEXT: v_and_b32_sdwa v2, v3, s2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX10-NEXT: v_and_b32_e32 v3, s0, v1
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_or_b32 v0, v0, s0, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8> %lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8> %rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs) %result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32 %cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result ret i32 %cast.result
} }
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