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Differential D83637

[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
ClosedPublic

Authored by critson on Jul 11 2020, 8:41 PM.

Details

Reviewers
rampitec
arsenm
nhaehnle
Commits
rG74c14202d90b: [AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
Summary

Preserve SCC dead flags in SIOptimizeExecMaskingPreRA.
This helps with removing redundant s_andn2 instructions later.

Diff Detail

Event Timeline

critson created this revision.Jul 11 2020, 8:41 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 11 2020, 8:41 PM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 7 others. · View Herald Transcript
Harbormaster completed remote builds in B63882: Diff 277273.Jul 11 2020, 9:18 PM
critson added a child revision: D83641: [AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns.Jul 12 2020, 1:30 AM
arsenm added inline comments.Jul 13 2020, 6:06 AM
llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
172–173

You know the exact 2 opcodes here, so you can just hardcode the scc index (which I think is just the last operand in both cases)

critson updated this revision to Diff 277457.Jul 13 2020, 9:17 AM

Hard code SCC operand number.

rampitec accepted this revision.Jul 13 2020, 9:51 AM
This revision is now accepted and ready to land.Jul 13 2020, 9:51 AM
Harbormaster completed remote builds in B63977: Diff 277457.Jul 13 2020, 10:21 AM
Closed by commit rG74c14202d90b: [AMDGPU] Propagate dead flag during pre-RA exec mask optimizations (authored by critson). · Explain WhyJul 13 2020, 8:54 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 277273

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Linesstatic unsigned optimizeVcndVcmpPair(MachineBasicBlock &MBB,
if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
Op1->getImm() != 0 || Op2->getImm() != 1) Op1->getImm() != 0 || Op2->getImm() != 1)
return AMDGPU::NoRegister; return AMDGPU::NoRegister;
LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t' LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t'
<< *And); << *And);
Register CCReg = CC->getReg(); Register CCReg = CC->getReg();
bool AndSCCIsDead = !!And->findRegisterDefOperand(AMDGPU::SCC, true);
LIS->RemoveMachineInstrFromMaps(*And); LIS->RemoveMachineInstrFromMaps(*And);
MachineInstr *Andn2 = MachineInstr *Andn2 =
BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc), BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc),
And->getOperand(0).getReg()) And->getOperand(0).getReg())
.addReg(ExecReg) .addReg(ExecReg)
.addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg()); .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
if (MachineOperand *Andn2SCC = Andn2->findRegisterDefOperand(AMDGPU::SCC))
Andn2SCC->setIsDead(AndSCCIsDead);
arsenmUnsubmitted
Not Done
ReplyInline Actions

You know the exact 2 opcodes here, so you can just hardcode the scc index (which I think is just the last operand in both cases)

arsenm: You know the exact 2 opcodes here, so you can just hardcode the scc index (which I think is…
And->eraseFromParent(); And->eraseFromParent();
LIS->InsertMachineInstrInMaps(*Andn2); LIS->InsertMachineInstrInMaps(*Andn2);
LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n'); LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
// Try to remove compare. Cmp value should not used in between of cmp // Try to remove compare. Cmp value should not used in between of cmp
// and s_and_b64 if VCC or just unused if any other register. // and s_and_b64 if VCC or just unused if any other register.
if ((Register::isVirtualRegister(CmpReg) && MRI.use_nodbg_empty(CmpReg)) || if ((Register::isVirtualRegister(CmpReg) && MRI.use_nodbg_empty(CmpReg)) ||
▲ Show 20 Lines • Show All 151 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
# s_cbranch_vccz, ensure that an undef operand is handled correctly. # s_cbranch_vccz, ensure that an undef operand is handled correctly.
--- ---
name: cndmask_cmp_cbranch_fold_undef name: cndmask_cmp_cbranch_fold_undef
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; GCN-LABEL: name: cndmask_cmp_cbranch_fold_undef ; GCN-LABEL: name: cndmask_cmp_cbranch_fold_undef
; GCN: bb.0: ; GCN: bb.0:
; GCN: successors: %bb.1(0x80000000) ; GCN: successors: %bb.1(0x80000000)
; GCN: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def $scc ; GCN: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def dead $scc
; GCN: S_CBRANCH_VCCZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCZ %bb.1, implicit $vcc
; GCN: bb.1: ; GCN: bb.1:
bb.0: bb.0:
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %0:sreg_64_xexec, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %0:sreg_64_xexec, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
$vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
S_CBRANCH_VCCZ %bb.1, implicit $vcc S_CBRANCH_VCCZ %bb.1, implicit $vcc
Show All 26 Lines

llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir

# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s
# GCN: name: negated_cond_vop2 # GCN: name: negated_cond_vop2
# GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN: %0:sgpr_32 = IMPLICIT_DEF
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop2 name: negated_cond_vop2
body: | body: |
bb.0: bb.0:
%0:sgpr_32 = IMPLICIT_DEF %0:sgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
$vcc_lo = S_AND_B32 $exec_lo, killed $vcc_lo, implicit-def dead $scc $vcc_lo = S_AND_B32 $exec_lo, killed $vcc_lo, implicit-def dead $scc
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
S_BRANCH %bb.0 S_BRANCH %bb.0
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop3 # GCN: name: negated_cond_vop3
# GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN: %0:sgpr_32 = IMPLICIT_DEF
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop3 name: negated_cond_vop3
body: | body: |
bb.0: bb.0:
%0:sgpr_32 = IMPLICIT_DEF %0:sgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
%2:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec %2:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines bb.1:
S_BRANCH %bb.0 S_BRANCH %bb.0
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop3_imp_vcc # GCN: name: negated_cond_vop3_imp_vcc
# GCN: $vcc_lo = IMPLICIT_DEF # GCN: $vcc_lo = IMPLICIT_DEF
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def $scc # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop3_imp_vcc name: negated_cond_vop3_imp_vcc
body: | body: |
bb.0: bb.0:
$vcc_lo = IMPLICIT_DEF $vcc_lo = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc_lo, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc_lo, implicit $exec
%2:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec %2:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
$vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc $vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
S_BRANCH %bb.0 S_BRANCH %bb.0
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop2_imp_vcc # GCN: name: negated_cond_vop2_imp_vcc
# GCN: $vcc_lo = IMPLICIT_DEF # GCN: $vcc_lo = IMPLICIT_DEF
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def $scc # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop2_imp_vcc name: negated_cond_vop2_imp_vcc
body: | body: |
bb.0: bb.0:
$vcc_lo = IMPLICIT_DEF $vcc_lo = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc_lo, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc_lo, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
Show All 32 Linesbody: |
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop2_used_sel # GCN: name: negated_cond_vop2_used_sel
# GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN: %0:sgpr_32 = IMPLICIT_DEF
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop2_used_sel name: negated_cond_vop2_used_sel
body: | body: |
bb.0: bb.0:
%0:sgpr_32 = IMPLICIT_DEF %0:sgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
Show All 9 Lines bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop2_used_vcc # GCN: name: negated_cond_vop2_used_vcc
# GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN: %0:sgpr_32 = IMPLICIT_DEF
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec # GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
# GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc # GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop2_used_vcc name: negated_cond_vop2_used_vcc
body: | body: |
bb.0: bb.0:
%0:sgpr_32 = IMPLICIT_DEF %0:sgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Linesbody: |
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop3_sel_right_subreg1 # GCN: name: negated_cond_vop3_sel_right_subreg1
# GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN: %0:sgpr_32 = IMPLICIT_DEF
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop3_sel_right_subreg1 name: negated_cond_vop3_sel_right_subreg1
body: | body: |
bb.0: bb.0:
%0:sgpr_32 = IMPLICIT_DEF %0:sgpr_32 = IMPLICIT_DEF
%1.sub1 = IMPLICIT_DEF %1.sub1 = IMPLICIT_DEF
%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
%2:sgpr_32 = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec %2:sgpr_32 = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec
$vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc $vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
S_BRANCH %bb.0 S_BRANCH %bb.0
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop3_sel_right_subreg2 # GCN: name: negated_cond_vop3_sel_right_subreg2
# GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN: %0:sgpr_32 = IMPLICIT_DEF
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop3_sel_right_subreg2 name: negated_cond_vop3_sel_right_subreg2
body: | body: |
bb.0: bb.0:
%0:sgpr_32 = IMPLICIT_DEF %0:sgpr_32 = IMPLICIT_DEF
%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
%1.sub1 = IMPLICIT_DEF %1.sub1 = IMPLICIT_DEF
Show All 37 Lines

llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s
# GCN: name: negated_cond_vop2 # GCN: name: negated_cond_vop2
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF # GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop2 name: negated_cond_vop2
body: | body: |
bb.0: bb.0:
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
S_BRANCH %bb.0 S_BRANCH %bb.0
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop3 # GCN: name: negated_cond_vop3
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF # GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop3 name: negated_cond_vop3
body: | body: |
bb.0: bb.0:
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines bb.1:
S_BRANCH %bb.0 S_BRANCH %bb.0
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop3_imp_vcc # GCN: name: negated_cond_vop3_imp_vcc
# GCN: $vcc = IMPLICIT_DEF # GCN: $vcc = IMPLICIT_DEF
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def $scc # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop3_imp_vcc name: negated_cond_vop3_imp_vcc
body: | body: |
bb.0: bb.0:
$vcc = IMPLICIT_DEF $vcc = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc, implicit $exec
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
S_BRANCH %bb.0 S_BRANCH %bb.0
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop2_imp_vcc # GCN: name: negated_cond_vop2_imp_vcc
# GCN: $vcc = IMPLICIT_DEF # GCN: $vcc = IMPLICIT_DEF
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def $scc # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop2_imp_vcc name: negated_cond_vop2_imp_vcc
body: | body: |
bb.0: bb.0:
$vcc = IMPLICIT_DEF $vcc = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
Show All 32 Linesbody: |
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop2_used_sel # GCN: name: negated_cond_vop2_used_sel
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF # GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop2_used_sel name: negated_cond_vop2_used_sel
body: | body: |
bb.0: bb.0:
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
Show All 9 Lines bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop2_used_vcc # GCN: name: negated_cond_vop2_used_vcc
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF # GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec # GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
# GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc # GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop2_used_vcc name: negated_cond_vop2_used_vcc
body: | body: |
bb.0: bb.0:
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Linesbody: |
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop3_sel_right_subreg1 # GCN: name: negated_cond_vop3_sel_right_subreg1
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF # GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop3_sel_right_subreg1 name: negated_cond_vop3_sel_right_subreg1
body: | body: |
bb.0: bb.0:
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1.sub1 = IMPLICIT_DEF %1.sub1 = IMPLICIT_DEF
%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec
$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
S_BRANCH %bb.0 S_BRANCH %bb.0
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop3_sel_right_subreg2 # GCN: name: negated_cond_vop3_sel_right_subreg2
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF # GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_vop3_sel_right_subreg2 name: negated_cond_vop3_sel_right_subreg2
body: | body: |
bb.0: bb.0:
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
%1.sub1 = IMPLICIT_DEF %1.sub1 = IMPLICIT_DEF
Show All 32 Lines bb.1:
S_BRANCH %bb.0 S_BRANCH %bb.0
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_vop2_dominated_blocks # GCN: name: negated_cond_vop2_dominated_blocks
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF # GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc # GCN: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
--- ---
name: negated_cond_vop2_dominated_blocks name: negated_cond_vop2_dominated_blocks
body: | body: |
bb.0: bb.0:
%0:sreg_64_xexec = IMPLICIT_DEF %0:sreg_64_xexec = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines bb.3:
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.4: bb.4:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN: name: negated_cond_subreg # GCN: name: negated_cond_subreg
# GCN: %0.sub0_sub1:sgpr_128 = IMPLICIT_DEF # GCN: %0.sub0_sub1:sgpr_128 = IMPLICIT_DEF
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0.sub0_sub1, implicit-def $scc # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0.sub0_sub1, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
--- ---
name: negated_cond_subreg name: negated_cond_subreg
body: | body: |
bb.0: bb.0:
%0.sub0_sub1:sgpr_128 = IMPLICIT_DEF %0.sub0_sub1:sgpr_128 = IMPLICIT_DEF
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0.sub0_sub1, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0.sub0_sub1, implicit $exec
%2.sub0_sub1:sgpr_128 = V_CMP_NE_U32_e64 %1, 1, implicit $exec %2.sub0_sub1:sgpr_128 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
Show All 10 Lines