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[PowerPC][Power10] 128-bit Binary Integer Operation instruction definitions and MC Tests
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Authored by Conanap on Jul 9 2020, 3:20 PM.

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Summary

This implements 128-bit Binary Integer Operation instruction definitions and MC tests used in vector shift builtins.

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Conanap created this revision.Jul 9 2020, 3:20 PM
Conanap edited the summary of this revision. (Show Details)Jul 10 2020, 12:04 PM
Conanap removed a reviewer: power-llvm-team.
Conanap retitled this revision from [PowerPC][Power10] RFC 2608 Instruction definitions and MC Tests to [PowerPC][Power10] Vector shift Instruction definitions and MC Tests.Jul 10 2020, 12:20 PM
Conanap edited the summary of this revision. (Show Details)
Conanap updated this revision to Diff 277127.Jul 10 2020, 12:37 PM

Added a new line to the end of ppc64-encoding-ISA31.txt

Conanap retitled this revision from [PowerPC][Power10] Vector shift Instruction definitions and MC Tests to [PowerPC][Power10] 128-bit Binary Integer Operation instruction definitions and MC Tests.Jul 10 2020, 12:58 PM
Conanap edited the summary of this revision. (Show Details)
lei accepted this revision.Jul 10 2020, 1:00 PM
lei added a subscriber: lei.

LGTM
Please address the nits on commit.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td
1035

nit: looks like there's a mix of diff spacings in the section above. Please keep it consistent. It should be def NAME : DEF

This revision is now accepted and ready to land.Jul 10 2020, 1:00 PM
Conanap updated this revision to Diff 277442.Jul 13 2020, 8:22 AM
Conanap marked an inline comment as done.

Some formatting changes

amyk accepted this revision.Jul 15 2020, 7:31 AM
amyk added a subscriber: amyk.

LGTM.

This revision was automatically updated to reflect the committed changes.