[NFC] Separate bitcode reading for FUNC_CODE_INST_CMPXCHG(_OLD)

[gchatelet]

Summary

This is preparatory work to unable storing alignment for AtomicCmpXchgInst.
See D83136 for context and bug: https://bugs.llvm.org/show_bug.cgi?id=27168

[gchatelet]

This patch splits the two implementations, moves a few lines and simplifies the code by inferring constant values.
The semantic is unchanged.

llvm/include/llvm/Bitcode/LLVMBitCodes.h

539

The documentation here was wrong.
alignment was never stored for FUNC_CODE_INST_CMPXCHG_OLD and failure_ordering and weak were optional.

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

4989

Each function taking Slot (previously OpNum) will increase it if successful.
This allows to replace OpNum + X by its value.

[jfb]

llvm/include/llvm/Bitcode/LLVMBitCodes.h

539

It used to only have "ordering", and didn't separate success / failure (so it wasn't optional as much as not there).

[gchatelet]

llvm/include/llvm/Bitcode/LLVMBitCodes.h

539

Thx for the explanation :)

[dmajor]

To connect the dots for anyone following along: this was reverted in cc28058c13e89ecc85dac7e1bd5d13a2ce1bb620.

[gchatelet]

In D83375#2169646, @dmajor wrote:

To connect the dots for anyone following along: this was reverted in cc28058c13e89ecc85dac7e1bd5d13a2ce1bb620.

Yes thx, I haven't been able to reproduce the error for now but working on it.

[courbet]

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

4989

I don't think there is any guarantee that they increase it by one. This could break silently in the future...

[courbet]

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

4989

Nevermind, I'm commenting on the old patch, I though I was looking at the new one...

llvm/include/llvm/Bitcode/LLVMBitCodes.h

enum FunctionCodes {
   FUNC_CODE_INST_INDIRECTBR = 31,       // INDIRECTBR: [opty, op0, op1, ...]
   // 32 is unused.
   FUNC_CODE_DEBUG_LOC_AGAIN = 33, // DEBUG_LOC_AGAIN
 
   FUNC_CODE_INST_CALL = 34, // CALL:    [attr, cc, fnty, fnid, args...]
 
   FUNC_CODE_DEBUG_LOC = 35,        // DEBUG_LOC:  [Line,Col,ScopeVal, IAVal]
   FUNC_CODE_INST_FENCE = 36,       // FENCE: [ordering, synchscope]
-  FUNC_CODE_INST_CMPXCHG_OLD = 37, // CMPXCHG: [ptrty,ptr,cmp,new, align, vol,
-                                   //           ordering, synchscope]
+  FUNC_CODE_INST_CMPXCHG_OLD = 37, // CMPXCHG: [ptrty, ptr, cmp, new, vol,
+                                   //           success_ordering, ssid,
+                                   //           failure_ordering?, weak?]
   FUNC_CODE_INST_ATOMICRMW = 38,   // ATOMICRMW: [ptrty,ptr,val, operation,
                                    //             align, vol,
                                    //             ordering, synchscope]
   FUNC_CODE_INST_RESUME = 39,      // RESUME:     [opval]
   FUNC_CODE_INST_LANDINGPAD_OLD =
       40,                         // LANDINGPAD: [ty,val,val,num,id0,val0...]
   FUNC_CODE_INST_LOADATOMIC = 41, // LOAD: [opty, op, align, vol,
                                   //        ordering, synchscope]
   FUNC_CODE_INST_STOREATOMIC_OLD = 42, // STORE: [ptrty,ptr,val, align, vol
                                        //         ordering, synchscope]
   FUNC_CODE_INST_GEP = 43,             // GEP:  [inbounds, n x operands]
   FUNC_CODE_INST_STORE = 44,       // STORE: [ptrty,ptr,valty,val, align, vol]
   FUNC_CODE_INST_STOREATOMIC = 45, // STORE: [ptrty,ptr,val, align, vol
-  FUNC_CODE_INST_CMPXCHG = 46,     // CMPXCHG: [ptrty,ptr,valty,cmp,new, align,
-                                   //           vol,ordering,synchscope]
+  FUNC_CODE_INST_CMPXCHG = 46,     // CMPXCHG: [ptrty, ptr, cmp, newval, vol,
+                                   //           success_ordering, ssid,
+                                   //           failure_ordering, weak]
   FUNC_CODE_INST_LANDINGPAD = 47,  // LANDINGPAD: [ty,val,num,id0,val0...]
   FUNC_CODE_INST_CLEANUPRET = 48,  // CLEANUPRET: [val] or [val,bb#]
   FUNC_CODE_INST_CATCHRET = 49,    // CATCHRET: [val,bb#]
   FUNC_CODE_INST_CATCHPAD = 50,    // CATCHPAD: [bb#,bb#,num,args...]
   FUNC_CODE_INST_CLEANUPPAD = 51,  // CLEANUPPAD: [num,args...]
   FUNC_CODE_INST_CATCHSWITCH =
       52, // CATCHSWITCH: [num,args...] or [num,args...,bb]
   // 53 is unused.

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

case bitc::FUNC_CODE_INST_STOREATOMIC_OLD: {
       if (Error Err = parseAlignmentValue(Record[OpNum], Align))
         return Err;
       if (!Align)
         return error("Alignment missing from atomic store");
       I = new StoreInst(Val, Ptr, Record[OpNum + 1], *Align, Ordering, SSID);
       InstructionList.push_back(I);
       break;
     }
-    case bitc::FUNC_CODE_INST_CMPXCHG_OLD:
-    case bitc::FUNC_CODE_INST_CMPXCHG: {
-      // CMPXCHG:[ptrty, ptr, cmp, new, vol, successordering, ssid,
+    case bitc::FUNC_CODE_INST_CMPXCHG_OLD: {
+      // CMPXCHG:[ptrty, ptr, cmp, new, vol, success_ordering, ssid,
       //          failureordering?, isweak?]
-      unsigned OpNum = 0;
-      Value *Ptr, *Cmp, *New;
-      if (getValueTypePair(Record, OpNum, NextValueNo, Ptr, &FullTy))
+      const size_t RecordCount = Record.size();
+      unsigned Slot = 0;
+      Value *Ptr = nullptr;
+      if (getValueTypePair(Record, Slot, NextValueNo, Ptr, &FullTy))
         return error("Invalid record");
 
       if (!isa<PointerType>(Ptr->getType()))
         return error("Cmpxchg operand is not a pointer type");
 
-      if (BitCode == bitc::FUNC_CODE_INST_CMPXCHG) {
-        if (getValueTypePair(Record, OpNum, NextValueNo, Cmp, &FullTy))
-          return error("Invalid record");
-      } else if (popValue(Record, OpNum, NextValueNo,
-                          getPointerElementFlatType(FullTy), Cmp))
+      Value *Cmp = nullptr;
+      if (popValue(Record, Slot, NextValueNo, getPointerElementFlatType(FullTy),
+                   Cmp))
+
+      if (!(RecordCount == 6 || RecordCount == 7 || RecordCount == 8))
         return error("Invalid record");
-      else
-        FullTy = cast<PointerType>(FullTy)->getElementType();
 
-      if (popValue(Record, OpNum, NextValueNo, Cmp->getType(), New) ||
-          Record.size() < OpNum + 3 || Record.size() > OpNum + 5)
+      Value *New = nullptr;
+      if (popValue(Record, Slot, NextValueNo, Cmp->getType(), New))
         return error("Invalid record");
 
-      AtomicOrdering SuccessOrdering = getDecodedOrdering(Record[OpNum + 1]);
+      if (Error Err = typeCheckLoadStoreInst(Cmp->getType(), Ptr->getType()))
+        return Err;
+
+      const bool IsVol = Record[3];
+
+      const AtomicOrdering SuccessOrdering = getDecodedOrdering(Record[4]);
       if (SuccessOrdering == AtomicOrdering::NotAtomic ||
           SuccessOrdering == AtomicOrdering::Unordered)
         return error("Invalid record");
-      SyncScope::ID SSID = getDecodedSyncScopeID(Record[OpNum + 2]);
 
-      if (Error Err = typeCheckLoadStoreInst(Cmp->getType(), Ptr->getType()))
-        return Err;
+      const SyncScope::ID SSID = getDecodedSyncScopeID(Record[5]);
+
       AtomicOrdering FailureOrdering;
-      if (Record.size() < 7)
+      if (RecordCount > 6)
+        FailureOrdering = getDecodedOrdering(Record[6]);
+      else
         FailureOrdering =
             AtomicCmpXchgInst::getStrongestFailureOrdering(SuccessOrdering);
-      else
-        FailureOrdering = getDecodedOrdering(Record[OpNum + 3]);
 
-      Align Alignment(
+      const Align Alignment(
           TheModule->getDataLayout().getTypeStoreSize(Cmp->getType()));
+
+      FullTy = cast<PointerType>(FullTy)->getElementType();
+      FullTy = StructType::get(Context, {FullTy, Type::getInt1Ty(Context)});
       I = new AtomicCmpXchgInst(Ptr, Cmp, New, Alignment, SuccessOrdering,
                                 FailureOrdering, SSID);
-      FullTy = StructType::get(Context, {FullTy, Type::getInt1Ty(Context)});
-      cast<AtomicCmpXchgInst>(I)->setVolatile(Record[OpNum]);
 
-      if (Record.size() < 8) {
+      cast<AtomicCmpXchgInst>(I)->setVolatile(IsVol);
+
+      if (RecordCount > 7) {
+        cast<AtomicCmpXchgInst>(I)->setWeak(Record[7]);
+      } else {
         // Before weak cmpxchgs existed, the instruction simply returned the
         // value loaded from memory, so bitcode files from that era will be
         // expecting the first component of a modern cmpxchg.
         CurBB->getInstList().push_back(I);
         I = ExtractValueInst::Create(I, 0);
         FullTy = cast<StructType>(FullTy)->getElementType(0);
-      } else {
-        cast<AtomicCmpXchgInst>(I)->setWeak(Record[OpNum+4]);
       }
+      InstructionList.push_back(I);
+      break;
+    }
+    case bitc::FUNC_CODE_INST_CMPXCHG: {
+      // CMPXCHG: [ptrty, ptr, cmp, newval, vol, success_ordering, ssid,
+      //           failure_ordering, weak]
+      const size_t RecordCount = Record.size();
+      unsigned Slot = 0;
+      Value *Ptr = nullptr;
+      if (getValueTypePair(Record, Slot, NextValueNo, Ptr, &FullTy))
+        return error("Invalid record");
+
+      if (!isa<PointerType>(Ptr->getType()))
+        return error("Cmpxchg operand is not a pointer type");
+
+      Value *Cmp = nullptr;
+      if (getValueTypePair(Record, Slot, NextValueNo, Cmp, &FullTy))
+        return error("Invalid record");
+
+      if (RecordCount != 8)
+        return error("Invalid record");
+
+      Value *New = nullptr;
+      if (popValue(Record, Slot, NextValueNo, Cmp->getType(), New))
+        return error("Invalid record");
+
+      const bool IsVol = Record[3];
+
+      const AtomicOrdering SuccessOrdering = getDecodedOrdering(Record[4]);
+      if (SuccessOrdering == AtomicOrdering::NotAtomic ||
+          SuccessOrdering == AtomicOrdering::Unordered)
+        return error("Invalid record");
+
+      const SyncScope::ID SSID = getDecodedSyncScopeID(Record[5]);
+
+      if (Error Err = typeCheckLoadStoreInst(Cmp->getType(), Ptr->getType()))
+        return Err;
+
+      const AtomicOrdering FailureOrdering = getDecodedOrdering(Record[6]);
+
+      const bool IsWeak = Record[7];
+
+      const Align Alignment(
+          TheModule->getDataLayout().getTypeStoreSize(Cmp->getType()));
+
+      FullTy = StructType::get(Context, {FullTy, Type::getInt1Ty(Context)});
+      I = new AtomicCmpXchgInst(Ptr, Cmp, New, Alignment, SuccessOrdering,
+                                FailureOrdering, SSID);
+
+      cast<AtomicCmpXchgInst>(I)->setVolatile(IsVol);
+      cast<AtomicCmpXchgInst>(I)->setWeak(IsWeak);
 
       InstructionList.push_back(I);
       break;
     }
     case bitc::FUNC_CODE_INST_ATOMICRMW: {
       // ATOMICRMW:[ptrty, ptr, val, op, vol, ordering, ssid]
       unsigned OpNum = 0;
       Value *Ptr, *Val;