Random access iterators must handle operator+, where the iterator is on the
RHS. The system header simulator library is extended with these operators.
Details
Details
Diff Detail
Diff Detail
- Repository
- rG LLVM Github Monorepo
Paths
| Differential D83226
[analyzer] Add system header simulator a symmetric random access iterator operator+ ClosedPublic Authored by gamesh411 on Jul 6 2020, 7:17 AM.
Details Summary Random access iterators must handle operator+, where the iterator is on the
Diff Detail
Event TimelineHerald added subscribers: cfe-commits, ASDenysPetrov, martong and 11 others. · View Herald Transcript gamesh411 added a child revision: D83190: [analyzer] Model iterator random incrementation symmetrically.Jul 6 2020, 7:39 AM This revision is now accepted and ready to land.Jul 14 2020, 4:23 AM Closed by commit rGfd02a86260b3: [analyzer] Add system header simulator a symmetric random access iterator… (authored by gamesh411). · Explain WhyJul 17 2020, 5:39 AM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 275703 clang/test/Analysis/Inputs/system-header-simulator-cxx.h
clang/test/Analysis/diagnostics/explicit-suppression.cpp
|