This is an archive of the discontinued LLVM Phabricator instance.

[analyzer] Add system header simulator a symmetric random access iterator operator+
ClosedPublic

Authored by gamesh411 on Jul 6 2020, 7:17 AM.

Details

Summary

Random access iterators must handle operator+, where the iterator is on the
RHS. The system header simulator library is extended with these operators.

Diff Detail

Event Timeline

gamesh411 created this revision.Jul 6 2020, 7:17 AM
This revision is now accepted and ready to land.Jul 14 2020, 4:23 AM
This revision was automatically updated to reflect the committed changes.