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[analyzer] Add system header simulator a symmetric random access iterator operator+
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Authored by gamesh411 on Jul 6 2020, 7:17 AM.

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Summary

Random access iterators must handle operator+, where the iterator is on the
RHS. The system header simulator library is extended with these operators.

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Event Timeline

gamesh411 created this revision.Jul 6 2020, 7:17 AM
This revision is now accepted and ready to land.Jul 14 2020, 4:23 AM
This revision was automatically updated to reflect the committed changes.