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Differential D82929

[PowerPC][Power10] Add Vector Multiply/Mod/Divide Instruction Definitions and MC Tests
ClosedPublic

Authored by amyk on Jun 30 2020, 8:49 PM.

Details

Reviewers
power-llvm-team
lei
Group Reviewers
Restricted Project
Commits
rG1eb279d2a8c8: [PowerPC][Power10] Add Vector Multiply/Mod/Divide Instruction Definitions and…
Summary

This patch adds the td definitions and asm/disasm tests for the following instructions:

vmulld 
vmodsw  
vmoduw 
vmodsd 
vmodud  
vdivsw  
vdivuw  
vdivsd  
vdivud  

vmulhsw  
vmulhuw  
vmulhsd 
vmulhud  

vdivesw  
vdiveuw  
vdivesd  
vdiveud

Diff Detail

Unit TestsFailed

TimeTest
10,580 mslinux > libomp.env::Unknown Unit Message ("")
1,450 mslinux > libomp.worksharing/for::Unknown Unit Message ("")

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
34 lines
test/
MC/
Disassembler/
PowerPC/
51 lines
PowerPC/
51 lines

Diff 274669

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Show First 20 Lines • Show All 803 Lines • ▼ Show 20 Lineslet Predicates = [IsISA3_1] in {
def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
"vclrlb $vD, $vA, $rB", IIC_VecGeneral, "vclrlb $vD, $vA, $rB", IIC_VecGeneral,
[(set v16i8:$vD, [(set v16i8:$vD,
(int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>; (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
"vclrrb $vD, $vA, $rB", IIC_VecGeneral, "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
[(set v16i8:$vD, [(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>; (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmulld $vD, $vA, $vB", IIC_VecGeneral, []>;
def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmulhsw $vD, $vA, $vB", IIC_VecGeneral, []>;
def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmulhuw $vD, $vA, $vB", IIC_VecGeneral, []>;
def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmulhsd $vD, $vA, $vB", IIC_VecGeneral, []>;
def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmulhud $vD, $vA, $vB", IIC_VecGeneral, []>;
def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmodsw $vD, $vA, $vB", IIC_VecGeneral, []>;
def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmoduw $vD, $vA, $vB", IIC_VecGeneral, []>;
def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmodsd $vD, $vA, $vB", IIC_VecGeneral, []>;
def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmodud $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivsw $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivuw $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivsd $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivud $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivesw $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdiveuw $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivesd $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdiveud $vD, $vA, $vB", IIC_VecGeneral, []>;
} }
//---------------------------- Anonymous Patterns ----------------------------// //---------------------------- Anonymous Patterns ----------------------------//
let Predicates = [IsISA3_1] in { let Predicates = [IsISA3_1] in {
def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)), def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
(v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>; (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;
def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)), def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)),
(v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>; (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;
def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)), def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),
(v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>; (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)), def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
(v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>; (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
} }

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt

Show First 20 Lines • Show All 224 Lines • ▼ Show 20 Lines
# CHECK: xxblendvd 6, 63, 21, 34 # CHECK: xxblendvd 6, 63, 21, 34
0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0xbc 0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0xbc
# CHECK: vsldbi 2, 3, 4, 5 # CHECK: vsldbi 2, 3, 4, 5
0x10 0x43 0x21 0x56 0x10 0x43 0x21 0x56
# CHECK: vsrdbi 2, 3, 4, 5 # CHECK: vsrdbi 2, 3, 4, 5
0x10 0x43 0x23 0x56 0x10 0x43 0x23 0x56
# CHECK: vmulld 1, 2, 3
0x10 0x22 0x19 0xc9
# CHECK: vmodsw 21, 11, 10
0x12 0xab 0x57 0x8b
# CHECK: vmoduw 21, 11, 10
0x12 0xab 0x56 0x8b
# CHECK: vmodsd 21, 11, 10
0x12 0xab 0x57 0xcb
# CHECK: vmodud 21, 11, 10
0x12 0xab 0x56 0xcb
# CHECK: vdivsw 21, 11, 10
0x12 0xab 0x51 0x8b
# CHECK: vdivuw 21, 11, 10
0x12 0xab 0x50 0x8b
# CHECK: vdivsd 21, 11, 10
0x12 0xab 0x51 0xcb
# CHECK: vdivud 21, 11, 10
0x12 0xab 0x50 0xcb
# CHECK: vmulhsw 1, 2, 3
0x10 0x22 0x1b 0x89
# CHECK: vmulhuw 1, 2, 3
0x10 0x22 0x1a 0x89
# CHECK: vmulhsd 1, 2, 3
0x10 0x22 0x1b 0xc9
# CHECK: vmulhud 1, 2, 3
0x10 0x22 0x1a 0xc9
# CHECK: vdivesw 21, 11, 10
0x12 0xab 0x53 0x8b
# CHECK: vdiveuw 21, 11, 10
0x12 0xab 0x52 0x8b
# CHECK: vdivesd 21, 11, 10
0x12 0xab 0x53 0xcb
# CHECK: vdiveud 21, 11, 10
0x12 0xab 0x52 0xcb

llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

Show First 20 Lines • Show All 351 Lines • ▼ Show 20 Lines
# CHECK-LE-SAME: 0xbc,0xa8,0xdf,0x84] # CHECK-LE-SAME: 0xbc,0xa8,0xdf,0x84]
xxblendvd 6, 63, 21, 34 xxblendvd 6, 63, 21, 34
# CHECK-BE: vsldbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x56] # CHECK-BE: vsldbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x56]
# CHECK-LE: vsldbi 2, 3, 4, 5 # encoding: [0x56,0x21,0x43,0x10] # CHECK-LE: vsldbi 2, 3, 4, 5 # encoding: [0x56,0x21,0x43,0x10]
vsldbi 2, 3, 4, 5 vsldbi 2, 3, 4, 5
# CHECK-BE: vsrdbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x23,0x56] # CHECK-BE: vsrdbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x23,0x56]
# CHECK-LE: vsrdbi 2, 3, 4, 5 # encoding: [0x56,0x23,0x43,0x10] # CHECK-LE: vsrdbi 2, 3, 4, 5 # encoding: [0x56,0x23,0x43,0x10]
vsrdbi 2, 3, 4, 5 vsrdbi 2, 3, 4, 5
# CHECK-BE: vmulld 1, 2, 3 # encoding: [0x10,0x22,0x19,0xc9]
# CHECK-LE: vmulld 1, 2, 3 # encoding: [0xc9,0x19,0x22,0x10]
vmulld 1, 2, 3
# CHECK-BE: vmulhsw 1, 2, 3 # encoding: [0x10,0x22,0x1b,0x89]
# CHECK-LE: vmulhsw 1, 2, 3 # encoding: [0x89,0x1b,0x22,0x10]
vmulhsw 1, 2, 3
# CHECK-BE: vmulhuw 1, 2, 3 # encoding: [0x10,0x22,0x1a,0x89]
# CHECK-LE: vmulhuw 1, 2, 3 # encoding: [0x89,0x1a,0x22,0x10]
vmulhuw 1, 2, 3
# CHECK-BE: vmulhsd 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xc9]
# CHECK-LE: vmulhsd 1, 2, 3 # encoding: [0xc9,0x1b,0x22,0x10]
vmulhsd 1, 2, 3
# CHECK-BE: vmulhud 1, 2, 3 # encoding: [0x10,0x22,0x1a,0xc9]
# CHECK-LE: vmulhud 1, 2, 3 # encoding: [0xc9,0x1a,0x22,0x10]
vmulhud 1, 2, 3
# CHECK-BE: vmodsw 21, 11, 10 # encoding: [0x12,0xab,0x57,0x8b]
# CHECK-LE: vmodsw 21, 11, 10 # encoding: [0x8b,0x57,0xab,0x12]
vmodsw 21, 11, 10
# CHECK-BE: vmoduw 21, 11, 10 # encoding: [0x12,0xab,0x56,0x8b]
# CHECK-LE: vmoduw 21, 11, 10 # encoding: [0x8b,0x56,0xab,0x12]
vmoduw 21, 11, 10
# CHECK-BE: vmodsd 21, 11, 10 # encoding: [0x12,0xab,0x57,0xcb]
# CHECK-LE: vmodsd 21, 11, 10 # encoding: [0xcb,0x57,0xab,0x12]
vmodsd 21, 11, 10
# CHECK-BE: vmodud 21, 11, 10 # encoding: [0x12,0xab,0x56,0xcb]
# CHECK-LE: vmodud 21, 11, 10 # encoding: [0xcb,0x56,0xab,0x12]
vmodud 21, 11, 10
# CHECK-BE: vdivsw 21, 11, 10 # encoding: [0x12,0xab,0x51,0x8b]
# CHECK-LE: vdivsw 21, 11, 10 # encoding: [0x8b,0x51,0xab,0x12]
vdivsw 21, 11, 10
# CHECK-BE: vdivuw 21, 11, 10 # encoding: [0x12,0xab,0x50,0x8b]
# CHECK-LE: vdivuw 21, 11, 10 # encoding: [0x8b,0x50,0xab,0x12]
vdivuw 21, 11, 10
# CHECK-BE: vdivsd 21, 11, 10 # encoding: [0x12,0xab,0x51,0xcb]
# CHECK-LE: vdivsd 21, 11, 10 # encoding: [0xcb,0x51,0xab,0x12]
vdivsd 21, 11, 10
# CHECK-BE: vdivud 21, 11, 10 # encoding: [0x12,0xab,0x50,0xcb]
# CHECK-LE: vdivud 21, 11, 10 # encoding: [0xcb,0x50,0xab,0x12]
vdivud 21, 11, 10
# CHECK-BE: vdivesw 21, 11, 10 # encoding: [0x12,0xab,0x53,0x8b]
# CHECK-LE: vdivesw 21, 11, 10 # encoding: [0x8b,0x53,0xab,0x12]
vdivesw 21, 11, 10
# CHECK-BE: vdiveuw 21, 11, 10 # encoding: [0x12,0xab,0x52,0x8b]
# CHECK-LE: vdiveuw 21, 11, 10 # encoding: [0x8b,0x52,0xab,0x12]
vdiveuw 21, 11, 10
# CHECK-BE: vdivesd 21, 11, 10 # encoding: [0x12,0xab,0x53,0xcb]
# CHECK-LE: vdivesd 21, 11, 10 # encoding: [0xcb,0x53,0xab,0x12]
vdivesd 21, 11, 10
# CHECK-BE: vdiveud 21, 11, 10 # encoding: [0x12,0xab,0x52,0xcb]
# CHECK-LE: vdiveud 21, 11, 10 # encoding: [0xcb,0x52,0xab,0x12]
vdiveud 21, 11, 10