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Differential D82913

[RISCV] Add mcountinhibit CSR
ClosedPublic

Authored by pzheng on Jun 30 2020, 2:34 PM.

Details

Reviewers
apazos
asb
lenary
luismarques
Commits
rGd36f2c6a6c4b: [RISCV] Add mcountinhibit CSR
Summary

The mcountinhibit CSR is defined in the ratified 1.11 version of the privileged
spec.

Diff Detail

Event Timeline

pzheng created this revision.Jun 30 2020, 2:34 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 30 2020, 2:34 PM
Herald added subscribers: llvm-commits, evandro, sameer.abuasal and 23 others. · View Herald Transcript
Harbormaster failed remote builds in B62406: Diff 274617!Jun 30 2020, 3:46 PM
asb accepted this revision.Jun 30 2020, 9:31 PM

Looks good to me, thanks for catching this.

This revision is now accepted and ready to land.Jun 30 2020, 9:31 PM
Closed by commit rGd36f2c6a6c4b: [RISCV] Add mcountinhibit CSR (authored by pzheng). · Explain WhyJul 1 2020, 8:38 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
1 line
test/
MC/
RISCV/
14 lines

Diff 274828

llvm/lib/Target/RISCV/RISCVSystemOperands.td

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def: SysReg<"mhpmcounter29h", 0xB9D>; def: SysReg<"mhpmcounter29h", 0xB9D>;
def: SysReg<"mhpmcounter30h", 0xB9E>; def: SysReg<"mhpmcounter30h", 0xB9E>;
def: SysReg<"mhpmcounter31h", 0xB9F>; def: SysReg<"mhpmcounter31h", 0xB9F>;
} }
//===-------------------------- //===--------------------------
// Machine Counter Setup // Machine Counter Setup
//===-------------------------- //===--------------------------
def : SysReg<"mcountinhibit", 0x320>;
def : SysReg<"mhpmevent3", 0x323>; def : SysReg<"mhpmevent3", 0x323>;
def : SysReg<"mhpmevent4", 0x324>; def : SysReg<"mhpmevent4", 0x324>;
def : SysReg<"mhpmevent5", 0x325>; def : SysReg<"mhpmevent5", 0x325>;
def : SysReg<"mhpmevent6", 0x326>; def : SysReg<"mhpmevent6", 0x326>;
def : SysReg<"mhpmevent7", 0x327>; def : SysReg<"mhpmevent7", 0x327>;
def : SysReg<"mhpmevent8", 0x328>; def : SysReg<"mhpmevent8", 0x328>;
def : SysReg<"mhpmevent9", 0x329>; def : SysReg<"mhpmevent9", 0x329>;
def : SysReg<"mhpmevent10", 0x32A>; def : SysReg<"mhpmevent10", 0x32A>;
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llvm/test/MC/RISCV/machine-csr-names.s

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csrrs t1, mhpmcounter31, zero csrrs t1, mhpmcounter31, zero
# uimm12 # uimm12
csrrs t2, 0xB1F, zero csrrs t2, 0xB1F, zero
###################################### ######################################
# Machine Counter Setup # Machine Counter Setup
###################################### ######################################
# mcountinhibit
# name
# CHECK-INST: csrrs t1, mcountinhibit, zero
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x32]
# CHECK-INST-ALIAS: csrr t1, mcountinhibit
# uimm12
# CHECK-INST: csrrs t2, mcountinhibit, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x32]
# CHECK-INST-ALIAS: csrr t2, mcountinhibit
# name
csrrs t1, mcountinhibit, zero
# uimm12
csrrs t2, 0x320, zero
# mhpmevent3 # mhpmevent3
# name # name
# CHECK-INST: csrrs t1, mhpmevent3, zero # CHECK-INST: csrrs t1, mhpmevent3, zero
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x32] # CHECK-ENC: encoding: [0x73,0x23,0x30,0x32]
# CHECK-INST-ALIAS: csrr t1, mhpmevent3 # CHECK-INST-ALIAS: csrr t1, mhpmevent3
# uimm12 # uimm12
# CHECK-INST: csrrs t2, mhpmevent3, zero # CHECK-INST: csrrs t2, mhpmevent3, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x32] # CHECK-ENC: encoding: [0xf3,0x23,0x30,0x32]
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