[LLDB] Send SVE vg register in custom expedited registerset

[omjavaid]

Summary

This patch ovverides GetExpeditedRegisterSet for NativeRegisterContextLinux_arm64 to send vector granule register in expedited register set if SVE mode is selected.

[omjavaid]

This revision updated after rebase.

[omjavaid]

@labath ping!

[omjavaid]

Updated after changes to parent rev D82853

[labath]

This looks good, though it would be nice to add a test for it. It looks like TestGdbRemoteExpeditedRegisters.py has a lot of functionality that could be reused for this purpose.

[omjavaid]

Added test case for vg testing.

[labath]

lldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py

185 ↗

(On Diff #288941)

"must be available" ?

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

Status WriteRegister(const RegisterInfo *reg_info,
                        const RegisterValue &reg_value) override;
 
   Status ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override;
 
   Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
 
   void InvalidateAllRegisters() override;
 
+  std::vector<uint32_t>
+  GetExpeditedRegisters(ExpeditedRegs expType) const override;
+
   // Hardware breakpoints/watchpoint management functions
 
   uint32_t NumSupportedHardwareBreakpoints() override;
 
   uint32_t SetHardwareBreakpoint(lldb::addr_t addr, size_t size) override;
 
   bool ClearHardwareBreakpoint(uint32_t hw_idx) override;
 

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

 
 void *NativeRegisterContextLinux_arm64::GetSVEBuffer() {
   if (m_sve_state == SVEState::FPSIMD)
     return m_sve_ptrace_payload.data() + SVE_PT_FPSIMD_OFFSET;
 
   return m_sve_ptrace_payload.data();
 }
 
+std::vector<uint32_t> NativeRegisterContextLinux_arm64::GetExpeditedRegisters(
+    ExpeditedRegs expType) const {
+  std::vector<uint32_t> expedited_reg_nums =
+      NativeRegisterContext::GetExpeditedRegisters(expType);
+  if (m_sve_state == SVEState::FPSIMD || m_sve_state == SVEState::Full)
+    expedited_reg_nums.push_back(GetRegisterInfo().GetRegNumSVEVG());
+
+  return expedited_reg_nums;
+}
+
 #endif // defined (__arm64__) || defined (__aarch64__)

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

public:
   bool IsSVEZReg(unsigned reg) const;
   bool IsSVEPReg(unsigned reg) const;
   bool IsSVERegVG(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
+  uint32_t GetRegNumSVEVG() const;
 
 private:
   typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
       per_vq_register_infos;
 
   per_vq_register_infos m_per_vq_reg_infos;
 
   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
 
   const lldb_private::RegisterInfo *m_register_info_p;
   uint32_t m_register_info_count;
 };
 
 #endif

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
+
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }