[LLDB] Send SVE vg register in custom expedited registerset

[omjavaid]

Summary

This patch ovverides GetExpeditedRegisterSet for NativeRegisterContextLinux_arm64 to send vector granule register in expedited register set if SVE mode is selected.

[omjavaid]

This revision updated after rebase.

[omjavaid]

@labath ping!

[omjavaid]

Updated after changes to parent rev D82853

[labath]

This looks good, though it would be nice to add a test for it. It looks like TestGdbRemoteExpeditedRegisters.py has a lot of functionality that could be reused for this purpose.

[omjavaid]

Added test case for vg testing.

[labath]

lldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py

185 ↗

(On Diff #288941)

"must be available" ?

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

Status WriteRegister(const RegisterInfo *reg_info,
                        const RegisterValue &reg_value) override;
 
   Status ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override;
 
   Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
 
   void InvalidateAllRegisters() override;
 
+  const RegisterSet *GetExpeditedRegisterSet() const override;
+
   // Hardware breakpoints/watchpoint management functions
 
   uint32_t NumSupportedHardwareBreakpoints() override;
 
   uint32_t SetHardwareBreakpoint(lldb::addr_t addr, size_t size) override;
 
   bool ClearHardwareBreakpoint(uint32_t hw_idx) override;
 
private:
 
   RegisterInfoPOSIX_arm64::FPU
       m_fpr; // floating-point registers including extended register sets.
 
   SVEState m_sve_state;
   struct user_sve_header m_sve_header;
   std::vector<uint8_t> m_sve_ptrace_payload;
 
+  RegisterSet m_expedited_reg_set;
+  std::vector<uint32_t> m_expedited_reg_nums;
+
   // Debug register info for hardware breakpoints and watchpoints management.
   struct DREG {
     lldb::addr_t address;  // Breakpoint/watchpoint address value.
     lldb::addr_t hit_addr; // Address at which last watchpoint trigger exception
                            // occurred.
     lldb::addr_t real_addr; // Address value that should cause target to stop.
     uint32_t control;       // Breakpoint/watchpoint control value.
     uint32_t refcount;      // Serves as enable/disable and reference counter.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

void NativeRegisterContextLinux_arm64::ConfigureRegisterContext() {
   // Read SVE configuration data and configure register infos.
   if (!m_sve_header_is_valid && m_sve_state != SVEState::Disabled) {
     Status error = ReadSVEHeader();
     if (!error.Success() && m_sve_state == SVEState::Unknown) {
       m_sve_state = SVEState::Disabled;
       GetRegisterInfo().ConfigureVectorRegisterInfos(
           RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64);
     } else {
+      // Setup expedited register set if not done already.
+      if (m_sve_state == SVEState::Unknown) {
+        const uint32_t *reg_list_set0 =
+            GetRegisterInfo().GetRegisterSet(0)->registers;
+        const size_t reg_count_set0 =
+            GetRegisterInfo().GetRegisterSet(0)->num_registers;
+
+        m_expedited_reg_nums = std::vector<uint32_t>(
+            reg_list_set0, reg_list_set0 + reg_count_set0);
+        m_expedited_reg_nums.push_back(GetRegisterInfo().GetRegNumSVEVG());
+        m_expedited_reg_set = {"Expedited Registers", "expedited",
+                               m_expedited_reg_nums.size(),
+                               m_expedited_reg_nums.data()};
+      }
       if ((m_sve_header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD)
         m_sve_state = SVEState::FPSIMD;
       else if ((m_sve_header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE)
         m_sve_state = SVEState::Full;
 
       uint32_t vq = RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64SVE;
       if (sve_vl_valid(m_sve_header.vl))
         vq = sve_vq_from_vl(m_sve_header.vl);
sve_reg_offset =
         SVE_SIG_REGS_OFFSET + reg_info->byte_offset - sve_z0_offset;
   }
   return sve_reg_offset;
 }
 
 void *NativeRegisterContextLinux_arm64::GetSVEBuffer() {
   if (m_sve_state == SVEState::FPSIMD)
     return m_sve_ptrace_payload.data() + SVE_PT_FPSIMD_OFFSET;
-
   return m_sve_ptrace_payload.data();
 }
 
+const RegisterSet *
+NativeRegisterContextLinux_arm64::GetExpeditedRegisterSet() const {
+  if (m_sve_state == SVEState::FPSIMD || m_sve_state == SVEState::Full)
+    &m_expedited_reg_set;
+  return GetRegisterInfo().GetRegisterSet(0);
+}
+
 #endif // defined (__arm64__) || defined (__aarch64__)

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

public:
   bool IsSVEZReg(unsigned reg) const;
   bool IsSVEPReg(unsigned reg) const;
   bool IsSVERegVG(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
+  uint32_t GetRegNumSVEVG() const;
 
 private:
   typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
       per_vq_register_infos;
 
   per_vq_register_infos m_per_vq_reg_infos;
 
   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
 
   const lldb_private::RegisterInfo *m_register_info_p;
   uint32_t m_register_info_count;
 };
 
 #endif

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
+
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }