[CodeGen] Matching promoted type for 16-bit integer bitcasts from fp16 operand

[pratlucas]

Summary

When legalizing a biscast operation from an fp16 operand to an i16 on a
target that requires both input and output types to be promoted to
32-bits, an assertion can fail when building the new node due to a
mismatch between the the operation's result size and the type specified to
the node.

This patches fix the issue by making sure the bit width of the types
match for the FP_TO_FP16 node, covering the difference with an extra
ANYEXTEND operation.

[efriedma]

If you look at PromoteIntRes_FP_TO_FP16, it just widens the result type. I'm not sure why it isn't okay to do the same thing here; is there some interaction here I'm missing?

[pratlucas]

The issue happens when creating the ISD::FP_TO_FP16 in case the input is a constant.
It tries to generate the new 16-bit constant but the NOutVT type passed to DAG.getNode has 32-bits, which causes the assertion in SelectionDAG.cpp:1307 to fail:

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1307: llvm::SDValue llvm::SelectionDAG::getConstant(const llvm::ConstantInt &, const llvm::SDLoc &, llvm::EVT, bool, bool): Assertion `Elt->getBitWidth() == EltVT.getSizeInBits() && "APInt size does not match type size!"' failed.

[efriedma]

In that case, please fix SelectionDAG::getNode.

[plotfi]

Is there anything blocking progress?

[efriedma]

I'm waiting for my latest comment to be addressed.

[plotfi]

Ping?

[pratlucas]

Moving fix to SelectionDAG::getNode.

[plotfi]

llvm/test/CodeGen/ARM/arm-half-promote.ll

5

Spelling?

31

Spelling?

[plotfi]

Ping?

[pratlucas]

Fixing typos.

[plotfi]

@efriedma Does this seem right to you?

[efriedma]

LGTM

[plotfi]

@pratlucas gentle ping

[plotfi]

@pratlucas Awesome thank you!

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::BITCAST:
         return getConstant(V.bitcastToAPInt().getZExtValue(), DL, VT);
       break;
     case ISD::FP_TO_FP16: {
       bool Ignored;
       // This can return overflow, underflow, or inexact; we don't care.
       // FIXME need to be more flexible about rounding mode.
       (void)V.convert(APFloat::IEEEhalf(),
                       APFloat::rmNearestTiesToEven, &Ignored);
-      return getConstant(V.bitcastToAPInt(), DL, VT);
+      return getConstant(V.bitcastToAPInt().getZExtValue(), DL, VT);
     }
     }
   }
 
   // Constant fold unary operations with a vector integer or float operand.
   if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Operand)) {
     if (BV->isConstant()) {
       switch (Opcode) {

llvm/test/CodeGen/ARM/arm-half-promote.ll

+; RUN: llc < %s -mtriple=thumbv7s-apple-ios7.0.0 | FileCheck %s
+
+define arm_aapcs_vfpcc { <8 x half>, <8 x half> } @f1() {
+; CHECK-LABEL: _f1
+; CHECK: vpush   {d8}
+; CHECK-NEXT: vmov.f64        d8, #5.000000e-01
+; CHECK-NEXT: vmov.i32        d8, #0x0
+; CHECK-NEXT: vmov.i32        d0, #0x0
+; CHECK-NEXT: vmov.i32        d1, #0x0
+; CHECK-NEXT: vmov.i32        d2, #0x0
+; CHECK-NEXT: vmov.i32        d3, #0x0
+; CHECK-NEXT: vmov.i32        d4, #0x0
+; CHECK-NEXT: vmov.i32        d5, #0x0
+; CHECK-NEXT: vmov.i32        d6, #0x0
+; CHECK-NEXT: vmov.i32        d7, #0x0
+; CHECK-NEXT: vmov.f32        s1, s16
+; CHECK-NEXT: vmov.f32        s3, s16
+; CHECK-NEXT: vmov.f32        s5, s16
+; CHECK-NEXT: vmov.f32        s7, s16
+; CHECK-NEXT: vmov.f32        s9, s16
+; CHECK-NEXT: vmov.f32        s11, s16
+; CHECK-NEXT: vmov.f32        s13, s16
+; CHECK-NEXT: vmov.f32        s15, s16
+; CHECK-NEXT: vpop    {d8}
+; CHECK-NEXT: bx      lr
+  ret { <8 x half>, <8 x half> } zeroinitializer
+}
+
+define swiftcc { <8 x half>, <8 x half> } @f2() {
+; CHECK-LABEL: _f2
+; CHECK: vpush   {d8}
+; CHECK-NEXT: vmov.f64        d8, #5.000000e-01
+; CHECK-NEXT: vmov.i32        d8, #0x0
+; CHECK-NEXT: vmov.i32        d0, #0x0
+; CHECK-NEXT: vmov.i32        d1, #0x0
+; CHECK-NEXT: vmov.i32        d2, #0x0
+; CHECK-NEXT: vmov.i32        d3, #0x0
+; CHECK-NEXT: vmov.i32        d4, #0x0
+; CHECK-NEXT: vmov.i32        d5, #0x0
+; CHECK-NEXT: vmov.i32        d6, #0x0
+; CHECK-NEXT: vmov.i32        d7, #0x0
+; CHECK-NEXT: vmov.f32        s1, s16
+; CHECK-NEXT: vmov.f32        s3, s16
+; CHECK-NEXT: vmov.f32        s5, s16
+; CHECK-NEXT: vmov.f32        s7, s16
+; CHECK-NEXT: vmov.f32        s9, s16
+; CHECK-NEXT: vmov.f32        s11, s16
+; CHECK-NEXT: vmov.f32        s13, s16
+; CHECK-NEXT: vmov.f32        s15, s16
+; CHECK-NEXT: vpop    {d8}
+; CHECK-NEXT: bx      lr
+  ret { <8 x half>, <8 x half> } zeroinitializer
+}