[AMDGPU] Fix DPP Combiner:

[vpykhtin]

Summary

1. skip multiple per instruction DPP register usage.
2. don't combine when DPP register is used as part of superreg/supersubreg.

I had to refactor the code to fix the first issue, so that the check for
multiple uses of DPP register can be done for all uses. In the process
I discovered that the combiner can try to combine DPP registers that
are part of superreg (REG_SEQUENCE) and aren't used as independent lanes.

execMayBeModifiedBeforeAnyUse is now called once for all uses. Number of
uses is constrained by the caller.

I removed code patching REG_SEQUENCE but instead stopped deleting original
DPP mov instruction, it will be deleted in the DCE.

[arsenm]

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

364

Usually for an output small vector, you pass SmallVectorImpl<Type>& rather than needing a template parameter for the size

365

Independ looks like a weird abbrevation to me. Shorten to Indep or lengthen to Independent?

367

Should cast to const SIRegisterInfo

370

It's weird to limit this based on the size of the small vector. It might make sense to add a maximum use to check, but disconnected from the vector size

382

Same as previous function

407

Why is this an rvalue reference? I also don't see why this needs to be a template

410–416

Why does this need to be a separate function? Can't you determine this over the initial use walk in collectRegUse?

504

s/much/many and end with newline

581

Typo orphane

[vpykhtin]

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

364

This is the way to pass the constraint on Uses. Initially the constraint was performed by execMayBeModifiedBeforeAnyUse but it's a bit late there. The constraint was introduced to reduce compile time so its of the same nature as a preallocation for Uses array and has similar value, so I decied to join them. Actually I don't need SmallVector here, but I haven't found vector with fixed size.

410–416

There're two places where Uses are collected: collectRegUse and collectIndependSubRegUse - I would need to add this code twice. Number of uses is limited to be small and the walk is cheap.

[arsenm]

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

410–416

You could early exit out of the whole search if you check up front, it's not really duplication there

[vpykhtin]

Rebased, per review issues fixed:

1. Use separate value to constrain use count
2. Check multiple DPP operand during use collection
3. Misc

[foad]

1. skip multiple per instruction DPP register usage.
2. don't combine when DPP register is used as part of superreg/supersubreg.

I had to refactor the code to fix the first issue,

Would it make sense to split this patch into two or three? Refactoring, fix bug 1, fix bug 2?

[vpykhtin]

In D82451#2113831, @foad wrote:

1. skip multiple per instruction DPP register usage.
2. don't combine when DPP register is used as part of superreg/supersubreg.

I had to refactor the code to fix the first issue,

Would it make sense to split this patch into two or three? Refactoring, fix bug 1, fix bug 2?

Yes, if there're no other objections.

[vpykhtin]

split to parts

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/Pass.h"
 #include <cassert>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "gcn-dpp-combine"
 
+static const unsigned DefaultMaxDPPRegUses = 16;
+
+static cl::opt<unsigned> MaxDPPRegUses(
+    "dpp-combine-max-reg-uses", cl::init(DefaultMaxDPPRegUses), cl::Hidden,
+    cl::desc("Maximum number of uses for a DPP register to combine"));
+
 STATISTIC(NumDPPMovsCombined, "Number of DPP moves combined.");
 
 namespace {
 
+using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
+
 class GCNDPPCombine : public MachineFunctionPass {
   MachineRegisterInfo *MRI;
   const SIInstrInfo *TII;
 
-  using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
-
   MachineOperand *getOldOpndValue(MachineOperand &OldOpnd) const;
 
   MachineInstr *createDPPInst(MachineInstr &OrigMI,
                               MachineInstr &MovMI,
                               RegSubRegPair CombOldVGPR,
                               MachineOperand *OldOpnd,
                               bool CombBCZ) const;
 
bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, unsigned OpndName,
   auto *Imm = TII->getNamedOperand(MI, OpndName);
   if (!Imm)
     return true;
 
   assert(Imm->isImm());
   return (Imm->getImm() & Mask) == Value;
 }
 
+static bool addUse(MachineOperand *Use,
+                   SmallVectorImpl<MachineOperand *> &Uses) {
+  if (Uses.size() == MaxDPPRegUses) {
+    LLVM_DEBUG(dbgs() << "  " << *Use->getParent() << "  failed: exceeded the "
+                                                      "maximum number of uses "
+                                                      "for a DPP register\n");
+    return false;
+  }
+
+  // Assuming per instruction uses come together,
+  // see defusechain_iterator::operator++
+  if (!Uses.empty() && Uses.back()->getParent() == Use->getParent()) {
+    LLVM_DEBUG(
+        dbgs()
+        << "  " << *Use->getParent()
+        << "  failed: DPP register is used more than once per instruction\n");
+    return false;
+  }
+
+  Uses.push_back(Use);
+  return true;
+}
+
+// Store uses of RSR, checking that RSR.SubReg is used as independent lane
+// (i.e not as part of the whole reg or other subreg)
+static bool collectIndepSubRegUse(MachineRegisterInfo &MRI, RegSubRegPair RSR,
+                                  SmallVectorImpl<MachineOperand *> &Uses) {
+  const auto &TRI =
+      *static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
+  LaneBitmask Mask = TRI.getSubRegIndexLaneMask(RSR.SubReg);
+  for (auto &Op : MRI.use_nodbg_operands(RSR.Reg)) {
+    if (Op.getSubReg() == RSR.SubReg) {
+      if (!addUse(&Op, Uses))
+        return false;
+    } else if (!Op.getSubReg() ||
+               (Mask & TRI.getSubRegIndexLaneMask(Op.getSubReg())).any())
+      return false;
+  }
+  return true;
+}
+
+static bool collectRegUse(MachineRegisterInfo &MRI, Register R,
+                          SmallVectorImpl<MachineOperand *> &Uses) {
+  for (auto &Use : MRI.use_nodbg_operands(R)) {
+    auto &MI = *Use.getParent();
+    switch (MI.getOpcode()) {
+    case AMDGPU::REG_SEQUENCE: {
+      unsigned OpNo = MI.getOperandNo(&Use);
+      assert(OpNo > 0 && "Use cannot be a destination register");
+      auto RSR = RegSubRegPair(MI.getOperand(0).getReg(),
+                               MI.getOperand(OpNo + 1).getImm());
+      if (!collectIndepSubRegUse(MRI, RSR, Uses))
+        return false;
+      break;
+    }
+    // TODO: add INSERT_SUBREG?
+    default:
+      if (!addUse(&Use, Uses))
+        return false;
+    }
+  }
+  return true;
+}
+
 bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
   assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
   LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
 
   auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
   assert(DstOpnd && DstOpnd->isReg());
   auto DPPMovReg = DstOpnd->getReg();
   if (DPPMovReg.isPhysical()) {
     LLVM_DEBUG(dbgs() << "  failed: dpp move writes physreg\n");
     return false;
   }
-  if (execMayBeModifiedBeforeAnyUse(*MRI, DPPMovReg, MovMI)) {
-    LLVM_DEBUG(dbgs() << "  failed: EXEC mask should remain the same"
-                         " for all uses\n");
-    return false;
-  }
 
   auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);
   assert(RowMaskOpnd && RowMaskOpnd->isImm());
   auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);
   assert(BankMaskOpnd && BankMaskOpnd->isImm());
   const bool MaskAllLanes = RowMaskOpnd->getImm() == 0xF &&
                             BankMaskOpnd->getImm() == 0xF;
 
bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
 
   LLVM_DEBUG(dbgs() << "  old=";
     if (!OldOpndValue)
       dbgs() << "undef";
     else
       dbgs() << *OldOpndValue;
     dbgs() << ", bound_ctrl=" << CombBCZ << '\n');
 
+  SmallVector<MachineOperand *, DefaultMaxDPPRegUses> Uses;
+  if (!collectRegUse(*MRI, DPPMovReg, Uses))
+    return false;
+
+  if (execMayBeModifiedBeforeAnyUse(*MRI, MovMI, Uses)) {
+    LLVM_DEBUG(
+        dbgs() << "  failed: EXEC mask should remain the same for all uses\n");
+    return false;
+  }
+
   SmallVector<MachineInstr*, 4> OrigMIs, DPPMIs;
-  DenseMap<MachineInstr*, SmallVector<unsigned, 4>> RegSeqWithOpNos;
   auto CombOldVGPR = getRegSubRegPair(*OldOpnd);
   // try to reuse previous old reg if its undefined (IMPLICIT_DEF)
   if (CombBCZ && OldOpndValue) { // CombOldVGPR should be undef
     CombOldVGPR = RegSubRegPair(
       MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass));
     auto UndefInst = BuildMI(*MovMI.getParent(), MovMI, MovMI.getDebugLoc(),
                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);
     DPPMIs.push_back(UndefInst.getInstr());
   }
 
-  OrigMIs.push_back(&MovMI);
   bool Rollback = true;
-  SmallVector<MachineOperand*, 16> Uses;
-
-  for (auto &Use : MRI->use_nodbg_operands(DPPMovReg)) {
-    Uses.push_back(&Use);
-  }
-
   while (!Uses.empty()) {
     MachineOperand *Use = Uses.pop_back_val();
     Rollback = true;
 
     auto &OrigMI = *Use->getParent();
     LLVM_DEBUG(dbgs() << "  try: " << OrigMI);
-
     auto OrigOp = OrigMI.getOpcode();
-    if (OrigOp == AMDGPU::REG_SEQUENCE) {
-      Register FwdReg = OrigMI.getOperand(0).getReg();
-      unsigned FwdSubReg = 0;
-
-      if (execMayBeModifiedBeforeAnyUse(*MRI, FwdReg, OrigMI)) {
-        LLVM_DEBUG(dbgs() << "  failed: EXEC mask should remain the same"
-                             " for all uses\n");
-        break;
-      }
-
-      unsigned OpNo, E = OrigMI.getNumOperands();
-      for (OpNo = 1; OpNo < E; OpNo += 2) {
-        if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) {
-          FwdSubReg = OrigMI.getOperand(OpNo + 1).getImm();
-          break;
-        }
-      }
-
-      if (!FwdSubReg)
-        break;
-
-      for (auto &Op : MRI->use_nodbg_operands(FwdReg)) {
-        if (Op.getSubReg() == FwdSubReg)
-          Uses.push_back(&Op);
-      }
-      RegSeqWithOpNos[&OrigMI].push_back(OpNo);
-      continue;
-    }
 
     if (TII->isVOP3(OrigOp)) {
       if (!TII->hasVALU32BitEncoding(OrigOp)) {
         LLVM_DEBUG(dbgs() << "  failed: VOP3 hasn't e32 equivalent\n");
         break;
       }
       // check if other than abs|neg modifiers are set (opsel for example)
       const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG);
if (Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)) {
       LLVM_DEBUG(dbgs() << "  failed: no suitable operands\n");
     if (Rollback)
       break;
     OrigMIs.push_back(&OrigMI);
   }
 
   Rollback |= !Uses.empty();
 
-  for (auto *MI : *(Rollback? &DPPMIs : &OrigMIs))
-    MI->eraseFromParent();
-
+  // Don't delete the original dpp mov instruction because it may still be
+  // used by a REG_SEQUENCE(potentialy orphaned) producing invalid MIR. It will
+  // soon be deleted by the DCE.
   if (!Rollback) {
-    for (auto &S : RegSeqWithOpNos) {
-      if (MRI->use_nodbg_empty(S.first->getOperand(0).getReg())) {
-        S.first->eraseFromParent();
-        continue;
-      }
-      while (!S.second.empty())
-        S.first->getOperand(S.second.pop_back_val()).setIsUndef(true);
-    }
+    auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
+    Src0->setIsKill(false);
   }
 
+  for (auto *MI : *(Rollback ? &DPPMIs : &OrigMIs))
+    MI->eraseFromParent();
+
   return !Rollback;
 }
 
 bool GCNDPPCombine::runOnMachineFunction(MachineFunction &MF) {
   auto &ST = MF.getSubtarget<GCNSubtarget>();
   if (!ST.hasDPP() || skipFunction(MF.getFunction()))
     return false;
 

llvm/lib/Target/AMDGPU/SIInstrInfo.h

 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file

 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
 /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
 /// attempt to track between blocks.
 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
                                 Register VReg,
                                 const MachineInstr &DefMI,
                                 const MachineInstr &UseMI);
 
-/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
-/// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
-/// track between blocks.
-bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
-                                   Register VReg,
-                                   const MachineInstr &DefMI);
+/// \brief Return false if EXEC is not changed between the \p DefMI and all its
+/// \p Uses. Should be run on SSA. Currently does not attempt to track between
+/// blocks.
+bool execMayBeModifiedBeforeAnyUse(
+    const MachineRegisterInfo &MRI, MachineInstr &DefMI,
+    const SmallVectorImpl<MachineOperand*> &Uses);
 
 namespace AMDGPU {
 
   LLVM_READONLY
   int getVOPe64(uint16_t Opcode);
 
   LLVM_READONLY
   int getVOPe32(uint16_t Opcode);

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

 //===- SIInstrInfo.cpp - SI Instruction Information  ----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
for (auto I = std::next(DefMI.getIterator()); I != E; ++I) {
 
     if (I->modifiesRegister(AMDGPU::EXEC, TRI))
       return true;
   }
 
   return false;
 }
 
-bool llvm::execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
-                                         Register VReg,
-                                         const MachineInstr &DefMI) {
+bool llvm::execMayBeModifiedBeforeAnyUse(
+    const MachineRegisterInfo &MRI, MachineInstr &DefMI,
+    const SmallVectorImpl<MachineOperand*> &Uses) {
   assert(MRI.isSSA() && "Must be run on SSA");
+  const auto &TRI = *MRI.getTargetRegisterInfo();
 
-  auto *TRI = MRI.getTargetRegisterInfo();
-  auto *DefBB = DefMI.getParent();
-
-  const int MaxUseInstScan = 10;
-  int NumUseInst = 0;
-
-  for (auto &UseInst : MRI.use_nodbg_instructions(VReg)) {
-    // Don't bother searching between blocks, although it is possible this block
-    // doesn't modify exec.
-    if (UseInst.getParent() != DefBB)
+  for (const auto &Use : Uses)
+    if (Use->getParent()->getParent() != DefMI.getParent())
       return true;
 
-    if (++NumUseInst > MaxUseInstScan)
-      return true;
-  }
+  DenseSet<MachineInstr*> Users;
+  for (const auto &Use : Uses)
+    Users.insert(Use->getParent());
 
   const int MaxInstScan = 20;
   int NumInst = 0;
 
   // Stop scan when we have seen all the uses.
   for (auto I = std::next(DefMI.getIterator()); ; ++I) {
+    assert(I != DefMI.getParent()->end());
     if (I->isDebugInstr())
       continue;
 
+    Users.erase(&*I);
+    if (Users.empty())
+      break;
+
     if (++NumInst > MaxInstScan)
       return true;
 
-    if (I->readsRegister(VReg))
-      if (--NumUseInst == 0)
-        return false;
-
-    if (I->modifiesRegister(AMDGPU::EXEC, TRI))
+    if (I->modifiesRegister(AMDGPU::EXEC, &TRI))
       return true;
   }
+  return false;
 }
 
 MachineInstr *SIInstrInfo::createPHIDestinationCopy(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt,
     const DebugLoc &DL, Register Src, Register Dst) const {
   auto Cur = MBB.begin();
   if (Cur != MBB.end())
     do {

llvm/test/CodeGen/AMDGPU/dpp_combine.mir

bb.0:
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_first_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
 # GCN: %8:vgpr_32 = IMPLICIT_DEF
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
 # GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
-# GCN: %5:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, %4, %subreg.sub1
+# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
 # GCN: %6:vgpr_32 = V_ADD_I32_dpp %8, %1.sub0, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_first_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
     %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
     %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %6:vgpr_32 = V_ADD_I32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_second_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
 # GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
 # GCN: %8:vgpr_32 = IMPLICIT_DEF
-# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, undef %4:vgpr_32, %subreg.sub1
+# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
 # GCN: %6:vgpr_32 = V_ADD_I32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_second_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 

 body: |
   bb.0:
     %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
     %5:vgpr_32 = V_ADD_I32_e32 %2.sub0, undef %4:vgpr_32, implicit-def $vcc, implicit $exec
     %6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp64_add64_first_combined
+# GCN: %7:vgpr_32 = V_MOV_B32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, 1, 15, 15, 1, implicit $exec
 # GCN: %8:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64, undef %2.sub1:vreg_64, 1, 15, 15, 1, implicit $exec
-# GCN: %0:vreg_64 = REG_SEQUENCE undef %7:vgpr_32, %subreg.sub0, %8, %subreg.sub1
+# GCN: %0:vreg_64 = REG_SEQUENCE %7, %subreg.sub0, %8, %subreg.sub1
 # GCN: %3:vgpr_32 = V_ADD_I32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
 # GCN: %5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %0.sub1, undef $vcc, 0, implicit $exec
 name: dpp64_add64_first_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_I32_e32 %2.sub0, undef %3:vgpr_32, implicit-def $vcc, implicit $exec
bb.0:
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
     %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = nofpexcept nnan V_ADD_F32_e64 0, %3, 0, %0, 0, 0, implicit $mode, implicit $exec
     S_ENDPGM 0, implicit %4
 
 ...
+
+# GCN-LABEL: name: dont_combine_more_than_one_operand
+# GCN: %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
+name: dont_combine_more_than_one_operand
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vgpr_32 = COPY $vgpr1
+    %2:vgpr_32 = V_MOV_B32_dpp %0, %1, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
+...
+
+# GCN-LABEL: name: dont_combine_more_than_one_operand_dpp_reg_sequence
+# GCN: %5:vgpr_32 = V_ADD_I32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec
+# GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
+name: dont_combine_more_than_one_operand_dpp_reg_sequence
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    %0:vreg_64 = COPY $vgpr0_vgpr1
+    %1:vreg_64 = COPY $vgpr2_vgpr3
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
+    %5:vgpr_32 = V_ADD_I32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec
+    %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
+...
+
+# GCN-LABEL: name: dont_combine_dpp_reg_sequence_wholereg_used
+# GCN: %6:vgpr_32 = V_ADD_I32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
+# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
+name: dont_combine_dpp_reg_sequence_wholereg_used
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    %0:vreg_64 = COPY $vgpr0_vgpr1
+    %1:vreg_64 = COPY $vgpr2_vgpr3
+    %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
+    %6:vgpr_32 = V_ADD_I32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
+    %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
+    S_NOP 1, implicit %5
+...
+
+# GCN-LABEL: name: dpp_reg_sequence_use_supersubreg_for_second
+# GCN: %8:vgpr_32 = IMPLICIT_DEF
+# GCN: %6:vgpr_32 = V_ADD_I32_dpp %8, %1.sub0, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
+# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub2, %2, implicit-def $vcc, implicit $vcc, implicit $exec
+name: dpp_reg_sequence_use_supersubreg_for_second
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    %0:vreg_64 = COPY $vgpr0_vgpr1
+    %1:vreg_64 = COPY $vgpr2_vgpr3
+    %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %5:vreg_128 = REG_SEQUENCE %3, %subreg.sub0, %2, %subreg.sub1, %4, %subreg.sub2, %2, %subreg.sub3
+    %6:vgpr_32 = V_ADD_I32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
+    %7:vgpr_32 = V_ADDC_U32_e32 %5.sub2, %2, implicit-def $vcc, implicit $vcc, implicit $exec
+    S_NOP 1, implicit %5.sub2_sub3
+...