[Power10] Implement Vector Replace Builtins in LLVM/Clang

[biplmish]

Summary

This patch implements builtins for the following prototypes:

vector signed int vec_replace_elt (vector signed int, signed int, const int);
vector unsigned int vec_replace_elt (vector unsigned int, unsigned int, const int);
vector float vec_replace_elt (vector float, float, const int);
vector signed long long vec_replace_elt (vector signed long long, signed long long, const int);
vector unsigned long long vec_replace_elt (vector unsigned long long, unsigned long long, const int);
vector double rec_replace_elt (vector double, double, const int);

vector unsigned char vec_replace_unaligned (vector unsigned char, signed int, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, unsigned int, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, float, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, signed long long, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, unsigned long long, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, double, const int);

[lei]

clang/lib/Headers/altivec.h

16869

Nit: It would be good if we can keep the indentation for these definitions consistent.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

458

nit: // P10 Vector Insert with immediate.
Please end all sentences with a .
Space after //

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

414

nit: missing .

927

nit: indentation.

929

indentation.

[amyk]

clang/include/clang/Basic/BuiltinsPPC.def

315

End with a period.

clang/lib/Headers/altivec.h

16870

Nit: Space after the comment of the name.

[steven.zhang]

clang/lib/Headers/altivec.h

16875

I see that the value range for __c is 0, 3. Could you add some semantic check in frontend about this?

[biplmish]

clang/lib/Headers/altivec.h

16875

Yes value of __c should actually be 0.3 for 32 bit type and 0,1 for 64bit type. Also this is converted to a byte index as input to builtin as specified. So a range check for builtin input would be 0-12 for 32 bit type and 0-8 for 64 bit type.

[biplmish]

Review comments incorporated.

[steven.zhang]

clang/lib/Sema/SemaChecking.cpp

3127 ↗

(On Diff #272984)

Please add the diagnose message tests.

[biplmish]

Update the builtin implementation to incorporate instruction changes.

[lei]

This patch doesn't contain full context. Please regenerate with -U999999.

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

532

No need for this, please use default and remove the CHECK-LE run line as it's the same as the default run line.

[biplmish]

Updating the patch with latest code and modification to the redundant test case run.

[lei]

clang/lib/Headers/altivec.h

17037

This looks just like a cast to unsigned int, can you explain why it needs to be cast to a union to extract the unsigned int instead of just directly casting it to an unsigned int?

17044

nit: remove extra empty line.

clang/test/CodeGen/builtins-ppc-p10vector.c

523

I don't see why you have 2 different CHECK prefix for the same run line. Seems redundant to me. Please update to just use CHECK.

[biplmish]

clang/lib/Headers/altivec.h

17037

The intrinsic implements the input2 argument as i64. When the input to the function is of type float/double it generates fptoui which can modify the user input value.
Cast to union is done to preserve the float value and the same reaches the hw instruction.

[biplmish]

Modify the clang test to remove the redundant CHECK-LE's.

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

10

Should not remove this since there are tests in here that depends on this this check prefix.

[biplmish]

Add the CHECK-LE run because there are dependent tests.

[biplmish]

This patch will be implemented as 2 separate patches for LLVM and CLANG respectively.

clang/include/clang/Basic/BuiltinsPPC.def

 
 // P10 Vector Gather Every N-th Bit built-in.
 BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "")
 
 // P10 Vector Clear Bytes built-ins.
 BUILTIN(__builtin_altivec_vclrlb, "V16cV16cUi", "")
 BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "")
 
 // P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins.
 BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Shift built-ins.
 BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "")
 BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "")
 
 // P10 Vector Insert built-ins.
 BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcULLiULLi", "")
 BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcULLiULLi", "")
 BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsULLiULLi", "")
 BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsULLiULLi", "")
 BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiULLiULLi", "")
 BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiULLiULLi", "")
 BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "")
 BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "")
 BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcULLiV16Uc", "")
 BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcULLiV16Uc", "")
 BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsULLiV8Us", "")
 BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsULLiV8Us", "")
 BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiULLiV4Ui", "")
 BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiULLiV4Ui", "")
 
+// P10 Vector insert with immediate built-ins.
+BUILTIN(__builtin_altivec_vinsw, "V4UiV4UiULLiIi", "")
+BUILTIN(__builtin_altivec_vinsd, "V2ULLiV2ULLiULLiIi", "")
+
 // VSX built-ins.
 
 BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
 BUILTIN(__builtin_vsx_lxvw4x, "V4iivC*", "")
 BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "")
 BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "")
 
 BUILTIN(__builtin_vsx_stxvd2x, "vV2div*", "")

clang/lib/Headers/altivec.h

 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_clrr(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb((vector signed char)__a, __n);
 #else
   return __builtin_altivec_vclrrb((vector signed char)__a, __n);
 #endif
 }
 
 /* vec_cntlzm */
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_cntlzm(vector unsigned long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vclzdm(__a, __b);
 }
 
 /* vec_cnttzm */
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_cnttzm(vector unsigned long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vctzdm(__a, __b);
 }
 
vec_inserth(vector unsigned int __a, vector unsigned int __b,
             unsigned int __c) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vinswvlx(__b, __c, __a);
 #else
   return __builtin_altivec_vinswvrx(__b, __c, __a);
 #endif
 }
 
+/* vec_replace_elt */
+
+#define F2L(x)                                                                 \
+  ((union {                                                                    \
+    float f;                                                                   \
+    unsigned int ui;                                                           \
+  })(x))                                                                       \
+      .ui
+#define DP2LL(x)                                                               \
+  ((union {                                                                    \
+    double d;                                                                  \
+    unsigned long long ull;                                                    \
+  })(x))                                                                       \
+      .ull
+
+#ifdef __LITTLE_ENDIAN__
+#define vec_replace_elt(__a, __b, __c)                                         \
+  _Generic((__b), signed int                                                   \
+           : (vector signed int)__builtin_altivec_vinsw(                       \
+                 __a, (signed int)(__b), (12 - ((__c)*4))),                    \
+             unsigned int                                                      \
+           : (vector unsigned int)__builtin_altivec_vinsw(                     \
+                 __a, (unsigned int)(__b), (12 - ((__c)*4))),                  \
+             float                                                             \
+           : (vector float)__builtin_altivec_vinsw(__a, F2L((float)(__b)),     \
+                                                   (12 - ((__c)*4))),          \
+             signed long long                                                  \
+           : (vector signed long long)__builtin_altivec_vinsd(                 \
+                 __a, (signed long long)(__b), (8 - ((__c)*8))),               \
+             unsigned long long                                                \
+           : (vector unsigned long long)__builtin_altivec_vinsd(               \
+                 __a, (unsigned long long)(__b), (8 - ((__c)*8))),             \
+             double                                                            \
+           : (vector double)__builtin_altivec_vinsd(__a, DP2LL((double)(__b)), \
+                                                    (8 - ((__c)*8))))
+#else
+#define vec_replace_elt(__a, __b, __c)                                         \
+  _Generic((__b), signed int                                                   \
+           : (vector signed int)__builtin_altivec_vinsw(                       \
+                 __a, (signed int)(__b), ((__c)*4)),                           \
+             unsigned int                                                      \
+           : (vector unsigned int)__builtin_altivec_vinsw(                     \
+                 __a, (unsigned int)(__b), ((__c)*4)),                         \
+             float                                                             \
+           : (vector float)__builtin_altivec_vinsw(__a, F2L((float)(__b)),     \
+                                                   ((__c)*4)),                 \
+             signed long long                                                  \
+           : (vector signed long long)__builtin_altivec_vinsd(                 \
+                 __a, (signed long long)(__b), ((__c)*8)),                     \
+             unsigned long long                                                \
+           : (vector unsigned long long)__builtin_altivec_vinsd(               \
+                 __a, (unsigned long long)(__b), ((__c)*8)),                   \
+             double                                                            \
+           : (vector double)__builtin_altivec_vinsd(__a, DP2LL((double)(__b)), \
+                                                    ((__c)*8)))
+#endif
+
+/* vec_replace_unaligned */
+
+#ifdef __LITTLE_ENDIAN__
+#define vec_replace_unaligned(__a, __b, __c)                                   \
+  _Generic((__b), signed int                                                   \
+           : (vector unsigned char)__builtin_altivec_vinsw(                    \
+                 __a, (signed int)(__b), (12 - (__c))),                        \
+             unsigned int                                                      \
+           : (vector unsigned char)__builtin_altivec_vinsw(                    \
+                 __a, (unsigned int)(__b), (12 - (__c))),                      \
+             float                                                             \
+           : (vector unsigned char)__builtin_altivec_vinsw(                    \
+                 __a, F2L((float)(__b)), (12 - (__c))),                        \
+             signed long long                                                  \
+           : (vector unsigned char)__builtin_altivec_vinsd(                    \
+                 __a, (signed long long)(__b), (8 - (__c))),                   \
+             unsigned long long                                                \
+           : (vector unsigned char)__builtin_altivec_vinsd(                    \
+                 __a, (unsigned long long)(__b), (8 - (__c))),                 \
+             double                                                            \
+           : (vector unsigned char)__builtin_altivec_vinsd(                    \
+               __a, DP2LL((double)(__b)), (8 - (__c))))
+#else
+#define vec_replace_unaligned(__a, __b, __c)                                   \
+  _Generic((__b), signed int                                                   \
+           : (vector unsigned char)__builtin_altivec_vinsw(                    \
+                 __a, (signed int)(__b), (__c)),                               \
+             unsigned int                                                      \
+           : (vector unsigned char)__builtin_altivec_vinsw(                    \
+                 __a, (unsigned int)(__b), (__c)),                             \
+             float                                                             \
+           : (vector unsigned char)__builtin_altivec_vinsw(                    \
+                 __a, F2L((float)(__b)), (__c)),                               \
+             signed long long                                                  \
+           : (vector unsigned char)__builtin_altivec_vinsd(                    \
+                 __a, (signed long long)(__b), (__c)),                         \
+             unsigned long long                                                \
+           : (vector unsigned char)__builtin_altivec_vinsd(                    \
+                 __a, (unsigned long long)(__b), (__c)),                       \
+             double                                                            \
+           : (vector unsigned char)__builtin_altivec_vinsd(                    \
+               __a, DP2LL((double)(__b)), (__c)))
+#endif
+
 #ifdef __VSX__
 
 /* vec_permx */
 
 #define vec_permx(__a, __b, __c, __d)                                          \
   __builtin_vsx_xxpermx((__a), (__b), (__c), (__d))
 
 /* vec_blendv */

clang/test/CodeGen/builtins-ppc-p10vector.c

 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
 // RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s
 
 // RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
 // RUN:   -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s -check-prefix=CHECK-BE
 
 // RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
 // RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s -check-prefix=CHECK-LE
 
 #include <altivec.h>
 
 vector signed char vsca, vscb;
 vector unsigned char vuca, vucb, vucc;
 vector signed short vssa, vssb;
 vector unsigned short vusa, vusb, vusc;
 vector signed int vsia, vsib;
 vector unsigned int vuia, vuib, vuic;
 vector signed long long vslla, vsllb;
 vector unsigned long long vulla, vullb, vullc;
 vector unsigned __int128 vui128a, vui128b, vui128c;
 vector float vfa, vfb;
 vector double vda, vdb;
 unsigned int uia, uib;
 unsigned char uca;
 unsigned short usa;
 unsigned long long ulla;
+signed int sia;
+signed long long slla;
+float fa;
+double da;
 
 vector unsigned long long test_vpdepd(void) {
   // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_pdep(vulla, vullb);
 }
 
 vector unsigned long long test_vpextd(void) {

 
 vector unsigned int test_vec_inserth_uiv(void) {
   // CHECK-BE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
   // CHECK-BE-NEXT: ret <4 x i32>
   // CHECK-LE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
   // CHECK-LE-NEXT: ret <4 x i32>
   return vec_inserth(vuia, vuib, uia);
 }
+
+vector signed int test_vec_replace_elt_si(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 0
+  // CHECK-BE-NEXT: ret <4 x i32>
+  // CHECK: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 12
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_replace_elt(vsia, sia, 0);
+}
+
+vector unsigned int test_vec_replace_elt_ui(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 4
+  // CHECK-BE-NEXT: ret <4 x i32>
+  // CHECK: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 8
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_replace_elt(vuia, uia, 1);
+}
+
+vector float test_vec_replace_elt_f(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 8
+  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float>
+  // CHECK-BE-NEXT: ret <4 x float>
+  // CHECK: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 4
+  // CHECK-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float>
+  // CHECK-NEXT: ret <4 x float>
+  return vec_replace_elt(vfa, fa, 2);
+}
+
+vector signed long long test_vec_replace_elt_sll(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
+  // CHECK-BE-NEXT: ret <2 x i64>
+  // CHECK: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_replace_elt(vslla, slla, 0);
+}
+
+vector unsigned long long test_vec_replace_elt_ull(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
+  // CHECK-BE-NEXT: ret <2 x i64>
+  // CHECK: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_replace_elt(vulla, ulla, 0);
+}
+
+vector double test_vec_replace_elt_d(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
+  // CHECK-BE: bitcast <2 x i64> %{{.*}} to <2 x double>
+  // CHECK-BE-NEXT: ret <2 x double>
+  // CHECK: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
+  // CHECK: bitcast <2 x i64> %{{.*}} to <2 x double>
+  // CHECK-NEXT: ret <2 x double>
+  return vec_replace_elt(vda, da, 1);
+}
+
+vector unsigned char test_vec_replace_unaligned_si(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 6
+  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 6
+  // CHECK-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vsia, sia, 6);
+}
+
+vector unsigned char test_vec_replace_unaligned_ui(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 8
+  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 4
+  // CHECK-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vuia, uia, 8);
+}
+
+vector unsigned char test_vec_replace_unaligned_f(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 12
+  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 0
+  // CHECK-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vfa, fa, 12);
+}
+
+vector unsigned char test_vec_replace_unaligned_sll(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 6
+  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 2
+  // CHECK-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vslla, slla, 6);
+}
+
+vector unsigned char test_vec_replace_unaligned_ull(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 7
+  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 1
+  // CHECK-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vulla, ulla, 7);
+}
+
+vector unsigned char test_vec_replace_unaligned_d(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
+  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
+  // CHECK-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vda, da, 8);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
    // P10 Vector Clear Bytes
    def int_ppc_altivec_vclrlb :  GCCBuiltin<"__builtin_altivec_vclrlb">,
                Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
                          [IntrNoMem]>;
    def int_ppc_altivec_vclrrb :  GCCBuiltin<"__builtin_altivec_vclrrb">,
                Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
                          [IntrNoMem]>;
 
   // P10 Vector Shift Double Bit Immediate.
   def int_ppc_altivec_vsldbi : GCCBuiltin<"__builtin_altivec_vsldbi">,
               Intrinsic<[llvm_v16i8_ty],
                         [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
                         [IntrNoMem, ImmArg<ArgIndex<2>>]>;
   def int_ppc_altivec_vsrdbi : GCCBuiltin<"__builtin_altivec_vsrdbi">,
               Intrinsic<[llvm_v16i8_ty],
                         [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
                         [IntrNoMem, ImmArg<ArgIndex<2>>]>;
def int_ppc_altivec_vinshvrx : GCCBuiltin<"__builtin_altivec_vinshvrx">,
   def int_ppc_altivec_vinswvlx : GCCBuiltin<"__builtin_altivec_vinswvlx">,
               Intrinsic<[llvm_v4i32_ty],
                         [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
                         [IntrNoMem]>;
   def int_ppc_altivec_vinswvrx : GCCBuiltin<"__builtin_altivec_vinswvrx">,
               Intrinsic<[llvm_v4i32_ty],
                         [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
                         [IntrNoMem]>;
+
+  // P10 Vector Insert with immediate.
+  def int_ppc_altivec_vinsw : GCCBuiltin<"__builtin_altivec_vinsw">,
+              Intrinsic<[llvm_v4i32_ty],
+                        [llvm_v4i32_ty, llvm_i64_ty, llvm_i32_ty],
+                        [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+  def int_ppc_altivec_vinsd : GCCBuiltin<"__builtin_altivec_vinsd">,
+              Intrinsic<[llvm_v2i64_ty],
+                        [llvm_v2i64_ty, llvm_i64_ty, llvm_i32_ty],
+                        [IntrNoMem, ImmArg<ArgIndex<2>>]>;
 }
 
 // Vector average.
 def int_ppc_altivec_vavgsb : PowerPC_Vec_BBB_Intrinsic<"vavgsb">;
 def int_ppc_altivec_vavgsh : PowerPC_Vec_HHH_Intrinsic<"vavgsh">;
 def int_ppc_altivec_vavgsw : PowerPC_Vec_WWW_Intrinsic<"vavgsw">;
 def int_ppc_altivec_vavgub : PowerPC_Vec_BBB_Intrinsic<"vavgub">;
 def int_ppc_altivec_vavguh : PowerPC_Vec_HHH_Intrinsic<"vavguh">;

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL,
                                       !strconcat(asmstr, ", 0"), itin, []>;
   def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
                                     !strconcat(asmstr, ", 1"), itin, []>,
                                     isPCRel;
 }
 
 def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
 def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
 
 let Predicates = [PrefixInstrs] in {
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
     defm PADDI8 :
       MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
                               (ins immZero:$RA, s34imm:$SI),
                               "paddi $RT, $RA, $SI", IIC_LdStLFD>;
     let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
       def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
let Predicates = [IsISA3_1] in {
   def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
                                 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
                                 "vsrdbi $VRT, $VRA, $VRB, $SH",
                                 IIC_VecGeneral,
                                 [(set v16i8:$VRT,
                                       (int_ppc_altivec_vsrdbi v16i8:$VRA,
                                                               v16i8:$VRB, 
                                                               i32:$SH))]>;
-  def VINSW : VXForm_VRT5_UIM5_RB5_ins<207, "vinsw", []>;
-  def VINSD : VXForm_VRT5_UIM5_RB5_ins<463, "vinsd", []>;
+  def VINSW : 
+    VXForm_VRT5_UIM5_RB5_ins<207, "vinsw",
+                             [(set v4i32:$vD,
+                                   (int_ppc_altivec_vinsw v4i32:$vDi, i64:$rB,
+                                                          timm:$UIM))]>;
+  def VINSD :
+    VXForm_VRT5_UIM5_RB5_ins<463, "vinsd",
+                             [(set v2i64:$vD,
+                                   (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB,
+                                                          timm:$UIM))]>;
   def VINSBVLX :
     VXForm_VTB5_RA5_ins<15, "vinsbvlx",
-                        [(set v16i8:$vD,
-                              (int_ppc_altivec_vinsbvlx v16i8:$vDi, i64:$rA,
-                                                        v16i8:$vB))]>;
   def VINSBVRX :
     VXForm_VTB5_RA5_ins<271, "vinsbvrx",
-                        [(set v16i8:$vD,
-                              (int_ppc_altivec_vinsbvrx v16i8:$vDi, i64:$rA,
-                                                        v16i8:$vB))]>;
   def VINSHVLX :
     VXForm_VTB5_RA5_ins<79, "vinshvlx",
                         [(set v8i16:$vD,
                               (int_ppc_altivec_vinshvlx v8i16:$vDi, i64:$rA,
                                                         v8i16:$vB))]>;
   def VINSHVRX :
     VXForm_VTB5_RA5_ins<335, "vinshvrx",
                         [(set v8i16:$vD,
def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
                          "vclrlb $vD, $vA, $rB", IIC_VecGeneral,
                          [(set v16i8:$vD,
                                (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
    def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
                          "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
                          [(set v16i8:$vD,
                                (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
 }
 
 //---------------------------- Anonymous Patterns ----------------------------//
 let Predicates = [IsISA3_1] in {
   def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
             (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)),
             (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),
             (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
             (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;

llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinswvrx v2, r5, v3
 ; CHECK-NEXT:    blr
 entry:
   %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32> %a, i64 %b, <4 x i32> %c)
   ret <4 x i32> %0
 }
 declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>)
+
+define <4 x i32> @testVINSW(<4 x i32> %a, i64 %b) {
+; CHECK-LABEL: testVINSW:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsw v2, r5, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i64 %b, i32 1)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i64, i32 immarg)
+
+define <2 x i64> @testVINSD(<2 x i64> %a, i64 %b) {
+; CHECK-LABEL: testVINSD:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsd v2, r5, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> %a, i64 %b, i32 1)
+  ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64>, i64, i32 immarg)