[Power10] Implement Vector Replace Builtins in LLVM/Clang

[biplmish]

Summary

This patch implements builtins for the following prototypes:

vector signed int vec_replace_elt (vector signed int, signed int, const int);
vector unsigned int vec_replace_elt (vector unsigned int, unsigned int, const int);
vector float vec_replace_elt (vector float, float, const int);
vector signed long long vec_replace_elt (vector signed long long, signed long long, const int);
vector unsigned long long vec_replace_elt (vector unsigned long long, unsigned long long, const int);
vector double rec_replace_elt (vector double, double, const int);

vector unsigned char vec_replace_unaligned (vector unsigned char, signed int, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, unsigned int, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, float, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, signed long long, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, unsigned long long, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, double, const int);

[lei]

clang/lib/Headers/altivec.h

16833

Nit: It would be good if we can keep the indentation for these definitions consistent.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

429

nit: // P10 Vector Insert with immediate.
Please end all sentences with a .
Space after //

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

211

nit: missing .

579

nit: indentation.

581

indentation.

[amyk]

clang/include/clang/Basic/BuiltinsPPC.def

309

End with a period.

clang/lib/Headers/altivec.h

16834

Nit: Space after the comment of the name.

[steven.zhang]

clang/lib/Headers/altivec.h

16839

I see that the value range for __c is 0, 3. Could you add some semantic check in frontend about this?

[biplmish]

clang/lib/Headers/altivec.h

16839

Yes value of __c should actually be 0.3 for 32 bit type and 0,1 for 64bit type. Also this is converted to a byte index as input to builtin as specified. So a range check for builtin input would be 0-12 for 32 bit type and 0-8 for 64 bit type.

[biplmish]

Review comments incorporated.

[steven.zhang]

clang/lib/Sema/SemaChecking.cpp

3127

Please add the diagnose message tests.

[biplmish]

Update the builtin implementation to incorporate instruction changes.

[lei]

This patch doesn't contain full context. Please regenerate with -U999999.

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

532

No need for this, please use default and remove the CHECK-LE run line as it's the same as the default run line.

[biplmish]

Updating the patch with latest code and modification to the redundant test case run.

[lei]

clang/lib/Headers/altivec.h

16840

This looks just like a cast to unsigned int, can you explain why it needs to be cast to a union to extract the unsigned int instead of just directly casting it to an unsigned int?

16847

nit: remove extra empty line.

clang/test/CodeGen/builtins-ppc-p10vector.c

103

I don't see why you have 2 different CHECK prefix for the same run line. Seems redundant to me. Please update to just use CHECK.

[biplmish]

clang/lib/Headers/altivec.h

16840

The intrinsic implements the input2 argument as i64. When the input to the function is of type float/double it generates fptoui which can modify the user input value.
Cast to union is done to preserve the float value and the same reaches the hw instruction.

[biplmish]

Modify the clang test to remove the redundant CHECK-LE's.

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

5–6

Should not remove this since there are tests in here that depends on this this check prefix.

[biplmish]

Add the CHECK-LE run because there are dependent tests.

[biplmish]

This patch will be implemented as 2 separate patches for LLVM and CLANG respectively.

clang/include/clang/Basic/BuiltinsPPC.def

 // P10 Vector Parallel Bits built-ins.
 BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Clear Bytes built-ins.
 BUILTIN(__builtin_altivec_vclrlb, "V16cV16cUi", "")
 BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "")
 
+// P10 Vector insert with immediate built-ins.
+BUILTIN(__builtin_altivec_vinsw, "V4UiULLiIi", "")
+BUILTIN(__builtin_altivec_vinsd, "V2ULLiULLiIi", "")
+
 // VSX built-ins.
 
 BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
 BUILTIN(__builtin_vsx_lxvw4x, "V4iivC*", "")
 BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "")
 BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "")
 
 BUILTIN(__builtin_vsx_stxvd2x, "vV2div*", "")

clang/lib/Headers/altivec.h

 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_clrr(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb((vector signed char)__a, __n);
 #else
   return __builtin_altivec_vclrrb((vector signed char)__a, __n);
 #endif
 }
+
+/* vec_replace */
+
+#ifdef __LITTLE_ENDIAN__
+#define vec_replace_elt(__a, __b, __c)                                         \
+  _Generic(                                                                    \
+      (__b), signed int                                                        \
+      : (vector signed int)__builtin_altivec_vinsw((signed int)(__b),          \
+                                                   (12 - ((__c)*4))),          \
+        unsigned int                                                           \
+      : (vector unsigned int)__builtin_altivec_vinsw((unsigned int)(__b),      \
+                                                     (12 - ((__c)*4))),        \
+        float                                                                  \
+      : (vector float)__builtin_altivec_vinsw((float)(__b), (12 - ((__c)*4))), \
+        signed long long                                                       \
+      : (vector signed long long)__builtin_altivec_vinsd(                      \
+            (signed long long)(__b), (8 - ((__c)*8))),                         \
+        unsigned long long                                                     \
+      : (vector unsigned long long)__builtin_altivec_vinsd(                    \
+            (unsigned long long)(__b), (8 - ((__c)*8))),                       \
+        double                                                                 \
+      : (vector double)__builtin_altivec_vinsd((double)(__b),                  \
+                                               (8 - ((__c)*8))))
+
+#define vec_replace_unaligned(__a, __b, __c)                                   \
+  _Generic((__b), signed int                                                   \
+           : (vector unsigned char)__builtin_altivec_vinsw((signed int)(__b),  \
+                                                           (12 - (__c))),      \
+             unsigned int                                                      \
+           : (vector unsigned char)__builtin_altivec_vinsw(                    \
+                 (unsigned int)(__b), (12 - (__c))),                           \
+             float                                                             \
+           : (vector unsigned char)__builtin_altivec_vinsw((float)(__b),       \
+                                                           (12 - (__c))),      \
+             signed long long                                                  \
+           : (vector unsigned char)__builtin_altivec_vinsd(                    \
+                 (signed long long)(__b), (8 - (__c))),                        \
+             unsigned long long                                                \
+           : (vector unsigned char)__builtin_altivec_vinsd(                    \
+                 (unsigned long long)(__b), (8 - (__c))),                      \
+             double                                                            \
+           : (vector unsigned char)__builtin_altivec_vinsd((double)(__b),      \
+                                                           (8 - (__c))))
+
+#else
+#define vec_replace_elt(__a, __b, __c)                                         \
+  _Generic((__b), signed int                                                   \
+           : (vector signed int)__builtin_altivec_vinsw((signed int)(__b),     \
+                                                        ((__c)*4)),            \
+             unsigned int                                                      \
+           : (vector unsigned int)__builtin_altivec_vinsw((unsigned int)(__b), \
+                                                          ((__c)*4)),          \
+             float                                                             \
+           : (vector float)__builtin_altivec_vinsw((float)(__b), ((__c)*4)),   \
+             signed long long                                                  \
+           : (vector signed long long)__builtin_altivec_vinsd(                 \
+                 (signed long long)(__b), ((__c)*8)),                          \
+             unsigned long long                                                \
+           : (vector unsigned long long)__builtin_altivec_vinsd(               \
+                 (unsigned long long)(__b), ((__c)*8)),                        \
+             double                                                            \
+           : (vector double)__builtin_altivec_vinsd((double)(__b), ((__c)*8)))
+
+#define vec_replace_unaligned(__a, __b, __c)                                   \
+  _Generic(                                                                    \
+      (__b), signed int                                                        \
+      : (vector unsigned char)__builtin_altivec_vinsw((signed int)(__b),       \
+                                                      (__c)),                  \
+        unsigned int                                                           \
+      : (vector unsigned char)__builtin_altivec_vinsw((unsigned int)(__b),     \
+                                                      (__c)),                  \
+        float                                                                  \
+      : (vector unsigned char)__builtin_altivec_vinsw((float)(__b), (__c)),    \
+        signed long long                                                       \
+      : (vector unsigned char)__builtin_altivec_vinsd((signed long long)(__b), \
+                                                      (__c)),                  \
+        unsigned long long                                                     \
+      : (vector unsigned char)__builtin_altivec_vinsd(                         \
+            (unsigned long long)(__b), (__c)),                                 \
+        double                                                                 \
+      : (vector unsigned char)__builtin_altivec_vinsd((double)(__b), (__c)))
+#endif
 #endif /* __POWER10_VECTOR__ */
 
 #undef __ATTRS_o_ai
 
 #endif /* __ALTIVEC_H */

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case PPC::BI__builtin_vsx_xxpermdi:
   case PPC::BI__builtin_vsx_xxsldwi:
     return SemaBuiltinVSX(TheCall);
   case PPC::BI__builtin_unpack_vector_int128:
     return SemaVSXCheck(TheCall) ||
            SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
   case PPC::BI__builtin_pack_vector_int128:
     return SemaVSXCheck(TheCall);
+  case PPC::BI__builtin_altivec_vinsw:
+     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 12);
+  case PPC::BI__builtin_altivec_vinsd:
+     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 8);
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);
 }
 
 bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID,
                                           CallExpr *TheCall) {
   // position of memory order and scope arguments in the builtin
   unsigned OrderIndex, ScopeIndex;

clang/test/CodeGen/builtins-ppc-p10vector.c

 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
 // RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s
 
+// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
+// RUN:   -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -o - | FileCheck %s -check-prefix=CHECK-BE
+
+// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
+// RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -o - | FileCheck %s -check-prefix=CHECK-LE
+
 #include <altivec.h>
 
 vector signed char vsca;
 vector unsigned char vuca;
 vector unsigned short vusa;
 vector unsigned int vuia;
 vector unsigned long long vulla, vullb;
+vector signed int vsia;
+vector float vfa;
+vector signed long long vslla;
+vector double vda;
 unsigned int uia;
+signed int sia;
+float fa;
+signed long long slla;
+unsigned long long ulla;
+double da;
 
 vector unsigned long long test_vpdepd(void) {
   // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_pdep(vulla, vullb);
 }
 
 vector unsigned long long test_vpextd(void) {

 
 vector unsigned char test_vec_clrr_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
   return vec_clrr(vuca, uia);
 }
+
+vector signed int test_vec_replace_elt_si(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: ret <4 x i32>
+  // CHECK-LE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: ret <4 x i32>
+  return vec_replace_elt(vsia, sia, 0);
+}
+
+vector unsigned int test_vec_replace_elt_ui(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: ret <4 x i32>
+  // CHECK-LE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: ret <4 x i32>
+  return vec_replace_elt(vuia, uia, 0);
+}
+
+vector float test_vec_replace_elt_f(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float>
+  // CHECK-BE-NEXT: ret <4 x float>
+  // CHECK-LE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float>
+  // CHECK-LE-NEXT: ret <4 x float>
+  return vec_replace_elt(vfa, fa, 0);
+}
+
+vector signed long long test_vec_replace_elt_sll(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: ret <2 x i64>
+  // CHECK-LE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: ret <2 x i64>
+  return vec_replace_elt(vslla, slla, 0);
+}
+
+vector unsigned long long test_vec_replace_elt_ull(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: ret <2 x i64>
+  // CHECK-LE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: ret <2 x i64>
+  return vec_replace_elt(vulla, ulla, 0);
+}
+
+vector double test_vec_replace_elt_d(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-BE: bitcast <2 x i64> %{{.*}} to <2 x double>
+  // CHECK-BE-NEXT: ret <2 x double>
+  // CHECK-LE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-LE: bitcast <2 x i64> %{{.*}} to <2 x double>
+  // CHECK-LE-NEXT: ret <2 x double>
+  return vec_replace_elt(vda, da, 0);
+}
+
+vector unsigned char test_vec_replace_unaligned_si(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vsia, sia, 0);
+}
+
+vector unsigned char test_vec_replace_unaligned_ui(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vuia, uia, 0);
+}
+
+vector unsigned char test_vec_replace_unaligned_f(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsw(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vfa, fa, 0);
+}
+
+vector unsigned char test_vec_replace_unaligned_sll(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vslla, slla, 0);
+}
+
+vector unsigned char test_vec_replace_unaligned_ull(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vulla, ulla, 0);
+}
+
+vector unsigned char test_vec_replace_unaligned_d(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsd(i64 %{{.+}}, i32
+  // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_replace_unaligned(vda, da, 0);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
 
    // P10 Vector Clear Bytes
    def int_ppc_altivec_vclrlb :  GCCBuiltin<"__builtin_altivec_vclrlb">,
                Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
                          [IntrNoMem]>;
    def int_ppc_altivec_vclrrb :  GCCBuiltin<"__builtin_altivec_vclrrb">,
                Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
                          [IntrNoMem]>;
+
+  // P10 Vector Insert with immediate.
+  def int_ppc_altivec_vinsw : GCCBuiltin<"__builtin_altivec_vinsw">,
+              Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_i32_ty],
+                        [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+  def int_ppc_altivec_vinsd : GCCBuiltin<"__builtin_altivec_vinsd">,
+              Intrinsic<[llvm_v2i64_ty], [llvm_i64_ty, llvm_i32_ty],
+                        [IntrNoMem, ImmArg<ArgIndex<1>>]>;
 }
 
 // Vector average.
 def int_ppc_altivec_vavgsb : PowerPC_Vec_BBB_Intrinsic<"vavgsb">;
 def int_ppc_altivec_vavgsh : PowerPC_Vec_HHH_Intrinsic<"vavgsh">;
 def int_ppc_altivec_vavgsw : PowerPC_Vec_WWW_Intrinsic<"vavgsw">;
 def int_ppc_altivec_vavgub : PowerPC_Vec_BBB_Intrinsic<"vavgub">;
 def int_ppc_altivec_vavguh : PowerPC_Vec_HHH_Intrinsic<"vavguh">;

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
                                       InstrItinClass itin> {
   def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL,
                                       !strconcat(asmstr, ", 0"), itin, []>;
   def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
                                     !strconcat(asmstr, ", 1"), itin, []>,
                                     isPCRel;
 }
 
+// VX-Form: [PO VRT / UIM RB XO]. 
+// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
+// "/ UIM" (unused bit followed by a 4-bit immediate).
+class VX_VRT5_UIM5_RB5<bits<11> xo, string opc, list<dag> pattern>
+  : VXForm_1<xo, (outs vrrc:$VRT), (ins u4imm:$UIM, g8rc:$RB),
+             !strconcat(opc, " $VRT, $RB, $UIM"), IIC_VecGeneral, pattern>;
+
+class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL, 
+                        string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> RD;
+  bits<5> VB;
+  bit MP;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RD;
+  let Inst{11-14} = eo;
+  let Inst{15} = MP;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
+
 def PrefixInstrs : Predicate<"PPCSubTarget->hasPrefixInstrs()">;
 def IsISA3_1 : Predicate<"PPCSubTarget->isISA3_1()">;
 
 let Predicates = [PrefixInstrs] in {
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
     defm PADDI8 :
       MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
                               (ins immZero:$RA, s34imm:$SI),
let Predicates = [IsISA3_1] in {
    def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
                          "vclrlb $vD, $vA, $rB", IIC_VecGeneral,
                          [(set v16i8:$vD,
                                (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
    def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
                          "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
                          [(set v16i8:$vD,
                                (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+   def VINSW : VX_VRT5_UIM5_RB5<207, "vinsw", [(set v4i32:$VRT, (int_ppc_altivec_vinsw
+                         i64:$RB, timm:$UIM))]>;
+   def VINSD : VX_VRT5_UIM5_RB5<463, "vinsd", [(set v2i64:$VRT, (int_ppc_altivec_vinsd
+                         i64:$RB, timm:$UIM))]>;
 }
 
 //---------------------------- Anonymous Patterns ----------------------------//
 let Predicates = [IsISA3_1] in {
   def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
             (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)),
             (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),
             (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
             (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
 }

llvm/test/CodeGen/PowerPC/p10-permute-ops.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN:   -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN:   -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
+
+define <4 x i32> @testVINSW(i64 %a) {
+; CHECK-LABEL: testVINSW:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsw v2, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(i64 %a, i32 1)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinsw(i64, i32 immarg)
+
+define <2 x i64> @testVINSD(i64 %a) {
+; CHECK-LABEL: testVINSD:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsd v2, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsd(i64 %a, i32 1)
+  ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.altivec.vinsd(i64, i32 immarg)

llvm/test/MC/Disassembler/PowerPC/p10insts.txt

 # CHECK xxgenpcvdm 0, 1, 2
 0xf0 0x02 0x0f 0x6a
 
 # CHECK: vclrlb 1, 4, 3
 0x10 0x24 0x19 0x8d
 
 # CHECK: vclrrb 1, 4, 3
 0x10 0x24 0x19 0xcd
+
+# CHECK: vinsw 2, 3, 12
+0x10 0x4c 0x18 0xcf
+
+# CHECK: vinsd 2, 3, 12
+0x10 0x4c 0x19 0xcf

llvm/test/MC/PowerPC/p10.s

 # CHECK-LE: xxgenpcvdm 0, 1, 2                    # encoding: [0x6a,0x0f,0x02,0xf0]
             xxgenpcvdm 0, 1, 2
 # CHECK-BE: vclrlb 1, 4, 3                        # encoding: [0x10,0x24,0x19,0x8d]
 # CHECK-LE: vclrlb 1, 4, 3                        # encoding: [0x8d,0x19,0x24,0x10]
             vclrlb 1, 4, 3
 # CHECK-BE: vclrrb 1, 4, 3                        # encoding: [0x10,0x24,0x19,0xcd]
 # CHECK-LE: vclrrb 1, 4, 3                        # encoding: [0xcd,0x19,0x24,0x10]
             vclrrb 1, 4, 3
+# CHECK-BE: vinsw 2, 3, 12                  # encoding: [0x10,0x4c,0x18,0xcf]
+# CHECK-LE: vinsw 2, 3, 12                  # encoding: [0xcf,0x18,0x4c,0x10]
+            vinsw 2, 3, 12
+# CHECK-BE: vinsd 2, 3, 12                  # encoding: [0x10,0x4c,0x19,0xcf]
+# CHECK-LE: vinsd 2, 3, 12                  # encoding: [0xcf,0x19,0x4c,0x10]
+            vinsd 2, 3, 12