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Differential D82359

[Power10] Implement Vector Replace Builtins in LLVM/Clang
AbandonedPublic

Authored by biplmish on Jun 23 2020, 1:25 AM.

Details

Reviewers
amyk
nemanjai
steven.zhang
lei
Group Reviewers
Restricted Project
Summary

This patch implements builtins for the following prototypes:

vector signed int vec_replace_elt (vector signed int, signed int, const int);
vector unsigned int vec_replace_elt (vector unsigned int, unsigned int, const int);
vector float vec_replace_elt (vector float, float, const int);
vector signed long long vec_replace_elt (vector signed long long, signed long long, const int);
vector unsigned long long vec_replace_elt (vector unsigned long long, unsigned long long, const int);
vector double rec_replace_elt (vector double, double, const int);

vector unsigned char vec_replace_unaligned (vector unsigned char, signed int, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, unsigned int, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, float, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, signed long long, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, unsigned long long, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, double, const int);

Diff Detail

Event Timeline

biplmish created this revision.Jun 23 2020, 1:25 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 23 2020, 1:25 AM
Herald added subscribers: • wuzish, kbarton, hiraditya. · View Herald Transcript
lei added a subscriber: lei.Jun 23 2020, 7:57 AM
lei added inline comments.
clang/lib/Headers/altivec.h
16833

Nit: It would be good if we can keep the indentation for these definitions consistent.

llvm/include/llvm/IR/IntrinsicsPowerPC.td
429

nit: // P10 Vector Insert with immediate.
Please end all sentences with a .
Space after //

llvm/lib/Target/PowerPC/PPCInstrPrefix.td
211

nit: missing .

579

nit: indentation.

581

indentation.

amyk added inline comments.Jun 23 2020, 8:34 AM
clang/include/clang/Basic/BuiltinsPPC.def
309

End with a period.

clang/lib/Headers/altivec.h
16834

Nit: Space after the comment of the name.

steven.zhang added inline comments.Jun 23 2020, 5:58 PM
clang/lib/Headers/altivec.h
16839

I see that the value range for __c is 0, 3. Could you add some semantic check in frontend about this?

biplmish marked an inline comment as done.Jun 23 2020, 11:53 PM
biplmish added inline comments.
clang/lib/Headers/altivec.h
16839

Yes value of __c should actually be 0.3 for 32 bit type and 0,1 for 64bit type. Also this is converted to a byte index as input to builtin as specified. So a range check for builtin input would be 0-12 for 32 bit type and 0-8 for 64 bit type.

biplmish updated this revision to Diff 272984.Jun 24 2020, 5:00 AM

Review comments incorporated.

steven.zhang added inline comments.Jun 28 2020, 9:35 PM
clang/lib/Sema/SemaChecking.cpp
3127 ↗(On Diff #272984)

Please add the diagnose message tests.

biplmish updated this revision to Diff 275368.Jul 3 2020, 5:22 AM

Update the builtin implementation to incorporate instruction changes.

biplmish added a parent revision: D82365: [Power10] Implement Vector Insert Builtins in LLVM/Clang.Jul 3 2020, 5:22 AM
lei requested changes to this revision.Jul 3 2020, 2:05 PM

This patch doesn't contain full context. Please regenerate with -U999999.

This revision now requires changes to proceed.Jul 3 2020, 2:05 PM
lei added inline comments.Jul 3 2020, 3:12 PM
clang/test/CodeGen/builtins-ppc-p10vector.c
532

No need for this, please use default and remove the CHECK-LE run line as it's the same as the default run line.

biplmish updated this revision to Diff 275491.Jul 4 2020, 3:01 AM

Updating the patch with latest code and modification to the redundant test case run.

lei added inline comments.Jul 6 2020, 6:38 AM
clang/lib/Headers/altivec.h
17037

This looks just like a cast to unsigned int, can you explain why it needs to be cast to a union to extract the unsigned int instead of just directly casting it to an unsigned int?

17044

nit: remove extra empty line.

clang/test/CodeGen/builtins-ppc-p10vector.c
519

I don't see why you have 2 different CHECK prefix for the same run line. Seems redundant to me. Please update to just use CHECK.

biplmish added inline comments.Jul 6 2020, 8:15 AM
clang/lib/Headers/altivec.h
17037

The intrinsic implements the input2 argument as i64. When the input to the function is of type float/double it generates fptoui which can modify the user input value.
Cast to union is done to preserve the float value and the same reaches the hw instruction.

biplmish updated this revision to Diff 275723.Jul 6 2020, 8:17 AM

Modify the clang test to remove the redundant CHECK-LE's.

lei added inline comments.Jul 6 2020, 9:38 AM
clang/test/CodeGen/builtins-ppc-p10vector.c
10

Should not remove this since there are tests in here that depends on this this check prefix.

biplmish updated this revision to Diff 275748.Jul 6 2020, 9:56 AM

Add the CHECK-LE run because there are dependent tests.

biplmish abandoned this revision.Jul 7 2020, 7:54 AM

This patch will be implemented as 2 separate patches for LLVM and CLANG respectively.

amyk mentioned this in D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins..Aug 21 2020, 6:42 PM

Revision Contents

PathSize
clang/
include/
clang/
Basic/
4 lines
lib/
Headers/
84 lines
test/
CodeGen/
116 lines
llvm/
include/
llvm/
IR/
10 lines
lib/
Target/
PowerPC/
12 lines
test/
CodeGen/
PowerPC/
22 lines

Diff 275368

clang/include/clang/Basic/BuiltinsPPC.def

Context not available.
BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiULLiV4Ui", "") BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiULLiV4Ui", "")
BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiULLiV4Ui", "") BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiULLiV4Ui", "")
// P10 Vector insert with immediate built-ins.
BUILTIN(__builtin_altivec_vinsw, "V4UiV4UiULLiIi", "")
BUILTIN(__builtin_altivec_vinsd, "V2ULLiV2ULLiULLiIi", "")
// VSX built-ins. // VSX built-ins.
BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "") BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
Context not available.

clang/lib/Headers/altivec.h

Context not available.
#endif #endif
} }
/* vec_replace */
#ifdef __LITTLE_ENDIAN__
#define vec_replace_elt(__a, __b, __c) \
_Generic((__b), signed int \
: (vector signed int)__builtin_altivec_vinsw( \
__a, (signed int)(__b), (12 - ((__c)*4))), \
unsigned int \
: (vector unsigned int)__builtin_altivec_vinsw( \
__a, (unsigned int)(__b), (12 - ((__c)*4))), \
float \
: (vector float)__builtin_altivec_vinsw(__a, (float)(__b), \
(12 - ((__c)*4))), \
signed long long \
: (vector signed long long)__builtin_altivec_vinsd( \
__a, (signed long long)(__b), (8 - ((__c)*8))), \
leiUnsubmitted
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This looks just like a cast to unsigned int, can you explain why it needs to be cast to a union to extract the unsigned int instead of just directly casting it to an unsigned int?

lei: This looks just like a cast to `unsigned int`, can you explain why it needs to be cast to a…
biplmishAuthorUnsubmitted
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The intrinsic implements the input2 argument as i64. When the input to the function is of type float/double it generates fptoui which can modify the user input value.
Cast to union is done to preserve the float value and the same reaches the hw instruction.

biplmish: The intrinsic implements the input2 argument as i64. When the input to the function is of type…
unsigned long long \
: (vector unsigned long long)__builtin_altivec_vinsd( \
__a, (unsigned long long)(__b), (8 - ((__c)*8))), \
double \
: (vector double)__builtin_altivec_vinsd(__a, (double)(__b), \
(8 - ((__c)*8))))
leiUnsubmitted
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nit: remove extra empty line.

lei: nit: remove extra empty line.
#define vec_replace_unaligned(__a, __b, __c) \
_Generic((__b), signed int \
: (vector unsigned char)__builtin_altivec_vinsw( \
__a, (signed int)(__b), (12 - (__c))), \
unsigned int \
: (vector unsigned char)__builtin_altivec_vinsw( \
__a, (unsigned int)(__b), (12 - (__c))), \
float \
: (vector unsigned char)__builtin_altivec_vinsw(__a, (float)(__b), \
(12 - (__c))), \
signed long long \
: (vector unsigned char)__builtin_altivec_vinsd( \
__a, (signed long long)(__b), (8 - (__c))), \
unsigned long long \
: (vector unsigned char)__builtin_altivec_vinsd( \
__a, (unsigned long long)(__b), (8 - (__c))), \
double \
: (vector unsigned char)__builtin_altivec_vinsd(__a, (double)(__b), \
(8 - (__c))))
#else
#define vec_replace_elt(__a, __b, __c) \
_Generic( \
(__b), signed int \
: (vector signed int)__builtin_altivec_vinsw(__a, (signed int)(__b), \
((__c)*4)), \
unsigned int \
: (vector unsigned int)__builtin_altivec_vinsw(__a, (unsigned int)(__b), \
((__c)*4)), \
float \
: (vector float)__builtin_altivec_vinsw(__a, (float)(__b), ((__c)*4)), \
signed long long \
: (vector signed long long)__builtin_altivec_vinsd( \
__a, (signed long long)(__b), ((__c)*8)), \
unsigned long long \
: (vector unsigned long long)__builtin_altivec_vinsd( \
__a, (unsigned long long)(__b), ((__c)*8)), \
double \
: (vector double)__builtin_altivec_vinsd(__a, (double)(__b), ((__c)*8)))
#define vec_replace_unaligned(__a, __b, __c) \
_Generic((__b), signed int \
: (vector unsigned char)__builtin_altivec_vinsw( \
__a, (signed int)(__b), (__c)), \
unsigned int \
: (vector unsigned char)__builtin_altivec_vinsw( \
__a, (unsigned int)(__b), (__c)), \
float \
: (vector unsigned char)__builtin_altivec_vinsw(__a, (float)(__b), \
(__c)), \
signed long long \
: (vector unsigned char)__builtin_altivec_vinsd( \
__a, (signed long long)(__b), (__c)), \
unsigned long long \
: (vector unsigned char)__builtin_altivec_vinsd( \
__a, (unsigned long long)(__b), (__c)), \
double \
: (vector unsigned char)__builtin_altivec_vinsd(__a, (double)(__b), \
(__c)))
#endif
#ifdef __VSX__ #ifdef __VSX__
/* vec_permx */ /* vec_permx */
Context not available.

clang/test/CodeGen/builtins-ppc-p10vector.c

Context not available.
unsigned char uca; unsigned char uca;
unsigned short usa; unsigned short usa;
unsigned long long ulla; unsigned long long ulla;
signed int sia;
signed long long slla;
float fa;
double da;
vector unsigned long long test_vpdepd(void) { vector unsigned long long test_vpdepd(void) {
// CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64> // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
Context not available.
// CHECK-LE-NEXT: ret <4 x i32> // CHECK-LE-NEXT: ret <4 x i32>
return vec_inserth(vuia, vuib, uia); return vec_inserth(vuia, vuib, uia);
} }
leiUnsubmitted
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I don't see why you have 2 different CHECK prefix for the same run line. Seems redundant to me. Please update to just use CHECK.

lei: I don't see why you have 2 different CHECK prefix for the same run line. Seems redundant to me.
vector signed int test_vec_replace_elt_si(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 0
// CHECK-BE-NEXT: ret <4 x i32>
// CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 12
// CHECK-LE-NEXT: ret <4 x i32>
return vec_replace_elt(vsia, sia, 0);
}
vector unsigned int test_vec_replace_elt_ui(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 4
// CHECK-BE-NEXT: ret <4 x i32>
// CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 8
// CHECK-LE-NEXT: ret <4 x i32>
leiUnsubmitted
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No need for this, please use default and remove the CHECK-LE run line as it's the same as the default run line.

lei: No need for this, please use default and remove the CHECK-LE run line as it's the same as the…
return vec_replace_elt(vuia, uia, 1);
}
vector float test_vec_replace_elt_f(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 8
// CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float>
// CHECK-BE-NEXT: ret <4 x float>
// CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 4
// CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float>
// CHECK-LE-NEXT: ret <4 x float>
return vec_replace_elt(vfa, fa, 2);
}
vector signed long long test_vec_replace_elt_sll(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
// CHECK-BE-NEXT: ret <2 x i64>
// CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
// CHECK-LE-NEXT: ret <2 x i64>
return vec_replace_elt(vslla, slla, 0);
}
vector unsigned long long test_vec_replace_elt_ull(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
// CHECK-BE-NEXT: ret <2 x i64>
// CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
// CHECK-LE-NEXT: ret <2 x i64>
return vec_replace_elt(vulla, ulla, 0);
}
vector double test_vec_replace_elt_d(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
// CHECK-BE: bitcast <2 x i64> %{{.*}} to <2 x double>
// CHECK-BE-NEXT: ret <2 x double>
// CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
// CHECK-LE: bitcast <2 x i64> %{{.*}} to <2 x double>
// CHECK-LE-NEXT: ret <2 x double>
return vec_replace_elt(vda, da, 1);
}
vector unsigned char test_vec_replace_unaligned_si(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 6
// CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
// CHECK-BE-NEXT: ret <16 x i8>
// CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 6
// CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
// CHECK-LE-NEXT: ret <16 x i8>
return vec_replace_unaligned(vsia, sia, 6);
}
vector unsigned char test_vec_replace_unaligned_ui(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 8
// CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
// CHECK-BE-NEXT: ret <16 x i8>
// CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 4
// CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
// CHECK-LE-NEXT: ret <16 x i8>
return vec_replace_unaligned(vuia, uia, 8);
}
vector unsigned char test_vec_replace_unaligned_f(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 12
// CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
// CHECK-BE-NEXT: ret <16 x i8>
// CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i64 %{{.+}}, i32 0
// CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
// CHECK-LE-NEXT: ret <16 x i8>
return vec_replace_unaligned(vfa, fa, 12);
}
vector unsigned char test_vec_replace_unaligned_sll(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 6
// CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
// CHECK-BE-NEXT: ret <16 x i8>
// CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 2
// CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
// CHECK-LE-NEXT: ret <16 x i8>
return vec_replace_unaligned(vslla, slla, 6);
}
vector unsigned char test_vec_replace_unaligned_ull(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 7
// CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
// CHECK-BE-NEXT: ret <16 x i8>
// CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 1
// CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
// CHECK-LE-NEXT: ret <16 x i8>
return vec_replace_unaligned(vulla, ulla, 7);
}
vector unsigned char test_vec_replace_unaligned_d(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
// CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
// CHECK-BE-NEXT: ret <16 x i8>
// CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
// CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
// CHECK-LE-NEXT: ret <16 x i8>
return vec_replace_unaligned(vda, da, 8);
}
Context not available.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

Context not available.
Intrinsic<[llvm_v4i32_ty], Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
// P10 Vector Insert with immediate.
def int_ppc_altivec_vinsw : GCCBuiltin<"__builtin_altivec_vinsw">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_i64_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>]>;
def int_ppc_altivec_vinsd : GCCBuiltin<"__builtin_altivec_vinsd">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_i64_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>]>;
} }
// Vector average. // Vector average.
Context not available.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Context not available.
(int_ppc_altivec_vsrdbi v16i8:$VRA, (int_ppc_altivec_vsrdbi v16i8:$VRA,
v16i8:$VRB, v16i8:$VRB,
i32:$SH))]>; i32:$SH))]>;
def VINSW : VXForm_VRT5_UIM5_RB5_ins<207, "vinsw", []>; def VINSW :
def VINSD : VXForm_VRT5_UIM5_RB5_ins<463, "vinsd", []>; VXForm_VRT5_UIM5_RB5_ins<207, "vinsw",
[(set v4i32:$vD,
(int_ppc_altivec_vinsw v4i32:$vDi, i64:$rB,
timm:$UIM))]>;
def VINSD :
VXForm_VRT5_UIM5_RB5_ins<463, "vinsd",
[(set v2i64:$vD,
(int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB,
timm:$UIM))]>;
def VINSBVLX : def VINSBVLX :
VXForm_VTB5_RA5_ins<15, "vinsbvlx", VXForm_VTB5_RA5_ins<15, "vinsbvlx",
[(set v16i8:$vD, [(set v16i8:$vD,
Context not available.

llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll

Context not available.
ret <4 x i32> %0 ret <4 x i32> %0
} }
declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>) declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>)
define <4 x i32> @testVINSW(<4 x i32> %a, i64 %b) {
; CHECK-LABEL: testVINSW:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsw v2, r5, 1
; CHECK-NEXT: blr
entry:
%0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i64 %b, i32 1)
ret <4 x i32> %0
}
declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i64, i32 immarg)
define <2 x i64> @testVINSD(<2 x i64> %a, i64 %b) {
; CHECK-LABEL: testVINSD:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsd v2, r5, 1
; CHECK-NEXT: blr
entry:
%0 = tail call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> %a, i64 %b, i32 1)
ret <2 x i64> %0
}
declare <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64>, i64, i32 immarg)
Context not available.