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Differential D82358

[ARM] Mark more integer instructions as not having side effects.
ClosedPublic

Authored by dmgreen on Jun 23 2020, 1:19 AM.

Details

Reviewers
efriedma
samparker
SjoerdMeijer
ostannard
andreadb
Commits
rGd604cc6e9a41: [ARM] Mark more integer instructions as not having side effects.
Summary

LDRD and STRD, along with UBFX and SBFX are selected from DAGToDAG transforms, so do not have patterns. They don't get marked as having side effects so cannot be scheduled as efficiently as you would like.

Diff Detail

Event Timeline

dmgreen created this revision.Jun 23 2020, 1:19 AM
Herald added a reviewer: andreadb. · View Herald TranscriptJun 23 2020, 1:19 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: danielkiss, gbedwell, hiraditya, kristof.beyls. · View Herald Transcript
efriedma accepted this revision.Jun 23 2020, 1:11 PM

LGTM

This revision is now accepted and ready to land.Jun 23 2020, 1:11 PM
Closed by commit rGd604cc6e9a41: [ARM] Mark more integer instructions as not having side effects. (authored by dmgreen). · Explain WhyJun 23 2020, 3:06 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
12 lines
test/
CodeGen/
Thumb2/
8 lines
tools/
llvm-mca/
ARM/
12 lines

Diff 272839

llvm/lib/Target/ARM/ARMInstrThumb2.td

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} }
def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>; def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>; def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>; def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
// ldrd / strd pre / post variants // ldrd / strd pre / post variants
let mayLoad = 1 in let mayLoad = 1, hasSideEffects = 0 in
def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
(ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru, (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
"ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>, "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
Sched<[WriteLd]> { Sched<[WriteLd]> {
let DecoderMethod = "DecodeT2LDRDPreInstruction"; let DecoderMethod = "DecodeT2LDRDPreInstruction";
} }
let mayLoad = 1 in let mayLoad = 1, hasSideEffects = 0 in
def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
(ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm), (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm", IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
"$addr.base = $wb", []>, Sched<[WriteLd]>; "$addr.base = $wb", []>, Sched<[WriteLd]>;
let mayStore = 1 in let mayStore = 1, hasSideEffects = 0 in
def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb), def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
(ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr), (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!", IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
"$addr.base = $wb", []>, Sched<[WriteST]> { "$addr.base = $wb", []>, Sched<[WriteST]> {
let DecoderMethod = "DecodeT2STRDPreInstruction"; let DecoderMethod = "DecodeT2STRDPreInstruction";
} }
let mayStore = 1 in let mayStore = 1, hasSideEffects = 0 in
def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb), def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
(ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr, (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
t2am_imm8s4_offset:$imm), t2am_imm8s4_offset:$imm),
IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm", IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
"$addr.base = $wb", []>, Sched<[WriteST]>; "$addr.base = $wb", []>, Sched<[WriteST]>;
class T2Istrrel<bits<2> bit54, dag oops, dag iops, class T2Istrrel<bits<2> bit54, dag oops, dag iops,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
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def t2SBFX: T2TwoRegBitFI< def t2SBFX: T2TwoRegBitFI<
(outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> { IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 1; let Inst{25} = 1;
let Inst{24-20} = 0b10100; let Inst{24-20} = 0b10100;
let Inst{15} = 0; let Inst{15} = 0;
let hasSideEffects = 0;
} }
def t2UBFX: T2TwoRegBitFI< def t2UBFX: T2TwoRegBitFI<
(outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> { IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 1; let Inst{25} = 1;
let Inst{24-20} = 0b11100; let Inst{24-20} = 0b11100;
let Inst{15} = 0; let Inst{15} = 0;
let hasSideEffects = 0;
} }
// A8.8.247 UDF - Undefined (Encoding T2) // A8.8.247 UDF - Undefined (Encoding T2)
def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
[(int_arm_undefined imm0_65535:$imm16)]> { [(int_arm_undefined imm0_65535:$imm16)]> {
bits<16> imm16; bits<16> imm16;
let Inst{31-29} = 0b111; let Inst{31-29} = 0b111;
let Inst{28-27} = 0b10; let Inst{28-27} = 0b10;
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llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll

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; CHECK-NEXT: vldr.16 s0, [r2, #6] ; CHECK-NEXT: vldr.16 s0, [r2, #6]
; CHECK-NEXT: vmov.16 q1[1], r1 ; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vmov r1, s9 ; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: vmov.16 q1[2], r1 ; CHECK-NEXT: vmov.16 q1[2], r1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q1[3], r1 ; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: .LBB18_9: @ %else8 ; CHECK-NEXT: .LBB18_9: @ %else8
; CHECK-NEXT: vmrs r2, p0 ; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vmovx.f16 s0, s5 ; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vcvtb.f32.f16 s3, s0
; CHECK-NEXT: vmovx.f16 s8, s4 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vcvtb.f32.f16 s3, s0
; CHECK-NEXT: vcvtb.f32.f16 s2, s5 ; CHECK-NEXT: vcvtb.f32.f16 s2, s5
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vcvtb.f32.f16 s1, s8 ; CHECK-NEXT: vcvtb.f32.f16 s1, s8
; CHECK-NEXT: vcvtb.f32.f16 s0, s4 ; CHECK-NEXT: vcvtb.f32.f16 s0, s4
; CHECK-NEXT: and r3, r2, #1 ; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #0, #1 ; CHECK-NEXT: bfi r1, r3, #0, #1
; CHECK-NEXT: ubfx r3, r2, #4, #1 ; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #1, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1
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; CHECK-NEXT: vldr.16 s0, [r2, #6] ; CHECK-NEXT: vldr.16 s0, [r2, #6]
; CHECK-NEXT: vmov.16 q1[1], r1 ; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vmov r1, s9 ; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: vmov.16 q1[2], r1 ; CHECK-NEXT: vmov.16 q1[2], r1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q1[3], r1 ; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: .LBB19_9: @ %else8 ; CHECK-NEXT: .LBB19_9: @ %else8
; CHECK-NEXT: vmrs r2, p0 ; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vmovx.f16 s0, s5 ; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vcvtb.f32.f16 s3, s0
; CHECK-NEXT: vmovx.f16 s8, s4 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vcvtb.f32.f16 s3, s0
; CHECK-NEXT: vcvtb.f32.f16 s2, s5 ; CHECK-NEXT: vcvtb.f32.f16 s2, s5
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vcvtb.f32.f16 s1, s8 ; CHECK-NEXT: vcvtb.f32.f16 s1, s8
; CHECK-NEXT: vcvtb.f32.f16 s0, s4 ; CHECK-NEXT: vcvtb.f32.f16 s0, s4
; CHECK-NEXT: and r3, r2, #1 ; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #0, #1 ; CHECK-NEXT: bfi r1, r3, #0, #1
; CHECK-NEXT: ubfx r3, r2, #4, #1 ; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #1, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1
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llvm/test/tools/llvm-mca/ARM/m4-int.s

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# CHECK-NEXT: 1 2 1.00 * ldrb.w r0, [pc, #4] # CHECK-NEXT: 1 2 1.00 * ldrb.w r0, [pc, #4]
# CHECK-NEXT: 1 2 1.00 * ldrb.w r0, next # CHECK-NEXT: 1 2 1.00 * ldrb.w r0, next
# CHECK-NEXT: 1 2 1.00 * ldrb r0, [r1, r2] # CHECK-NEXT: 1 2 1.00 * ldrb r0, [r1, r2]
# CHECK-NEXT: 1 2 1.00 * ldrb.w r0, [r1, r2] # CHECK-NEXT: 1 2 1.00 * ldrb.w r0, [r1, r2]
# CHECK-NEXT: 1 2 1.00 * ldrb.w r0, [r1, r2, lsl #1] # CHECK-NEXT: 1 2 1.00 * ldrb.w r0, [r1, r2, lsl #1]
# CHECK-NEXT: 1 2 1.00 U ldrbt r0, [r1, #1] # CHECK-NEXT: 1 2 1.00 U ldrbt r0, [r1, #1]
# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1] # CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1]
# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1, #-4] # CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1, #-4]
# CHECK-NEXT: 1 2 1.00 * U ldrd r0, r2, [r1], #4 # CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1], #4
# CHECK-NEXT: 1 2 1.00 * U ldrd r0, r2, [r1, #4]! # CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1, #4]!
# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, next # CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, next
# CHECK-NEXT: 1 2 1.00 * * U ldrex r0, [r1] # CHECK-NEXT: 1 2 1.00 * * U ldrex r0, [r1]
# CHECK-NEXT: 1 2 1.00 * * U ldrex r0, [r1, #4] # CHECK-NEXT: 1 2 1.00 * * U ldrex r0, [r1, #4]
# CHECK-NEXT: 1 2 1.00 * * U ldrexb r0, [r1] # CHECK-NEXT: 1 2 1.00 * * U ldrexb r0, [r1]
# CHECK-NEXT: 1 2 1.00 * * U ldrexh r0, [r1] # CHECK-NEXT: 1 2 1.00 * * U ldrexh r0, [r1]
# CHECK-NEXT: 1 2 1.00 * ldrh r0, [r1, #2] # CHECK-NEXT: 1 2 1.00 * ldrh r0, [r1, #2]
# CHECK-NEXT: 1 2 1.00 * ldrh.w r0, [r1, #1] # CHECK-NEXT: 1 2 1.00 * ldrh.w r0, [r1, #1]
# CHECK-NEXT: 1 2 1.00 * ldrh r0, [r1, #-1] # CHECK-NEXT: 1 2 1.00 * ldrh r0, [r1, #-1]
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# CHECK-NEXT: 1 1 1.00 * * U sasx r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U sasx r0, r1, r2
# CHECK-NEXT: 1 1 1.00 sbc r0, r1, #1 # CHECK-NEXT: 1 1 1.00 sbc r0, r1, #1
# CHECK-NEXT: 1 1 1.00 sbcs r0, r1, #1 # CHECK-NEXT: 1 1 1.00 sbcs r0, r1, #1
# CHECK-NEXT: 1 1 1.00 U sbcs r0, r1 # CHECK-NEXT: 1 1 1.00 U sbcs r0, r1
# CHECK-NEXT: 1 1 1.00 sbc.w r0, r1, r2 # CHECK-NEXT: 1 1 1.00 sbc.w r0, r1, r2
# CHECK-NEXT: 1 1 1.00 sbcs.w r0, r1, r2 # CHECK-NEXT: 1 1 1.00 sbcs.w r0, r1, r2
# CHECK-NEXT: 1 1 1.00 sbc.w r0, r1, r2, lsl #1 # CHECK-NEXT: 1 1 1.00 sbc.w r0, r1, r2, lsl #1
# CHECK-NEXT: 1 1 1.00 sbcs.w r0, r1, r2, lsl #1 # CHECK-NEXT: 1 1 1.00 sbcs.w r0, r1, r2, lsl #1
# CHECK-NEXT: 1 1 1.00 U sbfx r0, r1, #1, #2 # CHECK-NEXT: 1 1 1.00 sbfx r0, r1, #1, #2
# CHECK-NEXT: 1 2 1.00 sdiv r0, r1, r2 # CHECK-NEXT: 1 2 1.00 sdiv r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * sel r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * sel r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U sev # CHECK-NEXT: 1 1 1.00 * * U sev
# CHECK-NEXT: 1 1 1.00 shadd16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 shadd16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 shadd8 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 shadd8 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 shasx r0, r1, r2 # CHECK-NEXT: 1 1 1.00 shasx r0, r1, r2
# CHECK-NEXT: 1 1 1.00 shsax r0, r1, r2 # CHECK-NEXT: 1 1 1.00 shsax r0, r1, r2
# CHECK-NEXT: 1 1 1.00 shsub16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 shsub16 r0, r1, r2
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# CHECK-NEXT: 1 1 1.00 * strb r0, [r1, #-1] # CHECK-NEXT: 1 1 1.00 * strb r0, [r1, #-1]
# CHECK-NEXT: 1 1 1.00 * strb r0, [r1], #1 # CHECK-NEXT: 1 1 1.00 * strb r0, [r1], #1
# CHECK-NEXT: 1 1 1.00 * strb r0, [r1, #1]! # CHECK-NEXT: 1 1 1.00 * strb r0, [r1, #1]!
# CHECK-NEXT: 1 1 1.00 * strb r0, [r1, r2] # CHECK-NEXT: 1 1 1.00 * strb r0, [r1, r2]
# CHECK-NEXT: 1 1 1.00 * strb.w r0, [r1, r2] # CHECK-NEXT: 1 1 1.00 * strb.w r0, [r1, r2]
# CHECK-NEXT: 1 1 1.00 * strb.w r0, [r1, r2, lsl #1] # CHECK-NEXT: 1 1 1.00 * strb.w r0, [r1, r2, lsl #1]
# CHECK-NEXT: 1 1 1.00 U strbt r0, [r1, #1] # CHECK-NEXT: 1 1 1.00 U strbt r0, [r1, #1]
# CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2, #4] # CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2, #4]
# CHECK-NEXT: 1 1 1.00 * U strd r0, r1, [r2], #4 # CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2], #4
# CHECK-NEXT: 1 1 1.00 * U strd r0, r1, [r2, #4]! # CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2, #4]!
# CHECK-NEXT: 1 1 1.00 * * U strex r0, r1, [r2] # CHECK-NEXT: 1 1 1.00 * * U strex r0, r1, [r2]
# CHECK-NEXT: 1 1 1.00 * * U strex r0, r1, [r2, #4] # CHECK-NEXT: 1 1 1.00 * * U strex r0, r1, [r2, #4]
# CHECK-NEXT: 1 1 1.00 * * U strexb r0, r1, [r2] # CHECK-NEXT: 1 1 1.00 * * U strexb r0, r1, [r2]
# CHECK-NEXT: 1 1 1.00 * * U strexh r0, r1, [r2] # CHECK-NEXT: 1 1 1.00 * * U strexh r0, r1, [r2]
# CHECK-NEXT: 1 1 1.00 * strh r0, [r1] # CHECK-NEXT: 1 1 1.00 * strh r0, [r1]
# CHECK-NEXT: 1 1 1.00 * strh r0, [r1, #2] # CHECK-NEXT: 1 1 1.00 * strh r0, [r1, #2]
# CHECK-NEXT: 1 1 1.00 * strh.w r0, [r1, #2] # CHECK-NEXT: 1 1 1.00 * strh.w r0, [r1, #2]
# CHECK-NEXT: 1 1 1.00 * strh r0, [r1, #-1] # CHECK-NEXT: 1 1 1.00 * strh r0, [r1, #-1]
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# CHECK-NEXT: 1 1 1.00 teq.w r0, r1, lsl #1 # CHECK-NEXT: 1 1 1.00 teq.w r0, r1, lsl #1
# CHECK-NEXT: 1 1 1.00 tst.w r0, #1 # CHECK-NEXT: 1 1 1.00 tst.w r0, #1
# CHECK-NEXT: 1 1 1.00 tst r0, r1 # CHECK-NEXT: 1 1 1.00 tst r0, r1
# CHECK-NEXT: 1 1 1.00 tst.w r0, r1 # CHECK-NEXT: 1 1 1.00 tst.w r0, r1
# CHECK-NEXT: 1 1 1.00 tst.w r0, r1, lsl #1 # CHECK-NEXT: 1 1 1.00 tst.w r0, r1, lsl #1
# CHECK-NEXT: 1 1 1.00 * * U uadd16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U uadd16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U uadd8 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U uadd8 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U uasx r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U uasx r0, r1, r2
# CHECK-NEXT: 1 1 1.00 U ubfx r0, r1, #1, #2 # CHECK-NEXT: 1 1 1.00 ubfx r0, r1, #1, #2
# CHECK-NEXT: 1 2 1.00 udiv r0, r1, r2 # CHECK-NEXT: 1 2 1.00 udiv r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uhadd16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uhadd16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uhadd8 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uhadd8 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uhasx r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uhasx r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uhsax r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uhsax r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uhsub16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uhsub16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uhsub8 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uhsub8 r0, r1, r2
# CHECK-NEXT: 2 2 2.00 umaal r0, r1, r2, r3 # CHECK-NEXT: 2 2 2.00 umaal r0, r1, r2, r3
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