[LiveIntervals] Fix early-clobber handling in handleMoveUp

[foad]

Summary

Without this fix, handleMoveUp can create an invalid live range like
this:

[98904e,98908r:0)[98908e,227504r:1)

where the two segments overlap, but only because we have lost the "e"
(early-clobber) on the end point of the first segment.

[arsenm]

LGTM, but unfortunately doesn't help me with either of the 2 LiveIntervals problems I'm looking at

llvm/unittests/MI/LiveIntervalTest.cpp

450–455

Can you compact these test register numbers?

llvm/lib/CodeGen/LiveIntervals.cpp

if (SlotIndex::isSameInstr(NewIdxOut->start, NewIdx)) {
             *NewSegment = LiveRange::Segment(SplitPos, Next->start, OldIdxVNI);
             NewSegment->valno->def = SplitPos;
           }
         } else {
           // Leave the end point of a live def.
           OldIdxOut->start = NewIdxDef;
           OldIdxVNI->def = NewIdxDef;
           if (OldIdxIn != E && SlotIndex::isEarlierInstr(NewIdx, OldIdxIn->end))
-            OldIdxIn->end = NewIdx.getRegSlot();
+            OldIdxIn->end = NewIdxDef;
         }
       } else if (OldIdxIn != E
           && SlotIndex::isEarlierInstr(NewIdxOut->start, NewIdx)
           && SlotIndex::isEarlierInstr(NewIdx, NewIdxOut->end)) {
         // OldIdxVNI is a dead def that has been moved into the middle of
         // another value in LR. That can happen when LR is a whole register,
         // but the dead def is a write to a subreg that is dead at NewIdx.
         // The dead def may have been moved across other values

llvm/unittests/MI/LiveIntervalTest.cpp

liveIntervalTest(R"MIR(
     undef %124.sub1:vreg_128 = nofpexcept V_MAD_F32 0, %57, 0, undef %70:vgpr_32, 0, %125.sub1, 0, 0, implicit $mode, implicit $exec
     %124.sub0:vreg_128 = nofpexcept V_MAD_F32 0, %54, 0, undef %73:vgpr_32, 0, %125.sub0, 0, 0, implicit $mode, implicit $exec
     dead undef %125.sub3:vreg_128 = nofpexcept V_MAC_F32_e32 %63, undef %76:vgpr_32, %125.sub3, implicit $mode, implicit $exec
 )MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
     testHandleMove(MF, LIS, 15, 12);
   });
 }
 
+TEST(LiveIntervalTest, EarlyClobberSubRegMoveUp) {
+  // handleMoveUp had a bug where moving an early-clobber subreg def into the
+  // middle of an earlier segment resulted in an invalid live range.
+  liveIntervalTest(R"MIR(
+    %4:sreg_32 = IMPLICIT_DEF
+    %6:sreg_32 = IMPLICIT_DEF
+    undef early-clobber %9.sub0:sreg_64 = WWM %4:sreg_32, implicit $exec
+    %5:sreg_32 = S_FLBIT_I32_B32 %9.sub0:sreg_64
+    early-clobber %9.sub1:sreg_64 = WWM %6:sreg_32, implicit $exec
+    %7:sreg_32 = S_FLBIT_I32_B32 %9.sub1:sreg_64
+)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
+    testHandleMove(MF, LIS, 4, 3);
+  });
+}
+
 TEST(LiveIntervalTest, TestMoveSubRegDefAcrossUseDef) {
   liveIntervalTest(R"MIR(
     %1:vreg_64 = IMPLICIT_DEF
 
   bb.1:
     %2:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
     %3:vgpr_32 = V_ADD_U32_e32 %2, %1.sub0, implicit $exec
     undef %1.sub0:vreg_64 = V_ADD_U32_e32 %2, %2, implicit $exec