GlobalISel: Don't fail translate on weak cmpxchg

[arsenm]

Summary

The translation of cmpxchg added by
9481399c0fd2c198c81b92636c0dcff7d4c41df2 specifically skipped weak
cmpxchg due to not understanding the meaning. Weak cmpxchg was added
in 420a216817def01816186910a2e35885c9201951. As explained in the
commit message, the weak mode is implicit in how
ATOMIC_CMP_SWAP_WITH_SUCCESS is lowered. If it's expanded to a regular
ATOMIC_CMP_SWAP, it's replaced with a strong cmpxchg.

This handling seems weird to me, but this was already following the
DAG behavior. I would expect the strong IR instruction to not have the
boolean output. Failing that, I might expect the IRTranslator to emit
ATOMIC_CMP_SWAP and a constant for the boolean.

[jfb]

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

1980

Does this now contains two loops instead of just one?

[arsenm]

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

1980

No? Not sure why you think there is

[jfb]

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

1980

The label name is different. It's a fundamental property of weak cmpxchg that it's (mostly) used inside a user-provided loop, so it's important to make sure we don't add an inner loop when translating it.

[arsenm]

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

1980

The label name is the same, MIR functions just get bb.<blocknumber> prepended to the IR block name

[arsenm]

ping

[arsenm]

ping

[paquette]

Considering this just follows the DAG behaviour, this LGTM.

[arsenm]

c2e403c19d40524f868d7803b104224ca4978597

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
   PendingPHIs.emplace_back(&PI, std::move(Insts));
   return true;
 }
 
 bool IRTranslator::translateAtomicCmpXchg(const User &U,
                                           MachineIRBuilder &MIRBuilder) {
   const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
 
-  if (I.isWeak())
-    return false;
-
   auto &TLI = *MF->getSubtarget().getTargetLowering();
   auto Flags = TLI.getAtomicMemOperandFlags(I, *DL);
 
   Type *ResType = I.getType();
   Type *ValType = ResType->Type::getStructElementType(0);
 
   auto Res = getOrCreateVRegs(I);
   Register OldValRes = Res[0];

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

repeat:
   %val_success = cmpxchg i32* %addr, i32 0, i32 1 monotonic monotonic
   %value_loaded = extractvalue { i32, i1 } %val_success, 0
   %success = extractvalue { i32, i1 } %val_success, 1
   br i1 %success, label %done, label %repeat
 done:
   ret i32 %value_loaded
 }
 
+; Try one cmpxchg
+define i32 @test_weak_atomic_cmpxchg_1(i32* %addr) {
+; CHECK-LABEL: name: test_weak_atomic_cmpxchg_1
+; CHECK:       bb.1.entry:
+; CHECK-NEXT:  successors: %bb.{{[^)]+}}
+; CHECK-NEXT:  liveins: $x0
+; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
+; CHECK-NEXT:    [[OLDVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-NEXT:    [[NEWVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK:       bb.2.repeat:
+; CHECK-NEXT:    successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
+; CHECK:         [[OLDVALRES:%[0-9]+]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic 4 on %ir.addr)
+; CHECK-NEXT:    G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK-NEXT:    G_BR %bb.2
+; CHECK:       bb.3.done:
+entry:
+  br label %repeat
+repeat:
+  %val_success = cmpxchg weak i32* %addr, i32 0, i32 1 monotonic monotonic
+  %value_loaded = extractvalue { i32, i1 } %val_success, 0
+  %success = extractvalue { i32, i1 } %val_success, 1
+  br i1 %success, label %done, label %repeat
+done:
+  ret i32 %value_loaded
+}
+
 ; Try one cmpxchg with a small type and high atomic ordering.
 define i16 @test_atomic_cmpxchg_2(i16* %addr) {
 ; CHECK-LABEL: name: test_atomic_cmpxchg_2
 ; CHECK:       bb.1.entry:
 ; CHECK-NEXT:  successors: %bb.2({{[^)]+}})
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
 ; CHECK-NEXT:    [[OLDVAL:%[0-9]+]]:_(s16) = G_CONSTANT i16 0