[ARM] MVE VCVT lowering for f16->f32 extends

[dmgreen]

Summary

This adds code to lower f16 to f32 fp_exts's using an MVE VCVT instructions, similar to D81139. Again it goes through the lowering of a BUILD_VECTOR, but is slightly simpler only having to deal with interleaved indices. It adds a VCVTL node to lower to, similar to VCVTN.

[efriedma]

Do you have a testcase that shows what happens for a plain fpext <8 x half> %strided.vec to <8 x float> without any surrounding shuffles?

[dmgreen]

llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

38

Do you have a testcase that shows what happens for a plain fpext <8 x half> %strided.vec to <8 x float> without any surrounding shuffles?

Like this one?

[dmgreen]

Ping :)

llvm/lib/Target/ARM/ARMISelLowering.h

enum NodeType : unsigned {
       VMOVN,        // MVE vmovn
 
       // MVE Saturating truncates
       VQMOVNs,      // Vector (V) Saturating (Q) Move and Narrow (N), signed (s)
       VQMOVNu,      // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u)
 
       // MVE float <> half converts
       VCVTN,        // MVE vcvt f32 -> f16, truncating into either the bottom or top lanes
+      VCVTL,        // MVE vcvt f16 -> f32, extending from either the bottom or top lanes
 
       // Vector multiply long:
       VMULLs,       // ...signed
       VMULLu,       // ...unsigned
 
       // MVE reductions
       VADDVs,       // sign- or zero-extend the elements of a vector to i32,
       VADDVu,       //   add them all together, and return an i32 of their sum

llvm/lib/Target/ARM/ARMISelLowering.cpp

const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::VUZP:          return "ARMISD::VUZP";
   case ARMISD::VTRN:          return "ARMISD::VTRN";
   case ARMISD::VTBL1:         return "ARMISD::VTBL1";
   case ARMISD::VTBL2:         return "ARMISD::VTBL2";
   case ARMISD::VMOVN:         return "ARMISD::VMOVN";
   case ARMISD::VQMOVNs:       return "ARMISD::VQMOVNs";
   case ARMISD::VQMOVNu:       return "ARMISD::VQMOVNu";
   case ARMISD::VCVTN:         return "ARMISD::VCVTN";
+  case ARMISD::VCVTL:         return "ARMISD::VCVTL";
   case ARMISD::VMULLs:        return "ARMISD::VMULLs";
   case ARMISD::VMULLu:        return "ARMISD::VMULLu";
   case ARMISD::VADDVs:        return "ARMISD::VADDVs";
   case ARMISD::VADDVu:        return "ARMISD::VADDVu";
   case ARMISD::VADDLVs:       return "ARMISD::VADDLVs";
   case ARMISD::VADDLVu:       return "ARMISD::VADDLVu";
   case ARMISD::VADDLVAs:      return "ARMISD::VADDLVAs";
   case ARMISD::VADDLVAu:      return "ARMISD::VADDLVAu";
if (M[i] >= 0 && M[i] != (int)i)
       return false;
     if (M[i+1] >= 0 && M[i+1] != (int)(NumElts + i + Offset))
       return false;
   }
 
   return true;
 }
 
-// Reconstruct an MVE VCVT from a BuildVector of scalar fptrunc, all extract
+// Reconstruct an MVE VCVT from a BuildVector of scalar fptrunc, all extracted
 // from a pair of inputs. For example:
 // BUILDVECTOR(FP_ROUND(EXTRACT_ELT(X, 0),
 //             FP_ROUND(EXTRACT_ELT(Y, 0),
 //             FP_ROUND(EXTRACT_ELT(X, 1),
 //             FP_ROUND(EXTRACT_ELT(Y, 1), ...)
 static SDValue LowerBuildVectorOfFPTrunc(SDValue BV, SelectionDAG &DAG,
                                          const ARMSubtarget *ST) {
   assert(BV.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
static SDValue LowerBuildVectorOfFPTrunc(SDValue BV, SelectionDAG &DAG,
   }
 
   SDValue N1 = DAG.getNode(ARMISD::VCVTN, dl, VT, DAG.getUNDEF(VT), Op0,
                            DAG.getConstant(0, dl, MVT::i32));
   return DAG.getNode(ARMISD::VCVTN, dl, VT, N1, Op1,
                      DAG.getConstant(1, dl, MVT::i32));
 }
 
+// Reconstruct an MVE VCVT from a BuildVector of scalar fpext, all extracted
+// from a single input on alternating lanes. For example:
+// BUILDVECTOR(FP_ROUND(EXTRACT_ELT(X, 0),
+//             FP_ROUND(EXTRACT_ELT(X, 2),
+//             FP_ROUND(EXTRACT_ELT(X, 4), ...)
+static SDValue LowerBuildVectorOfFPExt(SDValue BV, SelectionDAG &DAG,
+                                       const ARMSubtarget *ST) {
+  assert(BV.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
+  if (!ST->hasMVEFloatOps())
+    return SDValue();
+
+  SDLoc dl(BV);
+  EVT VT = BV.getValueType();
+  if (VT != MVT::v4f32)
+    return SDValue();
+
+  // We are looking for a buildvector of fptext elements, where all the
+  // elements are alternating lanes from a single source. For example <0,2,4,6>
+  // or <1,3,5,7>. Check the first two items are valid enough and extract some
+  // info from them (they are checked properly in the loop below).
+  if (BV.getOperand(0).getOpcode() != ISD::FP_EXTEND ||
+      BV.getOperand(0).getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT)
+    return SDValue();
+  SDValue Op0 = BV.getOperand(0).getOperand(0).getOperand(0);
+  int Offset = BV.getOperand(0).getOperand(0).getConstantOperandVal(1);
+  if (Op0.getValueType() != MVT::v8f16 || (Offset != 0 && Offset != 1))
+    return SDValue();
+
+  // Check all the values in the BuildVector line up with our expectations.
+  for (unsigned i = 1; i < 4; i++) {
+    auto Check = [](SDValue Trunc, SDValue Op, unsigned Idx) {
+      return Trunc.getOpcode() == ISD::FP_EXTEND &&
+             Trunc.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
+             Trunc.getOperand(0).getOperand(0) == Op &&
+             Trunc.getOperand(0).getConstantOperandVal(1) == Idx;
+    };
+    if (!Check(BV.getOperand(i), Op0, 2 * i + Offset))
+      return SDValue();
+  }
+
+  return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0,
+                     DAG.getConstant(Offset, dl, MVT::i32));
+}
+
 // If N is an integer constant that can be moved into a register in one
 // instruction, return an SDValue of such a constant (will become a MOV
 // instruction).  Otherwise return null.
 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
                                      const ARMSubtarget *ST, const SDLoc &dl) {
   uint64_t Val;
   if (!isa<ConstantSDNode>(N))
     return SDValue();
SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
 
   // Reconstruct the BUILDVECTOR to one of the legal shuffles (such as vext and
   // vmovn). Empirical tests suggest this is rarely worth it for vectors of
   // length <= 2.
   if (NumElts >= 4)
     if (SDValue shuffle = ReconstructShuffle(Op, DAG))
       return shuffle;
 
-  // Attempt to turn a buildvector of scalar fptrunc's back into VCVT's
+  // Attempt to turn a buildvector of scalar fptrunc's or fpext's back into
+  // VCVT's
   if (SDValue VCVT = LowerBuildVectorOfFPTrunc(Op, DAG, Subtarget))
     return VCVT;
+  if (SDValue VCVT = LowerBuildVectorOfFPExt(Op, DAG, Subtarget))
+    return VCVT;
 
   if (ST->hasNEON() && VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) {
     // If we haven't found an efficient lowering, try splitting a 128-bit vector
     // into two 64-bit vectors; we might discover a better way to lower it.
     SmallVector<SDValue, 64> Ops(Op->op_begin(), Op->op_begin() + NumElts);
     EVT ExtVT = VT.getVectorElementType();
     EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElts / 2);
     SDValue Lower =

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,
   let Inst{12} = T;
   let Inst{8-7} = 0b00;
   let Inst{0} = 0b1;
 
   let Predicates = [HasMVEFloat];
   let retainsPreviousHalfElement = 1;
 }
 
+def SDTARMVCVTL    : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
+                                         SDTCisVT<2, i32>]>;
 def MVEvcvtn       : SDNode<"ARMISD::VCVTN", SDTARMVMOVNQ>;
+def MVEvcvtl       : SDNode<"ARMISD::VCVTL", SDTARMVCVTL>;
 
 multiclass MVE_VCVT_f2h_m<string iname, int half> {
   def "": MVE_VCVT_ff<iname, "f16.f32", 0b0, half,
                       (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
   defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEFloat] in {
     def : Pat<(v8f16 (int_arm_mve_vcvt_narrow
multiclass MVE_VCVT_h2f_m<string iname, int half> {
   let Predicates = [HasMVEFloat] in {
     def : Pat<(v4f32 (int_arm_mve_vcvt_widen (v8f16 MQPR:$Qm), (i32 half))),
               (v4f32 (Inst (v8f16 MQPR:$Qm)))>;
     def : Pat<(v4f32 (int_arm_mve_vcvt_widen_predicated
                          (v4f32 MQPR:$inactive), (v8f16 MQPR:$Qm), (i32 half),
                          (v4i1 VCCR:$mask))),
               (v4f32 (Inst (v8f16 MQPR:$Qm), ARMVCCThen,
                            (v4i1 VCCR:$mask), (v4f32 MQPR:$inactive)))>;
+
+    def : Pat<(v4f32 (MVEvcvtl (v8f16 MQPR:$Qm), (i32 half))),
+              (v4f32 (Inst (v8f16 MQPR:$Qm)))>;
   }
 }
 
 defm MVE_VCVTf16f32bh : MVE_VCVT_f2h_m<"vcvtb", 0b0>;
 defm MVE_VCVTf16f32th : MVE_VCVT_f2h_m<"vcvtt", 0b1>;
 defm MVE_VCVTf32f16bh : MVE_VCVT_h2f_m<"vcvtb", 0b0>;
 defm MVE_VCVTf32f16th : MVE_VCVT_h2f_m<"vcvtt", 0b1>;
 

llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll

for.cond.cleanup:                                 ; preds = %vector.body
   ret void
 }
 
 define void @both_8_I(half* nocapture readonly %x, half* noalias nocapture %y) {
 ; CHECK-LABEL: both_8_I:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
-; CHECK-NEXT:    .vsave {d8, d9}
-; CHECK-NEXT:    vpush {d8, d9}
 ; CHECK-NEXT:    adr r2, .LCPI9_0
 ; CHECK-NEXT:    mov.w lr, #128
 ; CHECK-NEXT:    vldrw.u32 q0, [r2]
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB9_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrh.u16 q1, [r0], #16
-; CHECK-NEXT:    vmovx.f16 s8, s7
-; CHECK-NEXT:    vmovx.f16 s14, s6
-; CHECK-NEXT:    vcvtb.f32.f16 s11, s8
-; CHECK-NEXT:    vmovx.f16 s13, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s10, s14
-; CHECK-NEXT:    vmovx.f16 s12, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s9, s13
-; CHECK-NEXT:    vcvtb.f32.f16 s19, s7
-; CHECK-NEXT:    vcvtb.f32.f16 s18, s6
-; CHECK-NEXT:    vcvtb.f32.f16 s17, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s16, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s8, s12
-; CHECK-NEXT:    vmul.f32 q1, q4, q0
+; CHECK-NEXT:    vcvtb.f32.f16 q2, q1
+; CHECK-NEXT:    vcvtt.f32.f16 q1, q1
 ; CHECK-NEXT:    vmul.f32 q2, q2, q0
-; CHECK-NEXT:    vcvtb.f16.f32 q1, q1
-; CHECK-NEXT:    vcvtt.f16.f32 q1, q2
-; CHECK-NEXT:    vstrb.8 q1, [r1], #16
+; CHECK-NEXT:    vmul.f32 q1, q1, q0
+; CHECK-NEXT:    vcvtb.f16.f32 q2, q2
+; CHECK-NEXT:    vcvtt.f16.f32 q2, q1
+; CHECK-NEXT:    vstrb.8 q2, [r1], #16
 ; CHECK-NEXT:    le lr, .LBB9_1
 ; CHECK-NEXT:  @ %bb.2: @ %for.cond.cleanup
-; CHECK-NEXT:    vpop {d8, d9}
 ; CHECK-NEXT:    pop {r7, pc}
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.3:
 ; CHECK-NEXT:  .LCPI9_0:
 ; CHECK-NEXT:    .long 0x40066666 @ float 2.0999999
 ; CHECK-NEXT:    .long 0x40066666 @ float 2.0999999
 ; CHECK-NEXT:    .long 0x40066666 @ float 2.0999999
 ; CHECK-NEXT:    .long 0x40066666 @ float 2.0999999
for.cond.cleanup:                                 ; preds = %vector.body
   ret void
 }
 
 define void @both_16_I(half* nocapture readonly %x, half* noalias nocapture %y) {
 ; CHECK-LABEL: both_16_I:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
-; CHECK-NEXT:    .vsave {d8, d9}
-; CHECK-NEXT:    vpush {d8, d9}
 ; CHECK-NEXT:    adr r2, .LCPI10_0
 ; CHECK-NEXT:    mov.w lr, #128
 ; CHECK-NEXT:    vldrw.u32 q0, [r2]
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB10_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrh.u16 q1, [r0]
-; CHECK-NEXT:    vmovx.f16 s8, s7
-; CHECK-NEXT:    vmovx.f16 s14, s6
-; CHECK-NEXT:    vcvtb.f32.f16 s11, s8
-; CHECK-NEXT:    vmovx.f16 s13, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s10, s14
-; CHECK-NEXT:    vmovx.f16 s12, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s9, s13
-; CHECK-NEXT:    vcvtb.f32.f16 s19, s7
-; CHECK-NEXT:    vcvtb.f32.f16 s18, s6
-; CHECK-NEXT:    vcvtb.f32.f16 s17, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s16, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s8, s12
-; CHECK-NEXT:    vmul.f32 q1, q4, q0
+; CHECK-NEXT:    vcvtb.f32.f16 q2, q1
+; CHECK-NEXT:    vcvtt.f32.f16 q1, q1
 ; CHECK-NEXT:    vmul.f32 q2, q2, q0
-; CHECK-NEXT:    vcvtb.f16.f32 q1, q1
-; CHECK-NEXT:    vcvtt.f16.f32 q1, q2
-; CHECK-NEXT:    vstrh.16 q1, [r1]
+; CHECK-NEXT:    vmul.f32 q1, q1, q0
+; CHECK-NEXT:    vcvtb.f16.f32 q2, q2
+; CHECK-NEXT:    vcvtt.f16.f32 q2, q1
 ; CHECK-NEXT:    vldrh.u16 q1, [r0, #16]!
-; CHECK-NEXT:    vmovx.f16 s12, s7
-; CHECK-NEXT:    vmovx.f16 s14, s6
-; CHECK-NEXT:    vcvtb.f32.f16 s19, s12
-; CHECK-NEXT:    vmovx.f16 s8, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s18, s14
-; CHECK-NEXT:    vmovx.f16 s10, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s17, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s16, s10
-; CHECK-NEXT:    vcvtb.f32.f16 s11, s7
-; CHECK-NEXT:    vcvtb.f32.f16 s10, s6
-; CHECK-NEXT:    vcvtb.f32.f16 s9, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s8, s4
-; CHECK-NEXT:    vmul.f32 q1, q4, q0
+; CHECK-NEXT:    vstrh.16 q2, [r1]
+; CHECK-NEXT:    vcvtb.f32.f16 q2, q1
+; CHECK-NEXT:    vcvtt.f32.f16 q1, q1
 ; CHECK-NEXT:    vmul.f32 q2, q2, q0
+; CHECK-NEXT:    vmul.f32 q1, q1, q0
 ; CHECK-NEXT:    vcvtb.f16.f32 q2, q2
 ; CHECK-NEXT:    vcvtt.f16.f32 q2, q1
 ; CHECK-NEXT:    vstrb.8 q2, [r1, #16]!
 ; CHECK-NEXT:    le lr, .LBB10_1
 ; CHECK-NEXT:  @ %bb.2: @ %for.cond.cleanup
-; CHECK-NEXT:    vpop {d8, d9}
 ; CHECK-NEXT:    pop {r7, pc}
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.3:
 ; CHECK-NEXT:  .LCPI10_0:
 ; CHECK-NEXT:    .long 0x40066666 @ float 2.0999999
 ; CHECK-NEXT:    .long 0x40066666 @ float 2.0999999
 ; CHECK-NEXT:    .long 0x40066666 @ float 2.0999999
 ; CHECK-NEXT:    .long 0x40066666 @ float 2.0999999

llvm/test/CodeGen/Thumb2/mve-shuffleext.ll

 }
 
 
 ; f16 -> f32
 
 define arm_aapcs_vfpcc <4 x float> @fpext_0246(<8 x half> %src) {
 ; CHECK-LABEL: fpext_0246:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vcvtb.f32.f16 s7, s3
-; CHECK-NEXT:    vcvtb.f32.f16 s6, s2
-; CHECK-NEXT:    vcvtb.f32.f16 s5, s1
-; CHECK-NEXT:    vcvtb.f32.f16 s4, s0
-; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    vcvtb.f32.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %strided.vec = shufflevector <8 x half> %src, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
   %out = fpext <4 x half> %strided.vec to <4 x float>
   ret <4 x float> %out
 }
 
 define arm_aapcs_vfpcc <4 x float> @fpext_1357(<8 x half> %src) {
 ; CHECK-LABEL: fpext_1357:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmovx.f16 s8, s3
-; CHECK-NEXT:    vmovx.f16 s4, s1
-; CHECK-NEXT:    vmovx.f16 s6, s0
-; CHECK-NEXT:    vmovx.f16 s10, s2
-; CHECK-NEXT:    vcvtb.f32.f16 s3, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s2, s10
-; CHECK-NEXT:    vcvtb.f32.f16 s1, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s0, s6
+; CHECK-NEXT:    vcvtt.f32.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %strided.vec = shufflevector <8 x half> %src, <8 x half> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
   %out = fpext <4 x half> %strided.vec to <4 x float>
   ret <4 x float> %out
 }
 
 define arm_aapcs_vfpcc <8 x float> @fpext_02468101214(<16 x half> %src) {
 ; CHECK-LABEL: fpext_02468101214:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vcvtb.f32.f16 s11, s3
-; CHECK-NEXT:    vcvtb.f32.f16 s10, s2
-; CHECK-NEXT:    vcvtb.f32.f16 s9, s1
-; CHECK-NEXT:    vcvtb.f32.f16 s8, s0
-; CHECK-NEXT:    vcvtb.f32.f16 s15, s7
-; CHECK-NEXT:    vcvtb.f32.f16 s14, s6
-; CHECK-NEXT:    vmov q0, q2
-; CHECK-NEXT:    vcvtb.f32.f16 s13, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s12, s4
-; CHECK-NEXT:    vmov q1, q3
+; CHECK-NEXT:    vcvtb.f32.f16 q0, q0
+; CHECK-NEXT:    vcvtb.f32.f16 q1, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %strided.vec = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
   %out = fpext <8 x half> %strided.vec to <8 x float>
   ret <8 x float> %out
 }
 
 define arm_aapcs_vfpcc <8 x float> @fpext_13579111315(<16 x half> %src) {
 ; CHECK-LABEL: fpext_13579111315:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmovx.f16 s14, s6
-; CHECK-NEXT:    vmovx.f16 s8, s5
-; CHECK-NEXT:    vmovx.f16 s5, s3
-; CHECK-NEXT:    vmovx.f16 s10, s4
-; CHECK-NEXT:    vmovx.f16 s12, s7
-; CHECK-NEXT:    vmovx.f16 s4, s1
-; CHECK-NEXT:    vmovx.f16 s6, s0
-; CHECK-NEXT:    vmovx.f16 s7, s2
-; CHECK-NEXT:    vcvtb.f32.f16 s3, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s2, s7
-; CHECK-NEXT:    vcvtb.f32.f16 s1, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s0, s6
-; CHECK-NEXT:    vcvtb.f32.f16 s7, s12
-; CHECK-NEXT:    vcvtb.f32.f16 s6, s14
-; CHECK-NEXT:    vcvtb.f32.f16 s5, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s4, s10
+; CHECK-NEXT:    vcvtt.f32.f16 q0, q0
+; CHECK-NEXT:    vcvtt.f32.f16 q1, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %strided.vec = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
   %out = fpext <8 x half> %strided.vec to <8 x float>
   ret <8 x float> %out
 }

llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

 ; CHECK-NEXT:    vcvtb.f32.f16 s8, s0
 ; CHECK-NEXT:    vcvtb.f32.f16 s7, s4
 ; CHECK-NEXT:    vcvtb.f32.f16 s6, s3
 ; CHECK-NEXT:    vcvtb.f32.f16 s5, s12
 ; CHECK-NEXT:    vcvtb.f32.f16 s4, s2
 ; CHECK-NEXT:    vmov q0, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %out = fpext <8 x half> %src1 to <8 x float>
   ret <8 x float> %out
 }
 
 
 define arm_aapcs_vfpcc <4 x half> @fptrunc_4(<4 x float> %src1) {
 ; CHECK-LABEL: fptrunc_4:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vcvtb.f16.f32 s4, s0
entry:
   %wide.load = load <16 x half>, <16 x half>* %src, align 4
   %e = fpext <16 x half> %wide.load to <16 x float>
   ret <16 x float> %e
 }
 
 define arm_aapcs_vfpcc <4 x float> @load_shuffleext_8(<8 x half>* %src) {
 ; CHECK-LABEL: load_shuffleext_8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vldrw.u32 q1, [r0]
-; CHECK-NEXT:    vcvtb.f32.f16 s3, s7
-; CHECK-NEXT:    vcvtb.f32.f16 s2, s6
-; CHECK-NEXT:    vcvtb.f32.f16 s1, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s0, s4
+; CHECK-NEXT:    vldrw.u32 q0, [r0]
+; CHECK-NEXT:    vcvtb.f32.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %wide.load = load <8 x half>, <8 x half>* %src, align 4
   %sh = shufflevector <8 x half> %wide.load, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
   %e = fpext <4 x half> %sh to <4 x float>
   ret <4 x float> %e
 }