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[ARM] MVE VCVT lowering for f16->f32 extends
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Authored by dmgreen on Jun 7 2020, 4:07 AM.

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Summary

This adds code to lower f16 to f32 fp_exts's using an MVE VCVT instructions, similar to D81139. Again it goes through the lowering of a BUILD_VECTOR, but is slightly simpler only having to deal with interleaved indices. It adds a VCVTL node to lower to, similar to VCVTN.

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dmgreen created this revision.Jun 7 2020, 4:07 AM

Do you have a testcase that shows what happens for a plain fpext <8 x half> %strided.vec to <8 x float> without any surrounding shuffles?

dmgreen marked an inline comment as done.Jun 8 2020, 11:18 PM
dmgreen added inline comments.
llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
38

Do you have a testcase that shows what happens for a plain fpext <8 x half> %strided.vec to <8 x float> without any surrounding shuffles?

Like this one?

simon_tatham accepted this revision.Jun 24 2020, 8:43 AM
This revision is now accepted and ready to land.Jun 24 2020, 8:43 AM
This revision was automatically updated to reflect the committed changes.