AMDGPU: Implement computeKnownAlignForTargetInstr

[arsenm]

Summary

We probably need to move where intrinsics are lowered to copies to
make this useful.

[hliao]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

11178

Try Intrinsic::getAttributes

[arsenm]

Get alignmnent from intrinsic declaration. This can probably go in generic code, but I'm unclear what the semantics of a call site with a lower alignment is

[foad]

In D81297#2085078, @arsenm wrote:

This can probably go in generic code, but I'm unclear what the semantics of a call site with a lower alignment is

IR has the same issue and the solution adopted in D65281 is that any attribute on the call site takes priority.

[arsenm]

ping

[foad]

Why not put it in generic code to start with? I don't understand why the concern about conflicting alignment would prevent that. I mean, are you more confident about how to handle conflicting alignments for AMDGPU than you are for all other targets?

[arsenm]

In D81297#2097573, @foad wrote:

Why not put it in generic code to start with? I don't understand why the concern about conflicting alignment would prevent that. I mean, are you more confident about how to handle conflicting alignments for AMDGPU than you are for all other targets?

I know in this case, even if the call site specified a lower alignment, you're always getting at least 4. For other targets, I don't know if a lower call site alignment would need to be respected. Ultimately we need an assert_align pseudo to track the call site attribute

[foad]

I'd still be inclined to either follow the precedent of IR, or take the max of the two alignments. But I guess this is OK if you're reluctant to do that.

[arsenm]

In D81297#2097987, @foad wrote:

I'd still be inclined to either follow the precedent of IR, or take the max of the two alignments. But I guess this is OK if you're reluctant to do that.

From the context of just the intrinsic itself, we don't have the option

[arsenm]

95605b784b350b9c51fd4f15f312b50566cab30d

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

 
 GISelKnownBits::GISelKnownBits(MachineFunction &MF, unsigned MaxDepth)
     : MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()),
       DL(MF.getFunction().getParent()->getDataLayout()), MaxDepth(MaxDepth) {}
 
 Align GISelKnownBits::computeKnownAlignment(Register R, unsigned Depth) {
   const MachineInstr *MI = MRI.getVRegDef(R);
   switch (MI->getOpcode()) {
+  case TargetOpcode::COPY:
+    return computeKnownAlignment(MI->getOperand(1).getReg(), Depth);
   case TargetOpcode::G_FRAME_INDEX: {
     int FrameIdx = MI->getOperand(1).getIndex();
     return MF.getFrameInfo().getObjectAlign(FrameIdx);
   }
   case TargetOpcode::G_INTRINSIC:
   case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
   default:
     return TL.computeKnownAlignForTargetInstr(*this, R, MRI, Depth + 1);

llvm/lib/Target/AMDGPU/SIISelLowering.h

SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
                    SDValue V) const;
 
   void finalizeLowering(MachineFunction &MF) const override;
 
   void computeKnownBitsForFrameIndex(int FrameIdx,
                                      KnownBits &Known,
                                      const MachineFunction &MF) const override;
 
+  Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R,
+                                        const MachineRegisterInfo &MRI,
+                                        unsigned Depth = 0) const override;
   bool isSDNodeSourceOfDivergence(const SDNode *N,
     FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
 
   bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
                        unsigned MaxDepth = 5) const;
   bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
 
   bool isKnownNeverNaNForTargetNode(SDValue Op,

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

void SITargetLowering::computeKnownBitsForFrameIndex(
   TargetLowering::computeKnownBitsForFrameIndex(FI, Known, MF);
 
   // Set the high bits to zero based on the maximum allowed scratch size per
   // wave. We can't use vaddr in MUBUF instructions if we don't know the address
   // calculation won't overflow, so assume the sign bit is never set.
   Known.Zero.setHighBits(getSubtarget()->getKnownHighZeroBitsForFrameIndex());
 }
 
+Align SITargetLowering::computeKnownAlignForTargetInstr(
+  GISelKnownBits &KB, Register R, const MachineRegisterInfo &MRI,
+  unsigned Depth) const {
+  const MachineInstr *MI = MRI.getVRegDef(R);
+  switch (MI->getOpcode()) {
+  case AMDGPU::G_INTRINSIC: {
+    switch (MI->getIntrinsicID()) {
+    case Intrinsic::amdgcn_dispatch_ptr:
+    case Intrinsic::amdgcn_queue_ptr:
+    case Intrinsic::amdgcn_kernarg_segment_ptr:
+    case Intrinsic::amdgcn_implicitarg_ptr:
+    case Intrinsic::amdgcn_implicit_buffer_ptr:
+      // FIXME: Is there a way to get the default alignment from the intrinsic
+      // declaration?
+      return Align(4);
+    default:
+      return Align(1);
+    }
+  }
+  default:
+    return Align(1);
+  }
+}
+
 Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
   const Align PrefAlign = TargetLowering::getPrefLoopAlignment(ML);
   const Align CacheLineAlign = Align(64);
 
   // Pre-GFX10 target did not benefit from loop alignment
   if (!ML || DisableLoopAlignment ||
       (getSubtarget()->getGeneration() < AMDGPUSubtarget::GFX10) ||
       getSubtarget()->hasInstFwdPrefetchBug())

llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

TEST_F(AMDGPUGISelMITest, TestNumSignBitsTrunc) {
 
   GISelKnownBits Info(*MF);
 
   EXPECT_EQ(24u, Info.computeNumSignBits(CopyLoadUByte));
   EXPECT_EQ(25u, Info.computeNumSignBits(CopyLoadSByte));
   EXPECT_EQ(16u, Info.computeNumSignBits(CopyLoadUShort));
   EXPECT_EQ(17u, Info.computeNumSignBits(CopyLoadSShort));
 }
+
+TEST_F(AMDGPUGISelMITest, TestTargetKnownAlign) {
+  StringRef MIRString =
+    "  %5:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.dispatch.ptr)\n"
+    "  %6:_(p4) = COPY %5\n"
+    "  %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.queue.ptr)\n"
+    "  %8:_(p4) = COPY %7\n"
+    "  %9:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)\n"
+    "  %10:_(p4) = COPY %9\n"
+    "  %11:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicitarg.ptr)\n"
+    "  %12:_(p4) = COPY %11\n"
+    "  %13:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicit.buffer.ptr)\n"
+    "  %14:_(p4) = COPY %13\n";
+
+  setUp(MIRString);
+  if (!TM)
+    return;
+
+  Register CopyDispatchPtr = Copies[Copies.size() - 5];
+  Register CopyQueuePtr = Copies[Copies.size() - 4];
+  Register CopyKernargSegmentPtr = Copies[Copies.size() - 3];
+  Register CopyImplicitArgPtr = Copies[Copies.size() - 2];
+  Register CopyImplicitBufferPtr = Copies[Copies.size() - 1];
+
+  GISelKnownBits Info(*MF);
+
+  EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyDispatchPtr));
+  EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyQueuePtr));
+  EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyKernargSegmentPtr));
+  EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitArgPtr));
+  EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitBufferPtr));
+}