[AMDGPU] Fix failure in VCC spilling

[critson]

Summary

Spills of VCC (SGPR64) will fail with new SGPR spill code,
because super register is not correctly resolved.

[arsenm]

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

941

Don't you just need to change SGPR_64RegClass to SReg_64RegClass (or maybe the XEXEC variant?)

llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir

3

-mattr=-wavefrontsize32,+wavefrontsize64 is unnecessary since wave32 is the default

[critson]

Change to SReg_64_XEXECRegClass.

[critson]

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

941

Thanks, that is a better solution.

llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir

3

This is setting wave64 as the test is not intended for wave32.

[arsenm]

LGTM with test nit

llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir

16

I think I'd go for generated mir checks in this case rather than the manual checks

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

void SIRegisterInfo::buildSGPRSpillLoadStore(MachineBasicBlock::iterator MI,
   } else {
     if (OnlyExecLo) {
       SavedExecReg = NumSubRegs == 1
                          ? SuperReg
                          : getSubReg(SuperReg, SplitParts[FirstPart]);
     } else {
       SavedExecReg =
           getMatchingSuperReg(getSubReg(SuperReg, SplitParts[FirstPart]),
-                              AMDGPU::sub0, &AMDGPU::SGPR_64RegClass);
+                              AMDGPU::sub0, &AMDGPU::SReg_64_XEXECRegClass);
       // If src/dst is an odd size it is possible subreg0 is not aligned.
       if (!SavedExecReg && NumSubRegs > 2)
         SavedExecReg =
             getMatchingSuperReg(getSubReg(SuperReg, SplitParts[FirstPart + 1]),
-                                AMDGPU::sub0, &AMDGPU::SGPR_64RegClass);
+                                AMDGPU::sub0, &AMDGPU::SReg_64_XEXECRegClass);
     }
 
     assert(SavedExecReg);
     BuildMI(*MBB, MI, DL, TII->get(ExecMovOpc), SavedExecReg).addReg(ExecReg);
   }
 
   // Setup EXEC
   BuildMI(*MBB, MI, DL, TII->get(ExecMovOpc), ExecReg).addImm(VGPRLanes);

llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir

+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=CHECK %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=CHECK %s
+
+--- |
+  define amdgpu_kernel void @check_vcc() #0 {
+    ret void
+  }
+
+  define amdgpu_kernel void @check_exec() #0 {
+    ret void
+  }
+
+  attributes #0 = {  "frame-pointer"="all" }
+...
+
+# CHECK-LABEL: name: check_vcc
+# CHECK: $vgpr0 = V_WRITELANE_B32_{{(vi|gfx10)}} $vcc_lo, 0, undef $vgpr0
+# CHECK: $vgpr0 = V_WRITELANE_B32_{{(vi|gfx10)}} $vcc_hi, 1, $vgpr0
+# CHECK: $vgpr0 = V_WRITELANE_B32_{{(vi|gfx10)}} $exec_lo, 32, $vgpr0
+# CHECK: $vgpr0 = V_WRITELANE_B32_{{(vi|gfx10)}} $exec_hi, 33, $vgpr0
+# CHECK: $exec = S_MOV_B64 3
+# CHECK: BUFFER_STORE_DWORD_OFFSET $vgpr0, ${{(sgpr[0-9_]+)*}}, $sgpr33, 4
+# CHECK: $exec_lo = V_READLANE_B32_{{(vi|gfx10)}} $vgpr0, 32
+# CHECK: $exec_hi = V_READLANE_B32_{{(vi|gfx10)}} killed $vgpr0, 33
+
+# CHECK: $vgpr0 = V_WRITELANE_B32_{{(vi|gfx10)}} $vcc_lo, 0, undef $vgpr0
+# CHECK: $vgpr0 = V_WRITELANE_B32_{{(vi|gfx10)}} $vcc_hi, 1, $vgpr0
+# CHECK: $vcc = S_MOV_B64 $exec
+# CHECK: $exec = S_MOV_B64 3
+# CHECK: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, ${{(sgpr[0-9_]+)*}}, $sgpr33, 4
+# CHECK: $exec = S_MOV_B64 killed $vcc
+
+
+# CHECK: $vcc = S_MOV_B64 $exec
+# CHECK: $exec = S_MOV_B64 3
+# CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET ${{(sgpr[0-9_]+)*}}, $sgpr33, 4
+# CHECK: $exec = S_MOV_B64 killed $vcc
+# CHECK: $vcc_lo = V_READLANE_B32_{{(vi|gfx10)}} $vgpr0, 0
+# CHECK: $vcc_hi = V_READLANE_B32_{{(vi|gfx10)}} killed $vgpr0, 1
+---
+name:            check_vcc
+tracksRegLiveness: true
+liveins:
+  - { reg: '$sgpr4_sgpr5' }
+  - { reg: '$sgpr6_sgpr7' }
+  - { reg: '$sgpr8' }
+frameInfo:
+  maxAlignment:    4
+stack:
+  - { id: 0, type: spill-slot, size: 8, alignment: 4 }
+machineFunctionInfo:
+  isEntryFunction: true
+  waveLimiter:     true
+  scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
+  stackPtrOffsetReg: '$sgpr32'
+  frameOffsetReg: '$sgpr33'
+  argumentInfo:
+    privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
+    dispatchPtr:     { reg: '$sgpr4_sgpr5' }
+    kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
+    workGroupIDX:    { reg: '$sgpr8' }
+    privateSegmentWaveByteOffset: { reg: '$sgpr9' }
+body:             |
+  bb.0:
+    liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7
+
+    $vcc = IMPLICIT_DEF
+    SI_SPILL_S64_SAVE $vcc, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
+
+    $vcc = IMPLICIT_DEF
+    SI_SPILL_S64_SAVE killed $vcc, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
+
+    $vcc = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
+
+
+# CHECK-LABEL: name: check_exec
+# CHECK: $vgpr0 = V_WRITELANE_B32_{{(vi|gfx10)}} $exec_lo, 0, undef $vgpr0
+# CHECK: $vgpr0 = V_WRITELANE_B32_{{(vi|gfx10)}} $exec_hi, 1, $vgpr0
+# CHECK: $exec = S_MOV_B64 3
+# CHECK: BUFFER_STORE_DWORD_OFFSET $vgpr0, ${{(sgpr[0-9_]+)*}}, $sgpr33, 4
+# CHECK: $exec_lo = V_READLANE_B32_{{(vi|gfx10)}} $vgpr0, 0
+# CHECK: $exec_hi = V_READLANE_B32_{{(vi|gfx10)}} killed $vgpr0, 1
+
+# CHECK: $exec = S_MOV_B64 3
+# CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET ${{(sgpr[0-9_]+)*}}, $sgpr33, 4
+# CHECK: $exec_lo = V_READLANE_B32_{{(vi|gfx10)}} $vgpr0, 0
+# CHECK: $exec_hi = V_READLANE_B32_{{(vi|gfx10)}} killed $vgpr0, 1
+---
+name:            check_exec
+tracksRegLiveness: true
+liveins:
+  - { reg: '$sgpr4_sgpr5' }
+  - { reg: '$sgpr6_sgpr7' }
+  - { reg: '$sgpr8' }
+frameInfo:
+  maxAlignment:    4
+stack:
+  - { id: 0, type: spill-slot, size: 8, alignment: 4 }
+machineFunctionInfo:
+  isEntryFunction: true
+  waveLimiter:     true
+  scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
+  stackPtrOffsetReg: '$sgpr32'
+  frameOffsetReg: '$sgpr33'
+  argumentInfo:
+    privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
+    dispatchPtr:     { reg: '$sgpr4_sgpr5' }
+    kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
+    workGroupIDX:    { reg: '$sgpr8' }
+    privateSegmentWaveByteOffset: { reg: '$sgpr9' }
+body:             |
+  bb.0:
+    liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7
+
+    SI_SPILL_S64_SAVE $exec, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
+
+    $exec = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32