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Differential D81141

[ARM] Add FP_ROUND handling to splitting MVE stores
ClosedPublic

Authored by dmgreen on Jun 4 2020, 4:05 AM.

Details

Reviewers
SjoerdMeijer
samparker
efriedma
simon_tatham
ostannard
Commits
rG0bfb4c250684: [ARM] Add FP_ROUND handling to splitting MVE stores
Summary

This splits MVE vector stores of a fp_trunc in the same way that we do for standard trunc's. It extends PerformSplittingToNarrowingStores to handle fp_round, splitting the store into pieces and adding a VCVTNb to perform the actual fp_round. The actual store is then converted to an integer store so that it can truncate bottom lanes of the result.

Diff Detail

Event Timeline

dmgreen created this revision.Jun 4 2020, 4:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 4 2020, 4:05 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
dmgreen added a comment.Jun 24 2020, 7:38 AM

Ping :)

SjoerdMeijer accepted this revision.Jun 25 2020, 1:13 AM

Looks reasonable to me.

This revision is now accepted and ready to land.Jun 25 2020, 1:13 AM
Closed by commit rG0bfb4c250684: [ARM] Add FP_ROUND handling to splitting MVE stores (authored by dmgreen). · Explain WhyJun 25 2020, 11:55 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
25 lines
test/
CodeGen/
Thumb2/
326 lines
107 lines

Diff 273475

llvm/lib/Target/ARM/ARMISelLowering.cpp

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Show First 20 Lines • Show All 14,262 Lines • ▼ Show 20 Lines
// Try taking a single vector store from an truncate (which would otherwise turn // Try taking a single vector store from an truncate (which would otherwise turn
// into an expensive buildvector) and splitting it into a series of narrowing // into an expensive buildvector) and splitting it into a series of narrowing
// stores. // stores.
static SDValue PerformSplittingToNarrowingStores(StoreSDNode *St, static SDValue PerformSplittingToNarrowingStores(StoreSDNode *St,
SelectionDAG &DAG) { SelectionDAG &DAG) {
if (!St->isSimple() || St->isTruncatingStore() || !St->isUnindexed()) if (!St->isSimple() || St->isTruncatingStore() || !St->isUnindexed())
return SDValue(); return SDValue();
SDValue Trunc = St->getValue(); SDValue Trunc = St->getValue();
if (Trunc->getOpcode() != ISD::TRUNCATE) if (Trunc->getOpcode() != ISD::TRUNCATE && Trunc->getOpcode() != ISD::FP_ROUND)
return SDValue(); return SDValue();
EVT FromVT = Trunc->getOperand(0).getValueType(); EVT FromVT = Trunc->getOperand(0).getValueType();
EVT ToVT = Trunc.getValueType(); EVT ToVT = Trunc.getValueType();
if (!ToVT.isVector()) if (!ToVT.isVector())
return SDValue(); return SDValue();
assert(FromVT.getVectorNumElements() == ToVT.getVectorNumElements()); assert(FromVT.getVectorNumElements() == ToVT.getVectorNumElements());
EVT ToEltVT = ToVT.getVectorElementType(); EVT ToEltVT = ToVT.getVectorElementType();
EVT FromEltVT = FromVT.getVectorElementType(); EVT FromEltVT = FromVT.getVectorElementType();
unsigned NumElements = 0; unsigned NumElements = 0;
if (FromEltVT == MVT::i32 && (ToEltVT == MVT::i16 || ToEltVT == MVT::i8)) if (FromEltVT == MVT::i32 && (ToEltVT == MVT::i16 || ToEltVT == MVT::i8))
NumElements = 4; NumElements = 4;
if (FromEltVT == MVT::i16 && ToEltVT == MVT::i8) if (FromEltVT == MVT::i16 && ToEltVT == MVT::i8)
NumElements = 8; NumElements = 8;
if (NumElements == 0 || FromVT.getVectorNumElements() == NumElements || if (FromEltVT == MVT::f32 && ToEltVT == MVT::f16)
NumElements = 4;
if (NumElements == 0 ||
(FromEltVT != MVT::f32 && FromVT.getVectorNumElements() == NumElements) ||
FromVT.getVectorNumElements() % NumElements != 0) FromVT.getVectorNumElements() % NumElements != 0)
return SDValue(); return SDValue();
// Test if the Trunc will be convertable to a VMOVN with a shuffle, and if so // Test if the Trunc will be convertable to a VMOVN with a shuffle, and if so
// use the VMOVN over splitting the store. We are looking for patterns of: // use the VMOVN over splitting the store. We are looking for patterns of:
// !rev: 0 N 1 N+1 2 N+2 ... // !rev: 0 N 1 N+1 2 N+2 ...
// rev: N 0 N+1 1 N+2 2 ... // rev: N 0 N+1 1 N+2 2 ...
auto isVMOVNOriginalMask = [&](ArrayRef<int> M, bool rev) { auto isVMOVNOriginalMask = [&](ArrayRef<int> M, bool rev) {
unsigned NumElts = ToVT.getVectorNumElements(); unsigned NumElts = ToVT.getVectorNumElements();
if (NumElts != M.size() || (ToVT != MVT::v8i16 && ToVT != MVT::v16i8)) if (NumElts != M.size())
return false; return false;
unsigned Off0 = rev ? NumElts : 0; unsigned Off0 = rev ? NumElts : 0;
unsigned Off1 = rev ? 0 : NumElts; unsigned Off1 = rev ? 0 : NumElts;
for (unsigned i = 0; i < NumElts; i += 2) { for (unsigned i = 0; i < NumElts; i += 2) {
if (M[i] >= 0 && M[i] != (int)(Off0 + i / 2)) if (M[i] >= 0 && M[i] != (int)(Off0 + i / 2))
return false; return false;
if (M[i + 1] >= 0 && M[i + 1] != (int)(Off1 + i / 2)) if (M[i + 1] >= 0 && M[i + 1] != (int)(Off1 + i / 2))
return false; return false;
} }
return true; return true;
}; };
if (auto *Shuffle = dyn_cast<ShuffleVectorSDNode>(Trunc->getOperand(0))) if (auto *Shuffle = dyn_cast<ShuffleVectorSDNode>(Trunc->getOperand(0)))
if (isVMOVNOriginalMask(Shuffle->getMask(), false) || if (isVMOVNOriginalMask(Shuffle->getMask(), false) ||
isVMOVNOriginalMask(Shuffle->getMask(), true)) isVMOVNOriginalMask(Shuffle->getMask(), true))
return SDValue(); return SDValue();
LLVMContext &C = *DAG.getContext();
SDLoc DL(St); SDLoc DL(St);
// Details about the old store // Details about the old store
SDValue Ch = St->getChain(); SDValue Ch = St->getChain();
SDValue BasePtr = St->getBasePtr(); SDValue BasePtr = St->getBasePtr();
Align Alignment = St->getOriginalAlign(); Align Alignment = St->getOriginalAlign();
MachineMemOperand::Flags MMOFlags = St->getMemOperand()->getFlags(); MachineMemOperand::Flags MMOFlags = St->getMemOperand()->getFlags();
AAMDNodes AAInfo = St->getAAInfo(); AAMDNodes AAInfo = St->getAAInfo();
EVT NewFromVT = EVT::getVectorVT(*DAG.getContext(), FromEltVT, NumElements); // We split the store into slices of NumElements. fp16 trunc stores are vcvt
EVT NewToVT = EVT::getVectorVT(*DAG.getContext(), ToEltVT, NumElements); // and then stored as truncating integer stores.
EVT NewFromVT = EVT::getVectorVT(C, FromEltVT, NumElements);
EVT NewToVT = EVT::getVectorVT(
C, EVT::getIntegerVT(C, ToEltVT.getSizeInBits()), NumElements);
SmallVector<SDValue, 4> Stores; SmallVector<SDValue, 4> Stores;
for (unsigned i = 0; i < FromVT.getVectorNumElements() / NumElements; i++) { for (unsigned i = 0; i < FromVT.getVectorNumElements() / NumElements; i++) {
unsigned NewOffset = i * NumElements * ToEltVT.getSizeInBits() / 8; unsigned NewOffset = i * NumElements * ToEltVT.getSizeInBits() / 8;
SDValue NewPtr = DAG.getObjectPtrOffset(DL, BasePtr, NewOffset); SDValue NewPtr = DAG.getObjectPtrOffset(DL, BasePtr, NewOffset);
SDValue Extract = SDValue Extract =
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewFromVT, Trunc.getOperand(0), DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewFromVT, Trunc.getOperand(0),
DAG.getConstant(i * NumElements, DL, MVT::i32)); DAG.getConstant(i * NumElements, DL, MVT::i32));
if (ToEltVT == MVT::f16) {
SDValue FPTrunc =
DAG.getNode(ARMISD::VCVTN, DL, MVT::v8f16, DAG.getUNDEF(MVT::v8f16),
Extract, DAG.getConstant(0, DL, MVT::i32));
Extract = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, MVT::v4i32, FPTrunc);
}
SDValue Store = DAG.getTruncStore( SDValue Store = DAG.getTruncStore(
Ch, DL, Extract, NewPtr, St->getPointerInfo().getWithOffset(NewOffset), Ch, DL, Extract, NewPtr, St->getPointerInfo().getWithOffset(NewOffset),
NewToVT, Alignment.value(), MMOFlags, AAInfo); NewToVT, Alignment.value(), MMOFlags, AAInfo);
Stores.push_back(Store); Stores.push_back(Store);
} }
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores); return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
} }
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llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
define void @to_4(float* nocapture readonly %x, half* noalias nocapture %y) { define void @to_4(float* nocapture readonly %x, half* noalias nocapture %y) {
; CHECK-LABEL: to_4: ; CHECK-LABEL: to_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: adr r2, .LCPI0_0 ; CHECK-NEXT: adr r2, .LCPI0_0
; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: mov.w lr, #256
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB0_1: @ %vector.body ; CHECK-NEXT: .LBB0_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: vmul.f32 q1, q1, q0 ; CHECK-NEXT: vmul.f32 q1, q1, q0
; CHECK-NEXT: vcvtb.f16.f32 s8, s4 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vstrh.32 q1, [r1], #8
; CHECK-NEXT: vcvtb.f16.f32 s8, s5
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: vmov.16 q2[0], r2
; CHECK-NEXT: vcvtb.f16.f32 s12, s6
; CHECK-NEXT: vmov.16 q2[1], r3
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s4, s7
; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov.16 q2[3], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: str r2, [r1]
; CHECK-NEXT: str r3, [r1, #4]
; CHECK-NEXT: adds r1, #8
; CHECK-NEXT: le lr, .LBB0_1 ; CHECK-NEXT: le lr, .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: .LCPI0_0: ; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
Show All 26 Lines
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: adr r2, .LCPI1_0 ; CHECK-NEXT: adr r2, .LCPI1_0
; CHECK-NEXT: mov.w lr, #128 ; CHECK-NEXT: mov.w lr, #128
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB1_1: @ %vector.body ; CHECK-NEXT: .LBB1_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmul.f32 q1, q1, q0
; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vstrh.32 q1, [r1, #8]
; CHECK-NEXT: vldrw.u32 q1, [r0], #32 ; CHECK-NEXT: vldrw.u32 q1, [r0], #32
; CHECK-NEXT: vmul.f32 q2, q1, q0 ; CHECK-NEXT: vmul.f32 q1, q1, q0
; CHECK-NEXT: vcvtb.f16.f32 s4, s8 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vstrh.32 q1, [r1], #16
; CHECK-NEXT: vcvtb.f16.f32 s4, s9
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.16 q1[0], r2
; CHECK-NEXT: vcvtb.f16.f32 s12, s10
; CHECK-NEXT: vmov.16 q1[1], r3
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vldrw.u32 q2, [r0, #-16]
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmul.f32 q2, q2, q0
; CHECK-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s9
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s10
; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vstrb.8 q1, [r1], #16
; CHECK-NEXT: le lr, .LBB1_1 ; CHECK-NEXT: le lr, .LBB1_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: .LCPI1_0: ; CHECK-NEXT: .LCPI1_0:
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
Show All 26 Lines
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: adr r2, .LCPI2_0 ; CHECK-NEXT: adr r2, .LCPI2_0
; CHECK-NEXT: mov.w lr, #64 ; CHECK-NEXT: mov.w lr, #64
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB2_1: @ %vector.body ; CHECK-NEXT: .LBB2_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vmul.f32 q1, q1, q0
; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vstrh.32 q1, [r1, #24]
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vmul.f32 q2, q1, q0 ; CHECK-NEXT: vmul.f32 q1, q1, q0
; CHECK-NEXT: vcvtb.f16.f32 s4, s8 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vstrh.32 q1, [r1, #16]
; CHECK-NEXT: vcvtb.f16.f32 s4, s9 ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmul.f32 q1, q1, q0
; CHECK-NEXT: vmov.16 q1[0], r2 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vcvtb.f16.f32 s12, s10 ; CHECK-NEXT: vstrh.32 q1, [r1, #8]
; CHECK-NEXT: vmov.16 q1[1], r3
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmul.f32 q2, q2, q0
; CHECK-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s9
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s10
; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vstrh.16 q1, [r1, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0], #64 ; CHECK-NEXT: vldrw.u32 q1, [r0], #64
; CHECK-NEXT: vmul.f32 q2, q1, q0 ; CHECK-NEXT: vmul.f32 q1, q1, q0
; CHECK-NEXT: vcvtb.f16.f32 s4, s9 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vstrh.32 q1, [r1], #32
; CHECK-NEXT: vcvtb.f16.f32 s4, s8
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vcvtb.f16.f32 s12, s10
; CHECK-NEXT: vmov.16 q1[0], r3
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vldrw.u32 q2, [r0, #-48]
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmul.f32 q2, q2, q0
; CHECK-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s9
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s10
; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vstrh.16 q1, [r1], #32
; CHECK-NEXT: le lr, .LBB2_1 ; CHECK-NEXT: le lr, .LBB2_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: .LCPI2_0: ; CHECK-NEXT: .LCPI2_0:
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
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; CHECK-NEXT: vmov.32 q1[1], r3 ; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: vmovx.f16 s10, s5 ; CHECK-NEXT: vmovx.f16 s10, s5
; CHECK-NEXT: vmovx.f16 s8, s4 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vcvtb.f32.f16 s15, s10 ; CHECK-NEXT: vcvtb.f32.f16 s15, s10
; CHECK-NEXT: vcvtb.f32.f16 s14, s5 ; CHECK-NEXT: vcvtb.f32.f16 s14, s5
; CHECK-NEXT: vcvtb.f32.f16 s13, s8 ; CHECK-NEXT: vcvtb.f32.f16 s13, s8
; CHECK-NEXT: vcvtb.f32.f16 s12, s4 ; CHECK-NEXT: vcvtb.f32.f16 s12, s4
; CHECK-NEXT: vmul.f32 q1, q3, q0 ; CHECK-NEXT: vmul.f32 q1, q3, q0
; CHECK-NEXT: vcvtb.f16.f32 s8, s4 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vstrh.32 q1, [r1], #8
; CHECK-NEXT: vcvtb.f16.f32 s8, s5
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: vmov.16 q2[0], r2
; CHECK-NEXT: vcvtb.f16.f32 s12, s6
; CHECK-NEXT: vmov.16 q2[1], r3
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s4, s7
; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov.16 q2[3], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: str r2, [r1]
; CHECK-NEXT: str r3, [r1, #4]
; CHECK-NEXT: adds r1, #8
; CHECK-NEXT: le lr, .LBB6_1 ; CHECK-NEXT: le lr, .LBB6_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: .LCPI6_0: ; CHECK-NEXT: .LCPI6_0:
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
Show All 21 Linesfor.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @both_8(half* nocapture readonly %x, half* noalias nocapture %y) { define void @both_8(half* nocapture readonly %x, half* noalias nocapture %y) {
; CHECK-LABEL: both_8: ; CHECK-LABEL: both_8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: adr r2, .LCPI7_0 ; CHECK-NEXT: adr r2, .LCPI7_0
; CHECK-NEXT: mov.w lr, #128 ; CHECK-NEXT: mov.w lr, #128
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB7_1: @ %vector.body ; CHECK-NEXT: .LBB7_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q2, [r0], #16 ; CHECK-NEXT: vldrh.u16 q1, [r0], #16
; CHECK-NEXT: vmovx.f16 s6, s9 ; CHECK-NEXT: vmovx.f16 s10, s7
; CHECK-NEXT: vmovx.f16 s4, s8 ; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vcvtb.f32.f16 s15, s6 ; CHECK-NEXT: vcvtb.f32.f16 s15, s10
; CHECK-NEXT: vcvtb.f32.f16 s14, s9 ; CHECK-NEXT: vcvtb.f32.f16 s14, s7
; CHECK-NEXT: vcvtb.f32.f16 s13, s4 ; CHECK-NEXT: vcvtb.f32.f16 s13, s8
; CHECK-NEXT: vcvtb.f32.f16 s12, s8 ; CHECK-NEXT: vcvtb.f32.f16 s12, s6
; CHECK-NEXT: vmul.f32 q3, q3, q0 ; CHECK-NEXT: vmul.f32 q2, q3, q0
; CHECK-NEXT: vcvtb.f16.f32 s4, s12 ; CHECK-NEXT: vcvtb.f16.f32 q2, q2
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vstrh.32 q2, [r1, #8]
; CHECK-NEXT: vcvtb.f16.f32 s4, s13 ; CHECK-NEXT: vmovx.f16 s10, s5
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vcvtb.f32.f16 s15, s10
; CHECK-NEXT: vmov.16 q1[0], r2 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vcvtb.f16.f32 s16, s14 ; CHECK-NEXT: vcvtb.f32.f16 s14, s5
; CHECK-NEXT: vcvtb.f16.f32 s12, s15 ; CHECK-NEXT: vcvtb.f32.f16 s13, s8
; CHECK-NEXT: vmovx.f16 s14, s11 ; CHECK-NEXT: vcvtb.f32.f16 s12, s4
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vmul.f32 q1, q3, q0
; CHECK-NEXT: vcvtb.f32.f16 s19, s14 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov.16 q1[1], r3 ; CHECK-NEXT: vstrh.32 q1, [r1], #16
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmovx.f16 s12, s10
; CHECK-NEXT: vcvtb.f32.f16 s18, s11
; CHECK-NEXT: vcvtb.f32.f16 s17, s12
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vcvtb.f32.f16 s16, s10
; CHECK-NEXT: vmul.f32 q2, q4, q0
; CHECK-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s9
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s10
; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vstrb.8 q1, [r1], #16
; CHECK-NEXT: le lr, .LBB7_1 ; CHECK-NEXT: le lr, .LBB7_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: .LCPI7_0: ; CHECK-NEXT: .LCPI7_0:
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
Show All 19 Linesfor.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @both_16(half* nocapture readonly %x, half* noalias nocapture %y) { define void @both_16(half* nocapture readonly %x, half* noalias nocapture %y) {
; CHECK-LABEL: both_16: ; CHECK-LABEL: both_16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: adr r2, .LCPI8_0 ; CHECK-NEXT: adr r2, .LCPI8_0
; CHECK-NEXT: mov.w lr, #64 ; CHECK-NEXT: mov.w lr, #64
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: .LBB8_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q2, [r0, #16] ; CHECK-NEXT: vldrh.u16 q1, [r0, #16]
; CHECK-NEXT: vmovx.f16 s6, s9 ; CHECK-NEXT: vmovx.f16 s10, s7
; CHECK-NEXT: vmovx.f16 s4, s8 ; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vcvtb.f32.f16 s15, s6 ; CHECK-NEXT: vcvtb.f32.f16 s15, s10
; CHECK-NEXT: vcvtb.f32.f16 s14, s9 ; CHECK-NEXT: vcvtb.f32.f16 s14, s7
; CHECK-NEXT: vcvtb.f32.f16 s13, s4 ; CHECK-NEXT: vcvtb.f32.f16 s13, s8
; CHECK-NEXT: vcvtb.f32.f16 s12, s8 ; CHECK-NEXT: vcvtb.f32.f16 s12, s6
; CHECK-NEXT: vmul.f32 q3, q3, q0 ; CHECK-NEXT: vmul.f32 q2, q3, q0
; CHECK-NEXT: vcvtb.f16.f32 s4, s12 ; CHECK-NEXT: vcvtb.f16.f32 q2, q2
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vstrh.32 q2, [r1, #24]
; CHECK-NEXT: vcvtb.f16.f32 s4, s13 ; CHECK-NEXT: vmovx.f16 s10, s5
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vcvtb.f32.f16 s15, s10
; CHECK-NEXT: vmov.16 q1[0], r2 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vcvtb.f16.f32 s16, s14 ; CHECK-NEXT: vcvtb.f32.f16 s14, s5
; CHECK-NEXT: vcvtb.f16.f32 s12, s15 ; CHECK-NEXT: vcvtb.f32.f16 s13, s8
; CHECK-NEXT: vmovx.f16 s14, s11 ; CHECK-NEXT: vcvtb.f32.f16 s12, s4
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vmul.f32 q1, q3, q0
; CHECK-NEXT: vcvtb.f32.f16 s19, s14 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov.16 q1[1], r3 ; CHECK-NEXT: vstrh.32 q1, [r1, #16]
; CHECK-NEXT: vmov.16 q1[2], r2 ; CHECK-NEXT: vldrh.u16 q1, [r0], #32
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vmovx.f16 s10, s7
; CHECK-NEXT: vmovx.f16 s12, s10 ; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vcvtb.f32.f16 s18, s11 ; CHECK-NEXT: vcvtb.f32.f16 s15, s10
; CHECK-NEXT: vcvtb.f32.f16 s17, s12 ; CHECK-NEXT: vcvtb.f32.f16 s14, s7
; CHECK-NEXT: vmov.16 q1[3], r2 ; CHECK-NEXT: vcvtb.f32.f16 s13, s8
; CHECK-NEXT: vcvtb.f32.f16 s16, s10 ; CHECK-NEXT: vcvtb.f32.f16 s12, s6
; CHECK-NEXT: vmul.f32 q2, q4, q0 ; CHECK-NEXT: vmul.f32 q2, q3, q0
; CHECK-NEXT: vcvtb.f16.f32 s12, s8 ; CHECK-NEXT: vcvtb.f16.f32 q2, q2
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vstrh.32 q2, [r1, #8]
; CHECK-NEXT: vcvtb.f16.f32 s12, s9 ; CHECK-NEXT: vmovx.f16 s10, s5
; CHECK-NEXT: vmov.16 q1[4], r2 ; CHECK-NEXT: vcvtb.f32.f16 s15, s10
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vcvtb.f16.f32 s12, s10 ; CHECK-NEXT: vcvtb.f32.f16 s14, s5
; CHECK-NEXT: vmov.16 q1[5], r2 ; CHECK-NEXT: vcvtb.f32.f16 s13, s8
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vcvtb.f32.f16 s12, s4
; CHECK-NEXT: vcvtb.f16.f32 s8, s11 ; CHECK-NEXT: vmul.f32 q1, q3, q0
; CHECK-NEXT: vmov.16 q1[6], r2 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vstrh.32 q1, [r1], #32
; CHECK-NEXT: vldrh.u16 q2, [r0], #32
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vstrh.16 q1, [r1, #16]
; CHECK-NEXT: vmovx.f16 s6, s9
; CHECK-NEXT: vmovx.f16 s4, s8
; CHECK-NEXT: vcvtb.f32.f16 s15, s6
; CHECK-NEXT: vcvtb.f32.f16 s14, s9
; CHECK-NEXT: vcvtb.f32.f16 s13, s4
; CHECK-NEXT: vcvtb.f32.f16 s12, s8
; CHECK-NEXT: vmul.f32 q3, q3, q0
; CHECK-NEXT: vcvtb.f16.f32 s4, s12
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vcvtb.f16.f32 s4, s13
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.16 q1[0], r2
; CHECK-NEXT: vcvtb.f16.f32 s16, s14
; CHECK-NEXT: vcvtb.f16.f32 s12, s15
; CHECK-NEXT: vmovx.f16 s14, s11
; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vcvtb.f32.f16 s19, s14
; CHECK-NEXT: vmov.16 q1[1], r3
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmovx.f16 s12, s10
; CHECK-NEXT: vcvtb.f32.f16 s18, s11
; CHECK-NEXT: vcvtb.f32.f16 s17, s12
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vcvtb.f32.f16 s16, s10
; CHECK-NEXT: vmul.f32 q2, q4, q0
; CHECK-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s9
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s12, s10
; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vstrh.16 q1, [r1], #32
; CHECK-NEXT: le lr, .LBB8_1 ; CHECK-NEXT: le lr, .LBB8_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: .LCPI8_0: ; CHECK-NEXT: .LCPI8_0:
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
; CHECK-NEXT: .long 0x40066666 @ float 2.0999999 ; CHECK-NEXT: .long 0x40066666 @ float 2.0999999
▲ Show 20 Lines • Show All 177 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

Show First 20 Lines • Show All 339 Lines • ▼ Show 20 Lines
} }
define arm_aapcs_vfpcc void @store_trunc_4(<4 x half>* %src, <4 x float> %val) { define arm_aapcs_vfpcc void @store_trunc_4(<4 x half>* %src, <4 x float> %val) {
; CHECK-LABEL: store_trunc_4: ; CHECK-LABEL: store_trunc_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvtb.f16.f32 s4, s0 ; CHECK-NEXT: vcvtb.f16.f32 q0, q0
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: vcvtb.f16.f32 s4, s1
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov.16 q1[0], r1
; CHECK-NEXT: vcvtb.f16.f32 s8, s2
; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vcvtb.f16.f32 s0, s3
; CHECK-NEXT: vmov.16 q1[2], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: strd r1, r2, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%e = fptrunc <4 x float> %val to <4 x half> %e = fptrunc <4 x float> %val to <4 x half>
store <4 x half> %e, <4 x half>* %src, align 4 store <4 x half> %e, <4 x half>* %src, align 4
ret void ret void
} }
define arm_aapcs_vfpcc void @store_trunc_8(<8 x half>* %src, <8 x float> %val) { define arm_aapcs_vfpcc void @store_trunc_8(<8 x half>* %src, <8 x float> %val) {
; CHECK-LABEL: store_trunc_8: ; CHECK-LABEL: store_trunc_8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvtb.f16.f32 s8, s0 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov r1, s8 ; CHECK-NEXT: vcvtb.f16.f32 q0, q0
; CHECK-NEXT: vcvtb.f16.f32 s8, s1 ; CHECK-NEXT: vstrh.32 q1, [r0, #8]
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: vmov.16 q2[0], r1
; CHECK-NEXT: vcvtb.f16.f32 s12, s2
; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov r1, s12
; CHECK-NEXT: vcvtb.f16.f32 s0, s3
; CHECK-NEXT: vmov.16 q2[2], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-NEXT: vmov.16 q2[3], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vcvtb.f16.f32 s0, s5
; CHECK-NEXT: vmov.16 q2[4], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vcvtb.f16.f32 s0, s6
; CHECK-NEXT: vmov.16 q2[5], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vcvtb.f16.f32 s0, s7
; CHECK-NEXT: vmov.16 q2[6], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q2[7], r1
; CHECK-NEXT: vstrw.32 q2, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%e = fptrunc <8 x float> %val to <8 x half> %e = fptrunc <8 x float> %val to <8 x half>
store <8 x half> %e, <8 x half>* %src, align 4 store <8 x half> %e, <8 x half>* %src, align 4
ret void ret void
} }
define arm_aapcs_vfpcc void @store_trunc_16(<16 x half>* %src, <16 x float> %val) { define arm_aapcs_vfpcc void @store_trunc_16(<16 x half>* %src, <16 x float> %val) {
; CHECK-LABEL: store_trunc_16: ; CHECK-LABEL: store_trunc_16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10} ; CHECK-NEXT: vcvtb.f16.f32 q3, q3
; CHECK-NEXT: vpush {d8, d9, d10} ; CHECK-NEXT: vcvtb.f16.f32 q2, q2
; CHECK-NEXT: vcvtb.f16.f32 s16, s8 ; CHECK-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-NEXT: vmov r1, s16 ; CHECK-NEXT: vcvtb.f16.f32 q0, q0
; CHECK-NEXT: vcvtb.f16.f32 s16, s9 ; CHECK-NEXT: vstrh.32 q3, [r0, #24]
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vstrh.32 q2, [r0, #16]
; CHECK-NEXT: vmov.16 q4[0], r1 ; CHECK-NEXT: vstrh.32 q1, [r0, #8]
; CHECK-NEXT: vcvtb.f16.f32 s20, s10 ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: vmov.16 q4[1], r2
; CHECK-NEXT: vmov r1, s20
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q4[2], r1
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vcvtb.f16.f32 s8, s12
; CHECK-NEXT: vmov.16 q4[3], r1
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vcvtb.f16.f32 s8, s13
; CHECK-NEXT: vmov.16 q4[4], r1
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vcvtb.f16.f32 s8, s14
; CHECK-NEXT: vmov.16 q4[5], r1
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vcvtb.f16.f32 s8, s15
; CHECK-NEXT: vmov.16 q4[6], r1
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vmov.16 q4[7], r1
; CHECK-NEXT: vstrw.32 q4, [r0, #16]
; CHECK-NEXT: vcvtb.f16.f32 s8, s0
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vcvtb.f16.f32 s8, s1
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q2[0], r1
; CHECK-NEXT: vcvtb.f16.f32 s12, s2
; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov r1, s12
; CHECK-NEXT: vcvtb.f16.f32 s0, s3
; CHECK-NEXT: vmov.16 q2[2], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-NEXT: vmov.16 q2[3], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vcvtb.f16.f32 s0, s5
; CHECK-NEXT: vmov.16 q2[4], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vcvtb.f16.f32 s0, s6
; CHECK-NEXT: vmov.16 q2[5], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vcvtb.f16.f32 s0, s7
; CHECK-NEXT: vmov.16 q2[6], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q2[7], r1
; CHECK-NEXT: vstrw.32 q2, [r0]
; CHECK-NEXT: vpop {d8, d9, d10}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%e = fptrunc <16 x float> %val to <16 x half> %e = fptrunc <16 x float> %val to <16 x half>
store <16 x half> %e, <16 x half>* %src, align 4 store <16 x half> %e, <16 x half>* %src, align 4
ret void ret void
} }
define arm_aapcs_vfpcc void @store_shuffletrunc_8(<8 x half>* %src, <4 x float> %val1, <4 x float> %val2) { define arm_aapcs_vfpcc void @store_shuffletrunc_8(<8 x half>* %src, <4 x float> %val1, <4 x float> %val2) {
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