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Differential D81012

[AMDGPU] More accurate gfx10 latencies
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Authored by foad on Jun 2 2020, 7:51 AM.

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arsenm
rampitec
nhaehnle
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rG590964c8353e: [AMDGPU] More accurate gfx10 latencies

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foad created this revision.Jun 2 2020, 7:51 AM
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Harbormaster failed remote builds in B58772: Diff 267891!Jun 2 2020, 8:47 AM
foad added a parent revision: D81011: [AMDGPU] Introduce new sched classes for transcendental instructions.Jun 2 2020, 9:01 AM
rampitec accepted this revision.Jun 2 2020, 10:30 AM
This revision is now accepted and ready to land.Jun 2 2020, 10:30 AM
Closed by commit rG590964c8353e: [AMDGPU] More accurate gfx10 latencies (authored by foad). · Explain WhyJun 4 2020, 2:40 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 268401

llvm/lib/Target/AMDGPU/SISchedule.td

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} // End SchedModel = SIQuarterSpeedModel } // End SchedModel = SIQuarterSpeedModel
let SchedModel = GFX10SpeedModel in { let SchedModel = GFX10SpeedModel in {
// The latency values are 1 / (operations / cycle). // The latency values are 1 / (operations / cycle).
// Add 1 stall cycle for VGPR read. // Add 1 stall cycle for VGPR read.
def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>; def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>;
def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>; def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>;
def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 9>; def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 6>;
def : HWWriteRes<WriteTrans32, [HWVALU, HWRC], 17>; def : HWWriteRes<WriteTrans32, [HWVALU, HWRC], 10>;
def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 17>; def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 8>;
def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>; def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>;
def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 17>; def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 22>;
def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 17>; def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 22>;
def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 17>; def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 22>;
def : HWWriteRes<WriteTrans64, [HWVALU, HWRC], 17>; def : HWWriteRes<WriteTrans64, [HWVALU, HWRC], 24>;
def : HWWriteRes<WriteBranch, [HWBranch], 32>; def : HWWriteRes<WriteBranch, [HWBranch], 32>;
def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>; def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>;
def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>; def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>;
def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 5>; def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>;
def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>; def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>;
def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>; def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>;
def : HWWriteRes<WriteBarrier, [HWBranch], 2000>; def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;
def : InstRW<[WriteCopy], (instrs COPY)>; def : InstRW<[WriteCopy], (instrs COPY)>;
} // End SchedModel = GFX10SpeedModel } // End SchedModel = GFX10SpeedModel

llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll

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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s6, s33 ; GFX10-NEXT: s_mov_b32 s6, s33
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_add_u32 s32, s32, 0x200 ; GFX10-NEXT: s_add_u32 s32, s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+4 ; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_mov_b32 s33, s6 ; GFX10-NEXT: s_mov_b32 s33, s6
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshl2_add_u32 s4, s4, 15 ; GFX10-NEXT: s_lshl2_add_u32 s4, s4, 15
; GFX10-NEXT: s_and_b32 s4, s4, -16 ; GFX10-NEXT: s_and_b32 s4, s4, -16
; GFX10-NEXT: s_lshl_b32 s4, s4, 5 ; GFX10-NEXT: s_lshl_b32 s4, s4, 5
; GFX10-NEXT: s_add_u32 s4, s32, s4 ; GFX10-NEXT: s_add_u32 s4, s32, s4
; GFX10-NEXT: s_sub_u32 s32, s32, 0x200 ; GFX10-NEXT: s_sub_u32 s32, s32, 0x200
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s6, s33 ; GFX10-NEXT: s_mov_b32 s6, s33
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_add_u32 s32, s32, 0x200 ; GFX10-NEXT: s_add_u32 s32, s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+4 ; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_mov_b32 s33, s6 ; GFX10-NEXT: s_mov_b32 s33, s6
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshl2_add_u32 s4, s4, 15 ; GFX10-NEXT: s_lshl2_add_u32 s4, s4, 15
; GFX10-NEXT: s_and_b32 s4, s4, -16 ; GFX10-NEXT: s_and_b32 s4, s4, -16
; GFX10-NEXT: s_lshl_b32 s4, s4, 5 ; GFX10-NEXT: s_lshl_b32 s4, s4, 5
; GFX10-NEXT: s_add_u32 s4, s32, s4 ; GFX10-NEXT: s_add_u32 s4, s32, s4
; GFX10-NEXT: s_sub_u32 s32, s32, 0x200 ; GFX10-NEXT: s_sub_u32 s32, s32, 0x200
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: func_dynamic_stackalloc_sgpr_align32: ; GFX10-LABEL: func_dynamic_stackalloc_sgpr_align32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_add_u32 s4, s32, 0x3e0 ; GFX10-NEXT: s_add_u32 s4, s32, 0x3e0
; GFX10-NEXT: s_mov_b32 s6, s33 ; GFX10-NEXT: s_mov_b32 s6, s33
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_and_b32 s33, s4, 0xfffffc00 ; GFX10-NEXT: s_and_b32 s33, s4, 0xfffffc00
; GFX10-NEXT: s_add_u32 s32, s32, 0x800 ; GFX10-NEXT: s_add_u32 s32, s32, 0x800
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+4 ; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+4
; GFX10-NEXT: s_mov_b32 s33, s6 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_mov_b32 s33, s6
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshl2_add_u32 s4, s4, 15 ; GFX10-NEXT: s_lshl2_add_u32 s4, s4, 15
; GFX10-NEXT: s_and_b32 s4, s4, -16 ; GFX10-NEXT: s_and_b32 s4, s4, -16
; GFX10-NEXT: s_lshl_b32 s4, s4, 5 ; GFX10-NEXT: s_lshl_b32 s4, s4, 5
; GFX10-NEXT: s_add_u32 s4, s32, s4 ; GFX10-NEXT: s_add_u32 s4, s32, s4
; GFX10-NEXT: s_and_b32 s4, s4, 0xfffffc00 ; GFX10-NEXT: s_and_b32 s4, s4, 0xfffffc00
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llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

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; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_mov_b32 s0, s2
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: v_mov_b32_e32 v16, s7 ; MOVREL-NEXT: v_mov_b32_e32 v16, s7
; MOVREL-NEXT: v_mov_b32_e32 v15, s6
; MOVREL-NEXT: v_mov_b32_e32 v14, s5 ; MOVREL-NEXT: v_mov_b32_e32 v14, s5
; MOVREL-NEXT: v_mov_b32_e32 v12, s3
; MOVREL-NEXT: v_mov_b32_e32 v13, s4 ; MOVREL-NEXT: v_mov_b32_e32 v13, s4
; MOVREL-NEXT: v_mov_b32_e32 v15, s6 ; MOVREL-NEXT: v_mov_b32_e32 v12, s3
; MOVREL-NEXT: v_mov_b32_e32 v11, s2 ; MOVREL-NEXT: v_mov_b32_e32 v11, s2
; MOVREL-NEXT: v_mov_b32_e32 v10, s1 ; MOVREL-NEXT: v_mov_b32_e32 v10, s1
; MOVREL-NEXT: v_mov_b32_e32 v9, s0 ; MOVREL-NEXT: v_mov_b32_e32 v9, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB3_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB3_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v0 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v0
; MOVREL-NEXT: v_mov_b32_e32 v1, v9 ; MOVREL-NEXT: v_mov_b32_e32 v1, v9
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; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_mov_b32 s0, s2
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: v_mov_b32_e32 v17, s7 ; MOVREL-NEXT: v_mov_b32_e32 v17, s7
; MOVREL-NEXT: v_mov_b32_e32 v16, s6
; MOVREL-NEXT: v_mov_b32_e32 v15, s5 ; MOVREL-NEXT: v_mov_b32_e32 v15, s5
; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v14, s4 ; MOVREL-NEXT: v_mov_b32_e32 v14, s4
; MOVREL-NEXT: v_mov_b32_e32 v16, s6 ; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v12, s2 ; MOVREL-NEXT: v_mov_b32_e32 v12, s2
; MOVREL-NEXT: v_mov_b32_e32 v11, s1 ; MOVREL-NEXT: v_mov_b32_e32 v11, s1
; MOVREL-NEXT: v_mov_b32_e32 v10, s0 ; MOVREL-NEXT: v_mov_b32_e32 v10, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB6_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB6_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v1 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
; MOVREL-NEXT: v_mov_b32_e32 v2, v10 ; MOVREL-NEXT: v_mov_b32_e32 v2, v10
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; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_const_s_v_v: ; MOVREL-LABEL: dyn_insertelement_v8f64_const_s_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0 ; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_mov_b32 s18, 0 ; MOVREL-NEXT: s_mov_b32 s18, 0
; MOVREL-NEXT: s_mov_b32 s19, 0x40200000 ; MOVREL-NEXT: s_mov_b32 s19, 0x40200000
; MOVREL-NEXT: s_mov_b32 s17, 0x401c0000 ; MOVREL-NEXT: s_mov_b32 s17, 0x401c0000
; MOVREL-NEXT: s_mov_b32 s15, 0x40180000
; MOVREL-NEXT: s_mov_b32 s13, 0x40140000
; MOVREL-NEXT: s_mov_b32 s16, s18 ; MOVREL-NEXT: s_mov_b32 s16, s18
; MOVREL-NEXT: s_mov_b32 s15, 0x40180000
; MOVREL-NEXT: s_mov_b32 s14, s18 ; MOVREL-NEXT: s_mov_b32 s14, s18
; MOVREL-NEXT: s_mov_b32 s13, 0x40140000
; MOVREL-NEXT: s_mov_b32 s12, s18 ; MOVREL-NEXT: s_mov_b32 s12, s18
; MOVREL-NEXT: s_mov_b64 s[10:11], 4.0 ; MOVREL-NEXT: s_mov_b64 s[10:11], 4.0
; MOVREL-NEXT: s_mov_b32 s9, 0x40080000 ; MOVREL-NEXT: s_mov_b32 s9, 0x40080000
; MOVREL-NEXT: s_mov_b32 s8, s18 ; MOVREL-NEXT: s_mov_b32 s8, s18
; MOVREL-NEXT: s_mov_b64 s[6:7], 2.0 ; MOVREL-NEXT: s_mov_b64 s[6:7], 2.0
; MOVREL-NEXT: s_mov_b64 s[4:5], 1.0 ; MOVREL-NEXT: s_mov_b64 s[4:5], 1.0
; MOVREL-NEXT: v_mov_b32_e32 v34, s19 ; MOVREL-NEXT: v_mov_b32_e32 v34, s19
; MOVREL-NEXT: v_mov_b32_e32 v33, s18 ; MOVREL-NEXT: v_mov_b32_e32 v33, s18
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; MOVREL-NEXT: s_mov_b32 s4, exec_lo ; MOVREL-NEXT: s_mov_b32 s4, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB13_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB13_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s5, v2 ; MOVREL-NEXT: v_readfirstlane_b32 s5, v2
; MOVREL-NEXT: v_mov_b32_e32 v3, v19 ; MOVREL-NEXT: v_mov_b32_e32 v3, v19
; MOVREL-NEXT: v_mov_b32_e32 v4, v20 ; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: s_lshl_b32 m0, s5, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s5, v2 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s5, v2
; MOVREL-NEXT: s_lshl_b32 m0, s5, 1
; MOVREL-NEXT: v_mov_b32_e32 v7, v23 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24 ; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25 ; MOVREL-NEXT: v_mov_b32_e32 v9, v25
; MOVREL-NEXT: v_mov_b32_e32 v10, v26 ; MOVREL-NEXT: v_mov_b32_e32 v10, v26
; MOVREL-NEXT: v_mov_b32_e32 v11, v27 ; MOVREL-NEXT: v_mov_b32_e32 v11, v27
; MOVREL-NEXT: v_mov_b32_e32 v12, v28 ; MOVREL-NEXT: v_mov_b32_e32 v12, v28
; MOVREL-NEXT: v_mov_b32_e32 v13, v29 ; MOVREL-NEXT: v_mov_b32_e32 v13, v29
; MOVREL-NEXT: v_mov_b32_e32 v14, v30 ; MOVREL-NEXT: v_mov_b32_e32 v14, v30
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; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_mov_b32 s8, s10 ; MOVREL-NEXT: s_mov_b32 s8, s10
; MOVREL-NEXT: s_mov_b32 s10, s12 ; MOVREL-NEXT: s_mov_b32 s10, s12
; MOVREL-NEXT: s_mov_b32 s12, s14 ; MOVREL-NEXT: s_mov_b32 s12, s14
; MOVREL-NEXT: s_mov_b32 s14, s16 ; MOVREL-NEXT: s_mov_b32 s14, s16
; MOVREL-NEXT: v_mov_b32_e32 v32, s15 ; MOVREL-NEXT: v_mov_b32_e32 v32, s15
; MOVREL-NEXT: v_mov_b32_e32 v31, s14
; MOVREL-NEXT: v_mov_b32_e32 v30, s13 ; MOVREL-NEXT: v_mov_b32_e32 v30, s13
; MOVREL-NEXT: v_mov_b32_e32 v28, s11
; MOVREL-NEXT: v_mov_b32_e32 v29, s12 ; MOVREL-NEXT: v_mov_b32_e32 v29, s12
; MOVREL-NEXT: v_mov_b32_e32 v31, s14 ; MOVREL-NEXT: v_mov_b32_e32 v28, s11
; MOVREL-NEXT: v_mov_b32_e32 v27, s10 ; MOVREL-NEXT: v_mov_b32_e32 v27, s10
; MOVREL-NEXT: v_mov_b32_e32 v26, s9 ; MOVREL-NEXT: v_mov_b32_e32 v26, s9
; MOVREL-NEXT: v_mov_b32_e32 v25, s8 ; MOVREL-NEXT: v_mov_b32_e32 v25, s8
; MOVREL-NEXT: v_mov_b32_e32 v24, s7 ; MOVREL-NEXT: v_mov_b32_e32 v24, s7
; MOVREL-NEXT: v_mov_b32_e32 v23, s6 ; MOVREL-NEXT: v_mov_b32_e32 v23, s6
; MOVREL-NEXT: v_mov_b32_e32 v22, s5 ; MOVREL-NEXT: v_mov_b32_e32 v22, s5
; MOVREL-NEXT: v_mov_b32_e32 v21, s4 ; MOVREL-NEXT: v_mov_b32_e32 v21, s4
; MOVREL-NEXT: v_mov_b32_e32 v20, s3 ; MOVREL-NEXT: v_mov_b32_e32 v20, s3
; MOVREL-NEXT: v_mov_b32_e32 v19, s2 ; MOVREL-NEXT: v_mov_b32_e32 v19, s2
; MOVREL-NEXT: v_mov_b32_e32 v18, s1 ; MOVREL-NEXT: v_mov_b32_e32 v18, s1
; MOVREL-NEXT: v_mov_b32_e32 v17, s0 ; MOVREL-NEXT: v_mov_b32_e32 v17, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB14_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB14_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v0 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v0
; MOVREL-NEXT: v_mov_b32_e32 v1, v17 ; MOVREL-NEXT: v_mov_b32_e32 v1, v17
; MOVREL-NEXT: v_mov_b32_e32 v2, v18 ; MOVREL-NEXT: v_mov_b32_e32 v2, v18
; MOVREL-NEXT: v_mov_b32_e32 v3, v19 ; MOVREL-NEXT: v_mov_b32_e32 v3, v19
; MOVREL-NEXT: v_mov_b32_e32 v4, v20 ; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v0
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: v_mov_b32_e32 v7, v23 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24 ; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25 ; MOVREL-NEXT: v_mov_b32_e32 v9, v25
; MOVREL-NEXT: v_mov_b32_e32 v10, v26 ; MOVREL-NEXT: v_mov_b32_e32 v10, v26
; MOVREL-NEXT: v_mov_b32_e32 v11, v27 ; MOVREL-NEXT: v_mov_b32_e32 v11, v27
; MOVREL-NEXT: v_mov_b32_e32 v12, v28 ; MOVREL-NEXT: v_mov_b32_e32 v12, v28
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; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_mov_b32 s8, s10 ; MOVREL-NEXT: s_mov_b32 s8, s10
; MOVREL-NEXT: s_mov_b32 s10, s12 ; MOVREL-NEXT: s_mov_b32 s10, s12
; MOVREL-NEXT: s_mov_b32 s12, s14 ; MOVREL-NEXT: s_mov_b32 s12, s14
; MOVREL-NEXT: s_mov_b32 s14, s16 ; MOVREL-NEXT: s_mov_b32 s14, s16
; MOVREL-NEXT: v_mov_b32_e32 v17, s15 ; MOVREL-NEXT: v_mov_b32_e32 v17, s15
; MOVREL-NEXT: v_mov_b32_e32 v2, s0 ; MOVREL-NEXT: v_mov_b32_e32 v2, s0
; MOVREL-NEXT: s_lshl_b32 m0, s18, 1 ; MOVREL-NEXT: s_lshl_b32 m0, s18, 1
; MOVREL-NEXT: v_mov_b32_e32 v15, s13
; MOVREL-NEXT: v_mov_b32_e32 v16, s14 ; MOVREL-NEXT: v_mov_b32_e32 v16, s14
; MOVREL-NEXT: v_mov_b32_e32 v15, s13
; MOVREL-NEXT: v_mov_b32_e32 v14, s12 ; MOVREL-NEXT: v_mov_b32_e32 v14, s12
; MOVREL-NEXT: v_mov_b32_e32 v13, s11 ; MOVREL-NEXT: v_mov_b32_e32 v13, s11
; MOVREL-NEXT: v_mov_b32_e32 v12, s10 ; MOVREL-NEXT: v_mov_b32_e32 v12, s10
; MOVREL-NEXT: v_mov_b32_e32 v11, s9 ; MOVREL-NEXT: v_mov_b32_e32 v11, s9
; MOVREL-NEXT: v_mov_b32_e32 v10, s8 ; MOVREL-NEXT: v_mov_b32_e32 v10, s8
; MOVREL-NEXT: v_mov_b32_e32 v9, s7 ; MOVREL-NEXT: v_mov_b32_e32 v9, s7
; MOVREL-NEXT: v_mov_b32_e32 v8, s6 ; MOVREL-NEXT: v_mov_b32_e32 v8, s6
; MOVREL-NEXT: v_mov_b32_e32 v7, s5 ; MOVREL-NEXT: v_mov_b32_e32 v7, s5
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; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_mov_b32 s8, s10 ; MOVREL-NEXT: s_mov_b32 s8, s10
; MOVREL-NEXT: s_mov_b32 s10, s12 ; MOVREL-NEXT: s_mov_b32 s10, s12
; MOVREL-NEXT: s_mov_b32 s12, s14 ; MOVREL-NEXT: s_mov_b32 s12, s14
; MOVREL-NEXT: s_mov_b32 s14, s16 ; MOVREL-NEXT: s_mov_b32 s14, s16
; MOVREL-NEXT: v_mov_b32_e32 v34, s15 ; MOVREL-NEXT: v_mov_b32_e32 v34, s15
; MOVREL-NEXT: v_mov_b32_e32 v33, s14
; MOVREL-NEXT: v_mov_b32_e32 v32, s13 ; MOVREL-NEXT: v_mov_b32_e32 v32, s13
; MOVREL-NEXT: v_mov_b32_e32 v30, s11
; MOVREL-NEXT: v_mov_b32_e32 v31, s12 ; MOVREL-NEXT: v_mov_b32_e32 v31, s12
; MOVREL-NEXT: v_mov_b32_e32 v33, s14 ; MOVREL-NEXT: v_mov_b32_e32 v30, s11
; MOVREL-NEXT: v_mov_b32_e32 v29, s10 ; MOVREL-NEXT: v_mov_b32_e32 v29, s10
; MOVREL-NEXT: v_mov_b32_e32 v28, s9 ; MOVREL-NEXT: v_mov_b32_e32 v28, s9
; MOVREL-NEXT: v_mov_b32_e32 v27, s8 ; MOVREL-NEXT: v_mov_b32_e32 v27, s8
; MOVREL-NEXT: v_mov_b32_e32 v26, s7 ; MOVREL-NEXT: v_mov_b32_e32 v26, s7
; MOVREL-NEXT: v_mov_b32_e32 v25, s6 ; MOVREL-NEXT: v_mov_b32_e32 v25, s6
; MOVREL-NEXT: v_mov_b32_e32 v24, s5 ; MOVREL-NEXT: v_mov_b32_e32 v24, s5
; MOVREL-NEXT: v_mov_b32_e32 v23, s4 ; MOVREL-NEXT: v_mov_b32_e32 v23, s4
; MOVREL-NEXT: v_mov_b32_e32 v22, s3 ; MOVREL-NEXT: v_mov_b32_e32 v22, s3
; MOVREL-NEXT: v_mov_b32_e32 v21, s2 ; MOVREL-NEXT: v_mov_b32_e32 v21, s2
; MOVREL-NEXT: v_mov_b32_e32 v20, s1 ; MOVREL-NEXT: v_mov_b32_e32 v20, s1
; MOVREL-NEXT: v_mov_b32_e32 v19, s0 ; MOVREL-NEXT: v_mov_b32_e32 v19, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB17_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB17_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v2 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v2
; MOVREL-NEXT: v_mov_b32_e32 v3, v19 ; MOVREL-NEXT: v_mov_b32_e32 v3, v19
; MOVREL-NEXT: v_mov_b32_e32 v4, v20 ; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v7, v23 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24 ; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25 ; MOVREL-NEXT: v_mov_b32_e32 v9, v25
; MOVREL-NEXT: v_mov_b32_e32 v10, v26 ; MOVREL-NEXT: v_mov_b32_e32 v10, v26
; MOVREL-NEXT: v_mov_b32_e32 v11, v27 ; MOVREL-NEXT: v_mov_b32_e32 v11, v27
; MOVREL-NEXT: v_mov_b32_e32 v12, v28 ; MOVREL-NEXT: v_mov_b32_e32 v12, v28
; MOVREL-NEXT: v_mov_b32_e32 v13, v29 ; MOVREL-NEXT: v_mov_b32_e32 v13, v29
; MOVREL-NEXT: v_mov_b32_e32 v14, v30 ; MOVREL-NEXT: v_mov_b32_e32 v14, v30
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; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB18_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB18_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v16 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v16
; MOVREL-NEXT: v_mov_b32_e32 v32, v15 ; MOVREL-NEXT: v_mov_b32_e32 v32, v15
; MOVREL-NEXT: v_mov_b32_e32 v17, v0 ; MOVREL-NEXT: v_mov_b32_e32 v17, v0
; MOVREL-NEXT: v_mov_b32_e32 v31, v14 ; MOVREL-NEXT: v_mov_b32_e32 v31, v14
; MOVREL-NEXT: v_mov_b32_e32 v30, v13 ; MOVREL-NEXT: v_mov_b32_e32 v30, v13
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v16 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v16
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v29, v12 ; MOVREL-NEXT: v_mov_b32_e32 v29, v12
; MOVREL-NEXT: v_mov_b32_e32 v28, v11 ; MOVREL-NEXT: v_mov_b32_e32 v28, v11
; MOVREL-NEXT: v_mov_b32_e32 v27, v10 ; MOVREL-NEXT: v_mov_b32_e32 v27, v10
; MOVREL-NEXT: v_mov_b32_e32 v26, v9 ; MOVREL-NEXT: v_mov_b32_e32 v26, v9
; MOVREL-NEXT: v_mov_b32_e32 v25, v8 ; MOVREL-NEXT: v_mov_b32_e32 v25, v8
; MOVREL-NEXT: v_mov_b32_e32 v24, v7 ; MOVREL-NEXT: v_mov_b32_e32 v24, v7
; MOVREL-NEXT: v_mov_b32_e32 v23, v6 ; MOVREL-NEXT: v_mov_b32_e32 v23, v6
; MOVREL-NEXT: v_mov_b32_e32 v22, v5 ; MOVREL-NEXT: v_mov_b32_e32 v22, v5
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; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB20_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB20_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v18 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v18
; MOVREL-NEXT: v_mov_b32_e32 v34, v15 ; MOVREL-NEXT: v_mov_b32_e32 v34, v15
; MOVREL-NEXT: v_mov_b32_e32 v19, v0 ; MOVREL-NEXT: v_mov_b32_e32 v19, v0
; MOVREL-NEXT: v_mov_b32_e32 v33, v14 ; MOVREL-NEXT: v_mov_b32_e32 v33, v14
; MOVREL-NEXT: v_mov_b32_e32 v32, v13 ; MOVREL-NEXT: v_mov_b32_e32 v32, v13
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v31, v12 ; MOVREL-NEXT: v_mov_b32_e32 v31, v12
; MOVREL-NEXT: v_mov_b32_e32 v30, v11 ; MOVREL-NEXT: v_mov_b32_e32 v30, v11
; MOVREL-NEXT: v_mov_b32_e32 v29, v10 ; MOVREL-NEXT: v_mov_b32_e32 v29, v10
; MOVREL-NEXT: v_mov_b32_e32 v28, v9 ; MOVREL-NEXT: v_mov_b32_e32 v28, v9
; MOVREL-NEXT: v_mov_b32_e32 v27, v8 ; MOVREL-NEXT: v_mov_b32_e32 v27, v8
; MOVREL-NEXT: v_mov_b32_e32 v26, v7 ; MOVREL-NEXT: v_mov_b32_e32 v26, v7
; MOVREL-NEXT: v_mov_b32_e32 v25, v6 ; MOVREL-NEXT: v_mov_b32_e32 v25, v6
; MOVREL-NEXT: v_mov_b32_e32 v24, v5 ; MOVREL-NEXT: v_mov_b32_e32 v24, v5
Show All 38 Lines
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v3i32_s_s_s: ; MOVREL-LABEL: dyn_insertelement_v3i32_s_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_mov_b32 s0, s2
; MOVREL-NEXT: s_mov_b32 m0, s6 ; MOVREL-NEXT: s_mov_b32 m0, s6
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_movreld_b32 s0, s5 ; MOVREL-NEXT: s_movreld_b32 s0, s5
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <3 x i32> %vec, i32 %val, i32 %idx %insert = insertelement <3 x i32> %vec, i32 %val, i32 %idx
ret <3 x i32> %insert ret <3 x i32> %insert
} }
define amdgpu_ps <3 x float> @dyn_insertelement_v3i32_v_v_s(<3 x float> %vec, float %val, i32 inreg %idx) { define amdgpu_ps <3 x float> @dyn_insertelement_v3i32_v_v_s(<3 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v3i32_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v3i32_v_v_s:
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; MOVREL-NEXT: BB32_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB32_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v18 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v18
; MOVREL-NEXT: v_mov_b32_e32 v34, v15 ; MOVREL-NEXT: v_mov_b32_e32 v34, v15
; MOVREL-NEXT: v_mov_b32_e32 v19, v0 ; MOVREL-NEXT: v_mov_b32_e32 v19, v0
; MOVREL-NEXT: v_mov_b32_e32 v33, v14 ; MOVREL-NEXT: v_mov_b32_e32 v33, v14
; MOVREL-NEXT: v_mov_b32_e32 v32, v13 ; MOVREL-NEXT: v_mov_b32_e32 v32, v13
; MOVREL-NEXT: s_add_i32 s2, s1, 1 ; MOVREL-NEXT: s_add_i32 s2, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_mov_b32_e32 v31, v12 ; MOVREL-NEXT: v_mov_b32_e32 v31, v12
; MOVREL-NEXT: v_mov_b32_e32 v30, v11 ; MOVREL-NEXT: v_mov_b32_e32 v30, v11
; MOVREL-NEXT: v_mov_b32_e32 v29, v10 ; MOVREL-NEXT: v_mov_b32_e32 v29, v10
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_mov_b32_e32 v28, v9 ; MOVREL-NEXT: v_mov_b32_e32 v28, v9
; MOVREL-NEXT: v_mov_b32_e32 v27, v8 ; MOVREL-NEXT: v_mov_b32_e32 v27, v8
; MOVREL-NEXT: v_mov_b32_e32 v26, v7 ; MOVREL-NEXT: v_mov_b32_e32 v26, v7
; MOVREL-NEXT: v_mov_b32_e32 v25, v6 ; MOVREL-NEXT: v_mov_b32_e32 v25, v6
; MOVREL-NEXT: v_mov_b32_e32 v24, v5 ; MOVREL-NEXT: v_mov_b32_e32 v24, v5
; MOVREL-NEXT: v_mov_b32_e32 v23, v4 ; MOVREL-NEXT: v_mov_b32_e32 v23, v4
; MOVREL-NEXT: v_mov_b32_e32 v22, v3 ; MOVREL-NEXT: v_mov_b32_e32 v22, v3
; MOVREL-NEXT: v_mov_b32_e32 v21, v2 ; MOVREL-NEXT: v_mov_b32_e32 v21, v2
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; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_mov_b32 s8, s10 ; MOVREL-NEXT: s_mov_b32 s8, s10
; MOVREL-NEXT: s_mov_b32 s10, s12 ; MOVREL-NEXT: s_mov_b32 s10, s12
; MOVREL-NEXT: s_mov_b32 s12, s14 ; MOVREL-NEXT: s_mov_b32 s12, s14
; MOVREL-NEXT: s_mov_b32 s14, s16 ; MOVREL-NEXT: s_mov_b32 s14, s16
; MOVREL-NEXT: v_mov_b32_e32 v16, s15 ; MOVREL-NEXT: v_mov_b32_e32 v16, s15
; MOVREL-NEXT: s_mov_b32 m0, s18
; MOVREL-NEXT: v_mov_b32_e32 v1, s0 ; MOVREL-NEXT: v_mov_b32_e32 v1, s0
; MOVREL-NEXT: v_mov_b32_e32 v14, s13 ; MOVREL-NEXT: s_mov_b32 m0, s18
; MOVREL-NEXT: v_mov_b32_e32 v15, s14 ; MOVREL-NEXT: v_mov_b32_e32 v15, s14
; MOVREL-NEXT: v_mov_b32_e32 v14, s13
; MOVREL-NEXT: v_mov_b32_e32 v13, s12 ; MOVREL-NEXT: v_mov_b32_e32 v13, s12
; MOVREL-NEXT: v_mov_b32_e32 v12, s11 ; MOVREL-NEXT: v_mov_b32_e32 v12, s11
; MOVREL-NEXT: v_mov_b32_e32 v11, s10 ; MOVREL-NEXT: v_mov_b32_e32 v11, s10
; MOVREL-NEXT: v_mov_b32_e32 v10, s9 ; MOVREL-NEXT: v_mov_b32_e32 v10, s9
; MOVREL-NEXT: v_mov_b32_e32 v9, s8 ; MOVREL-NEXT: v_mov_b32_e32 v9, s8
; MOVREL-NEXT: v_mov_b32_e32 v8, s7 ; MOVREL-NEXT: v_mov_b32_e32 v8, s7
; MOVREL-NEXT: v_mov_b32_e32 v7, s6 ; MOVREL-NEXT: v_mov_b32_e32 v7, s6
; MOVREL-NEXT: v_mov_b32_e32 v6, s5 ; MOVREL-NEXT: v_mov_b32_e32 v6, s5
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; MOVREL-NEXT: s_mov_b32 s23, s25 ; MOVREL-NEXT: s_mov_b32 s23, s25
; MOVREL-NEXT: s_mov_b32 s24, s26 ; MOVREL-NEXT: s_mov_b32 s24, s26
; MOVREL-NEXT: s_mov_b32 s25, s27 ; MOVREL-NEXT: s_mov_b32 s25, s27
; MOVREL-NEXT: s_mov_b32 s26, s28 ; MOVREL-NEXT: s_mov_b32 s26, s28
; MOVREL-NEXT: s_mov_b32 s27, s29 ; MOVREL-NEXT: s_mov_b32 s27, s29
; MOVREL-NEXT: s_mov_b32 s28, s30 ; MOVREL-NEXT: s_mov_b32 s28, s30
; MOVREL-NEXT: s_mov_b32 s29, s31 ; MOVREL-NEXT: s_mov_b32 s29, s31
; MOVREL-NEXT: s_mov_b32 s31, s33 ; MOVREL-NEXT: s_mov_b32 s31, s33
; MOVREL-NEXT: s_mov_b32 s30, s32
; MOVREL-NEXT: v_mov_b32_e32 v32, v0 ; MOVREL-NEXT: v_mov_b32_e32 v32, v0
; MOVREL-NEXT: s_mov_b32 s30, s32
; MOVREL-NEXT: v_mov_b32_e32 v0, s0 ; MOVREL-NEXT: v_mov_b32_e32 v0, s0
; MOVREL-NEXT: s_mov_b32 m0, s34 ; MOVREL-NEXT: s_mov_b32 m0, s34
; MOVREL-NEXT: v_mov_b32_e32 v1, s1 ; MOVREL-NEXT: v_mov_b32_e32 v1, s1
; MOVREL-NEXT: v_mov_b32_e32 v2, s2 ; MOVREL-NEXT: v_mov_b32_e32 v2, s2
; MOVREL-NEXT: v_mov_b32_e32 v3, s3 ; MOVREL-NEXT: v_mov_b32_e32 v3, s3
; MOVREL-NEXT: v_mov_b32_e32 v4, s4 ; MOVREL-NEXT: v_mov_b32_e32 v4, s4
; MOVREL-NEXT: v_mov_b32_e32 v5, s5 ; MOVREL-NEXT: v_mov_b32_e32 v5, s5
; MOVREL-NEXT: v_mov_b32_e32 v6, s6 ; MOVREL-NEXT: v_mov_b32_e32 v6, s6
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: s_mov_b32 s22, s24 ; MOVREL-NEXT: s_mov_b32 s22, s24
; MOVREL-NEXT: s_mov_b32 s24, s26 ; MOVREL-NEXT: s_mov_b32 s24, s26
; MOVREL-NEXT: s_mov_b32 s26, s28 ; MOVREL-NEXT: s_mov_b32 s26, s28
; MOVREL-NEXT: s_mov_b32 s28, s30 ; MOVREL-NEXT: s_mov_b32 s28, s30
; MOVREL-NEXT: s_mov_b32 s30, s32 ; MOVREL-NEXT: s_mov_b32 s30, s32
; MOVREL-NEXT: v_mov_b32_e32 v33, s31 ; MOVREL-NEXT: v_mov_b32_e32 v33, s31
; MOVREL-NEXT: v_mov_b32_e32 v2, s0 ; MOVREL-NEXT: v_mov_b32_e32 v2, s0
; MOVREL-NEXT: s_lshl_b32 m0, s34, 1 ; MOVREL-NEXT: s_lshl_b32 m0, s34, 1
; MOVREL-NEXT: v_mov_b32_e32 v31, s29
; MOVREL-NEXT: v_mov_b32_e32 v32, s30 ; MOVREL-NEXT: v_mov_b32_e32 v32, s30
; MOVREL-NEXT: v_mov_b32_e32 v31, s29
; MOVREL-NEXT: v_mov_b32_e32 v30, s28 ; MOVREL-NEXT: v_mov_b32_e32 v30, s28
; MOVREL-NEXT: v_mov_b32_e32 v29, s27 ; MOVREL-NEXT: v_mov_b32_e32 v29, s27
; MOVREL-NEXT: v_mov_b32_e32 v28, s26 ; MOVREL-NEXT: v_mov_b32_e32 v28, s26
; MOVREL-NEXT: v_mov_b32_e32 v27, s25 ; MOVREL-NEXT: v_mov_b32_e32 v27, s25
; MOVREL-NEXT: v_mov_b32_e32 v26, s24 ; MOVREL-NEXT: v_mov_b32_e32 v26, s24
; MOVREL-NEXT: v_mov_b32_e32 v25, s23 ; MOVREL-NEXT: v_mov_b32_e32 v25, s23
; MOVREL-NEXT: v_mov_b32_e32 v24, s22 ; MOVREL-NEXT: v_mov_b32_e32 v24, s22
; MOVREL-NEXT: v_mov_b32_e32 v23, s21 ; MOVREL-NEXT: v_mov_b32_e32 v23, s21
▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: s_mov_b32 s22, s24 ; MOVREL-NEXT: s_mov_b32 s22, s24
; MOVREL-NEXT: s_mov_b32 s24, s26 ; MOVREL-NEXT: s_mov_b32 s24, s26
; MOVREL-NEXT: s_mov_b32 s26, s28 ; MOVREL-NEXT: s_mov_b32 s26, s28
; MOVREL-NEXT: s_mov_b32 s28, s30 ; MOVREL-NEXT: s_mov_b32 s28, s30
; MOVREL-NEXT: s_mov_b32 s30, s32 ; MOVREL-NEXT: s_mov_b32 s30, s32
; MOVREL-NEXT: v_mov_b32_e32 v33, s31 ; MOVREL-NEXT: v_mov_b32_e32 v33, s31
; MOVREL-NEXT: v_mov_b32_e32 v2, s0 ; MOVREL-NEXT: v_mov_b32_e32 v2, s0
; MOVREL-NEXT: s_lshl_b32 m0, s34, 1 ; MOVREL-NEXT: s_lshl_b32 m0, s34, 1
; MOVREL-NEXT: v_mov_b32_e32 v31, s29
; MOVREL-NEXT: v_mov_b32_e32 v32, s30 ; MOVREL-NEXT: v_mov_b32_e32 v32, s30
; MOVREL-NEXT: v_mov_b32_e32 v31, s29
; MOVREL-NEXT: v_mov_b32_e32 v30, s28 ; MOVREL-NEXT: v_mov_b32_e32 v30, s28
; MOVREL-NEXT: v_mov_b32_e32 v29, s27 ; MOVREL-NEXT: v_mov_b32_e32 v29, s27
; MOVREL-NEXT: v_mov_b32_e32 v28, s26 ; MOVREL-NEXT: v_mov_b32_e32 v28, s26
; MOVREL-NEXT: v_mov_b32_e32 v27, s25 ; MOVREL-NEXT: v_mov_b32_e32 v27, s25
; MOVREL-NEXT: v_mov_b32_e32 v26, s24 ; MOVREL-NEXT: v_mov_b32_e32 v26, s24
; MOVREL-NEXT: v_mov_b32_e32 v25, s23 ; MOVREL-NEXT: v_mov_b32_e32 v25, s23
; MOVREL-NEXT: v_mov_b32_e32 v24, s22 ; MOVREL-NEXT: v_mov_b32_e32 v24, s22
; MOVREL-NEXT: v_mov_b32_e32 v23, s21 ; MOVREL-NEXT: v_mov_b32_e32 v23, s21
▲ Show 20 Lines • Show All 222 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_mov_b32 s0, s2
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: v_mov_b32_e32 v17, s7 ; MOVREL-NEXT: v_mov_b32_e32 v17, s7
; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v14, s4
; MOVREL-NEXT: v_mov_b32_e32 v15, s5
; MOVREL-NEXT: v_mov_b32_e32 v16, s6 ; MOVREL-NEXT: v_mov_b32_e32 v16, s6
; MOVREL-NEXT: v_mov_b32_e32 v15, s5
; MOVREL-NEXT: v_mov_b32_e32 v14, s4
; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v12, s2 ; MOVREL-NEXT: v_mov_b32_e32 v12, s2
; MOVREL-NEXT: v_mov_b32_e32 v11, s1 ; MOVREL-NEXT: v_mov_b32_e32 v11, s1
; MOVREL-NEXT: v_mov_b32_e32 v10, s0 ; MOVREL-NEXT: v_mov_b32_e32 v10, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB46_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB46_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v1 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
; MOVREL-NEXT: v_mov_b32_e32 v2, v10 ; MOVREL-NEXT: v_mov_b32_e32 v2, v10
▲ Show 20 Lines • Show All 362 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: s_mov_b32 s8, s10 ; MOVREL-NEXT: s_mov_b32 s8, s10
; MOVREL-NEXT: s_mov_b32 s9, s11 ; MOVREL-NEXT: s_mov_b32 s9, s11
; MOVREL-NEXT: s_mov_b32 s10, s12 ; MOVREL-NEXT: s_mov_b32 s10, s12
; MOVREL-NEXT: s_mov_b32 s11, s13 ; MOVREL-NEXT: s_mov_b32 s11, s13
; MOVREL-NEXT: s_mov_b32 s12, s14 ; MOVREL-NEXT: s_mov_b32 s12, s14
; MOVREL-NEXT: s_mov_b32 s13, s15 ; MOVREL-NEXT: s_mov_b32 s13, s15
; MOVREL-NEXT: v_mov_b32_e32 v34, s15 ; MOVREL-NEXT: v_mov_b32_e32 v34, s15
; MOVREL-NEXT: v_mov_b32_e32 v33, s14 ; MOVREL-NEXT: v_mov_b32_e32 v33, s14
; MOVREL-NEXT: v_mov_b32_e32 v30, s11
; MOVREL-NEXT: v_mov_b32_e32 v31, s12
; MOVREL-NEXT: v_mov_b32_e32 v32, s13 ; MOVREL-NEXT: v_mov_b32_e32 v32, s13
; MOVREL-NEXT: v_mov_b32_e32 v31, s12
; MOVREL-NEXT: v_mov_b32_e32 v30, s11
; MOVREL-NEXT: v_mov_b32_e32 v29, s10 ; MOVREL-NEXT: v_mov_b32_e32 v29, s10
; MOVREL-NEXT: v_mov_b32_e32 v28, s9 ; MOVREL-NEXT: v_mov_b32_e32 v28, s9
; MOVREL-NEXT: v_mov_b32_e32 v27, s8 ; MOVREL-NEXT: v_mov_b32_e32 v27, s8
; MOVREL-NEXT: v_mov_b32_e32 v26, s7 ; MOVREL-NEXT: v_mov_b32_e32 v26, s7
; MOVREL-NEXT: v_mov_b32_e32 v25, s6 ; MOVREL-NEXT: v_mov_b32_e32 v25, s6
; MOVREL-NEXT: v_mov_b32_e32 v24, s5 ; MOVREL-NEXT: v_mov_b32_e32 v24, s5
; MOVREL-NEXT: v_mov_b32_e32 v23, s4 ; MOVREL-NEXT: v_mov_b32_e32 v23, s4
; MOVREL-NEXT: v_mov_b32_e32 v22, s3 ; MOVREL-NEXT: v_mov_b32_e32 v22, s3
; MOVREL-NEXT: v_mov_b32_e32 v21, s2 ; MOVREL-NEXT: v_mov_b32_e32 v21, s2
; MOVREL-NEXT: v_mov_b32_e32 v20, s1 ; MOVREL-NEXT: v_mov_b32_e32 v20, s1
; MOVREL-NEXT: v_mov_b32_e32 v19, s0 ; MOVREL-NEXT: v_mov_b32_e32 v19, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB51_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB51_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v2 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v2
; MOVREL-NEXT: v_mov_b32_e32 v3, v19 ; MOVREL-NEXT: v_mov_b32_e32 v3, v19
; MOVREL-NEXT: v_mov_b32_e32 v4, v20 ; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v7, v23 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24 ; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25 ; MOVREL-NEXT: v_mov_b32_e32 v9, v25
; MOVREL-NEXT: v_mov_b32_e32 v10, v26 ; MOVREL-NEXT: v_mov_b32_e32 v10, v26
; MOVREL-NEXT: v_mov_b32_e32 v11, v27 ; MOVREL-NEXT: v_mov_b32_e32 v11, v27
; MOVREL-NEXT: v_mov_b32_e32 v12, v28 ; MOVREL-NEXT: v_mov_b32_e32 v12, v28
; MOVREL-NEXT: v_mov_b32_e32 v13, v29 ; MOVREL-NEXT: v_mov_b32_e32 v13, v29
; MOVREL-NEXT: v_mov_b32_e32 v14, v30 ; MOVREL-NEXT: v_mov_b32_e32 v14, v30
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: v_readfirstlane_b32 s10, v10 ; GPRIDX-NEXT: v_readfirstlane_b32 s10, v10
; GPRIDX-NEXT: v_readfirstlane_b32 s11, v11 ; GPRIDX-NEXT: v_readfirstlane_b32 s11, v11
; GPRIDX-NEXT: v_readfirstlane_b32 s12, v12 ; GPRIDX-NEXT: v_readfirstlane_b32 s12, v12
; GPRIDX-NEXT: v_readfirstlane_b32 s13, v13 ; GPRIDX-NEXT: v_readfirstlane_b32 s13, v13
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v7f64_v_v_s: ; MOVREL-LABEL: dyn_insertelement_v7f64_v_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_mov_b32_e32 v16, v15 ; MOVREL-NEXT: v_mov_b32_e32 v16, v15
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v14 ; MOVREL-NEXT: v_movreld_b32_e32 v0, v14
; MOVREL-NEXT: v_movreld_b32_e32 v1, v16 ; MOVREL-NEXT: v_movreld_b32_e32 v1, v16
; MOVREL-NEXT: v_readfirstlane_b32 s0, v0 ; MOVREL-NEXT: v_readfirstlane_b32 s0, v0
; MOVREL-NEXT: v_readfirstlane_b32 s1, v1 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
; MOVREL-NEXT: v_readfirstlane_b32 s2, v2 ; MOVREL-NEXT: v_readfirstlane_b32 s2, v2
; MOVREL-NEXT: v_readfirstlane_b32 s3, v3 ; MOVREL-NEXT: v_readfirstlane_b32 s3, v3
; MOVREL-NEXT: v_readfirstlane_b32 s4, v4 ; MOVREL-NEXT: v_readfirstlane_b32 s4, v4
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB53_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB53_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v16 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v16
; MOVREL-NEXT: v_mov_b32_e32 v32, v15 ; MOVREL-NEXT: v_mov_b32_e32 v32, v15
; MOVREL-NEXT: v_mov_b32_e32 v17, v0 ; MOVREL-NEXT: v_mov_b32_e32 v17, v0
; MOVREL-NEXT: v_mov_b32_e32 v31, v14 ; MOVREL-NEXT: v_mov_b32_e32 v31, v14
; MOVREL-NEXT: v_mov_b32_e32 v30, v13 ; MOVREL-NEXT: v_mov_b32_e32 v30, v13
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v16 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v16
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v29, v12 ; MOVREL-NEXT: v_mov_b32_e32 v29, v12
; MOVREL-NEXT: v_mov_b32_e32 v28, v11 ; MOVREL-NEXT: v_mov_b32_e32 v28, v11
; MOVREL-NEXT: v_mov_b32_e32 v27, v10 ; MOVREL-NEXT: v_mov_b32_e32 v27, v10
; MOVREL-NEXT: v_mov_b32_e32 v26, v9 ; MOVREL-NEXT: v_mov_b32_e32 v26, v9
; MOVREL-NEXT: v_mov_b32_e32 v25, v8 ; MOVREL-NEXT: v_mov_b32_e32 v25, v8
; MOVREL-NEXT: v_mov_b32_e32 v24, v7 ; MOVREL-NEXT: v_mov_b32_e32 v24, v7
; MOVREL-NEXT: v_mov_b32_e32 v23, v6 ; MOVREL-NEXT: v_mov_b32_e32 v23, v6
; MOVREL-NEXT: v_mov_b32_e32 v22, v5 ; MOVREL-NEXT: v_mov_b32_e32 v22, v5
▲ Show 20 Lines • Show All 265 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB56_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB56_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v2 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v2
; MOVREL-NEXT: v_mov_b32_e32 v3, v19 ; MOVREL-NEXT: v_mov_b32_e32 v3, v19
; MOVREL-NEXT: v_mov_b32_e32 v4, v20 ; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v7, v23 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24 ; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25 ; MOVREL-NEXT: v_mov_b32_e32 v9, v25
; MOVREL-NEXT: v_mov_b32_e32 v10, v26 ; MOVREL-NEXT: v_mov_b32_e32 v10, v26
; MOVREL-NEXT: v_mov_b32_e32 v11, v27 ; MOVREL-NEXT: v_mov_b32_e32 v11, v27
; MOVREL-NEXT: v_mov_b32_e32 v12, v28 ; MOVREL-NEXT: v_mov_b32_e32 v12, v28
; MOVREL-NEXT: v_mov_b32_e32 v13, v29 ; MOVREL-NEXT: v_mov_b32_e32 v13, v29
; MOVREL-NEXT: v_mov_b32_e32 v14, v30 ; MOVREL-NEXT: v_mov_b32_e32 v14, v30
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6 ; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7 ; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8 ; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9 ; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_s: ; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_mov_b32_e32 v16, v11 ; MOVREL-NEXT: v_mov_b32_e32 v16, v11
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v10 ; MOVREL-NEXT: v_movreld_b32_e32 v0, v10
; MOVREL-NEXT: v_movreld_b32_e32 v1, v16 ; MOVREL-NEXT: v_movreld_b32_e32 v1, v16
; MOVREL-NEXT: v_readfirstlane_b32 s0, v0 ; MOVREL-NEXT: v_readfirstlane_b32 s0, v0
; MOVREL-NEXT: v_readfirstlane_b32 s1, v1 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
; MOVREL-NEXT: v_readfirstlane_b32 s2, v2 ; MOVREL-NEXT: v_readfirstlane_b32 s2, v2
; MOVREL-NEXT: v_readfirstlane_b32 s3, v3 ; MOVREL-NEXT: v_readfirstlane_b32 s3, v3
; MOVREL-NEXT: v_readfirstlane_b32 s4, v4 ; MOVREL-NEXT: v_readfirstlane_b32 s4, v4
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: v_mov_b32_e32 v20, v7 ; MOVREL-NEXT: v_mov_b32_e32 v20, v7
; MOVREL-NEXT: v_mov_b32_e32 v19, v6 ; MOVREL-NEXT: v_mov_b32_e32 v19, v6
; MOVREL-NEXT: v_mov_b32_e32 v18, v5 ; MOVREL-NEXT: v_mov_b32_e32 v18, v5
; MOVREL-NEXT: v_mov_b32_e32 v17, v4 ; MOVREL-NEXT: v_mov_b32_e32 v17, v4
; MOVREL-NEXT: v_mov_b32_e32 v16, v3 ; MOVREL-NEXT: v_mov_b32_e32 v16, v3
; MOVREL-NEXT: v_mov_b32_e32 v15, v2 ; MOVREL-NEXT: v_mov_b32_e32 v15, v2
; MOVREL-NEXT: v_mov_b32_e32 v14, v1 ; MOVREL-NEXT: v_mov_b32_e32 v14, v1
; MOVREL-NEXT: v_mov_b32_e32 v13, v0 ; MOVREL-NEXT: v_mov_b32_e32 v13, v0
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v12 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v12
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_movreld_b32_e32 v13, v10 ; MOVREL-NEXT: v_movreld_b32_e32 v13, v10
; MOVREL-NEXT: v_movreld_b32_e32 v14, v11 ; MOVREL-NEXT: v_movreld_b32_e32 v14, v11
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo ; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo
; MOVREL-NEXT: s_cbranch_execnz BB58_1 ; MOVREL-NEXT: s_cbranch_execnz BB58_1
; MOVREL-NEXT: ; %bb.2: ; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b32 exec_lo, s0 ; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_readfirstlane_b32 s0, v13 ; MOVREL-NEXT: v_readfirstlane_b32 s0, v13
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

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; GFX8-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GFX8-NEXT: v_div_fmas_f32 v0, v0, v1, v2
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX10_W32-LABEL: s_div_fmas_f32: ; GFX10_W32-LABEL: s_div_fmas_f32:
; GFX10_W32: ; %bb.0: ; GFX10_W32: ; %bb.0:
; GFX10_W32-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W32-NEXT: s_cmp_eq_u32 s3, 0
; GFX10_W32-NEXT: v_mov_b32_e32 v0, s1 ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s1
; GFX10_W32-NEXT: v_mov_b32_e32 v1, s2 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s2
; GFX10_W32-NEXT: ; implicit-def: $vcc_hi
; GFX10_W32-NEXT: s_cselect_b32 s3, 1, 0 ; GFX10_W32-NEXT: s_cselect_b32 s3, 1, 0
; GFX10_W32-NEXT: ; implicit-def: $vcc_hi
; GFX10_W32-NEXT: s_and_b32 s3, 1, s3 ; GFX10_W32-NEXT: s_and_b32 s3, 1, s3
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3 ; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; GFX10_W32-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, s0, v0, v1
; GFX10_W32-NEXT: ; return to shader part epilog ; GFX10_W32-NEXT: ; return to shader part epilog
; ;
; GFX10_W64-LABEL: s_div_fmas_f32: ; GFX10_W64-LABEL: s_div_fmas_f32:
; GFX10_W64: ; %bb.0: ; GFX10_W64: ; %bb.0:
; GFX10_W64-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W64-NEXT: s_cmp_eq_u32 s3, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s1 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s1
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10_W64-NEXT: s_cselect_b32 s3, 1, 0 ; GFX10_W64-NEXT: s_cselect_b32 s3, 1, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10_W64-NEXT: s_and_b32 s3, 1, s3 ; GFX10_W64-NEXT: s_and_b32 s3, 1, s3
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3
; GFX10_W64-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, s0, v0, v1
; GFX10_W64-NEXT: ; return to shader part epilog ; GFX10_W64-NEXT: ; return to shader part epilog
%vcc = icmp eq i32 %d, 0 %vcc = icmp eq i32 %d, 0
%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %vcc) %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %vcc)
ret float %result ret float %result
} }
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; GFX10_W32-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10_W32-NEXT: v_readfirstlane_b32 s0, v0
; GFX10_W32-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10_W32-NEXT: v_readfirstlane_b32 s1, v1
; GFX10_W32-NEXT: ; return to shader part epilog ; GFX10_W32-NEXT: ; return to shader part epilog
; ;
; GFX10_W64-LABEL: s_div_fmas_f64: ; GFX10_W64-LABEL: s_div_fmas_f64:
; GFX10_W64: ; %bb.0: ; GFX10_W64: ; %bb.0:
; GFX10_W64-NEXT: s_cmp_eq_u32 s6, 0 ; GFX10_W64-NEXT: s_cmp_eq_u32 s6, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2
; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s5
; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4
; GFX10_W64-NEXT: s_and_b32 s6, 1, s6 ; GFX10_W64-NEXT: s_and_b32 s6, 1, s6
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s5
; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[0:1], v[0:1], v[2:3] ; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[0:1], v[0:1], v[2:3]
; GFX10_W64-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10_W64-NEXT: v_readfirstlane_b32 s0, v0
; GFX10_W64-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10_W64-NEXT: v_readfirstlane_b32 s1, v1
; GFX10_W64-NEXT: ; return to shader part epilog ; GFX10_W64-NEXT: ; return to shader part epilog
%vcc = icmp eq i32 %d, 0 %vcc = icmp eq i32 %d, 0
%result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %vcc) %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %vcc)
ret double %result ret double %result
} }
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; GFX10_W64-NEXT: s_load_dword s2, s[0:1], 0xb8 ; GFX10_W64-NEXT: s_load_dword s2, s[0:1], 0xb8
; GFX10_W64-NEXT: s_load_dword s3, s[0:1], 0x70 ; GFX10_W64-NEXT: s_load_dword s3, s[0:1], 0x70
; GFX10_W64-NEXT: s_load_dword s4, s[0:1], 0x94 ; GFX10_W64-NEXT: s_load_dword s4, s[0:1], 0x94
; GFX10_W64-NEXT: s_load_dword s5, s[0:1], 0x4c ; GFX10_W64-NEXT: s_load_dword s5, s[0:1], 0x4c
; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 ; GFX10_W64-NEXT: s_and_b32 s2, 1, s2
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s3 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s3
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s4
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s4
; GFX10_W64-NEXT: v_div_fmas_f32 v2, s5, v0, v1 ; GFX10_W64-NEXT: v_div_fmas_f32 v2, s5, v0, v1
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s1 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s1
; GFX10_W64-NEXT: global_store_dword v[0:1], v2, off ; GFX10_W64-NEXT: global_store_dword v[0:1], v2, off
; GFX10_W64-NEXT: s_endpgm ; GFX10_W64-NEXT: s_endpgm
%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d)
store float %result, float addrspace(1)* %out, align 4 store float %result, float addrspace(1)* %out, align 4
ret void ret void
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; GFX10_W64: ; %bb.0: ; GFX10_W64: ; %bb.0:
; GFX10_W64-NEXT: s_clause 0x1 ; GFX10_W64-NEXT: s_clause 0x1
; GFX10_W64-NEXT: s_load_dword s8, s[0:1], 0x44 ; GFX10_W64-NEXT: s_load_dword s8, s[0:1], 0x44
; GFX10_W64-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX10_W64-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_and_b32 s8, 1, s8 ; GFX10_W64-NEXT: s_and_b32 s8, 1, s8
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s4 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s4
; GFX10_W64-NEXT: v_mov_b32_e32 v2, s6 ; GFX10_W64-NEXT: v_mov_b32_e32 v2, s6
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s8
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s5 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s5
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s7 ; GFX10_W64-NEXT: v_mov_b32_e32 v3, s7
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s8
; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[2:3], v[0:1], v[2:3] ; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[2:3], v[0:1], v[2:3]
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s1 ; GFX10_W64-NEXT: v_mov_b32_e32 v3, s1
; GFX10_W64-NEXT: v_mov_b32_e32 v2, s0 ; GFX10_W64-NEXT: v_mov_b32_e32 v2, s0
; GFX10_W64-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10_W64-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10_W64-NEXT: s_endpgm ; GFX10_W64-NEXT: s_endpgm
%result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d)
store double %result, double addrspace(1)* %out, align 8 store double %result, double addrspace(1)* %out, align 8
ret void ret void
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; GFX10_W64-LABEL: test_div_fmas_f32_cond_to_vcc: ; GFX10_W64-LABEL: test_div_fmas_f32_cond_to_vcc:
; GFX10_W64: ; %bb.0: ; GFX10_W64: ; %bb.0:
; GFX10_W64-NEXT: s_clause 0x1 ; GFX10_W64-NEXT: s_clause 0x1
; GFX10_W64-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c ; GFX10_W64-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_cmp_eq_u32 s7, 0 ; GFX10_W64-NEXT: s_cmp_eq_u32 s7, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s5 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s5
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s6
; GFX10_W64-NEXT: s_cselect_b32 s2, 1, 0 ; GFX10_W64-NEXT: s_cselect_b32 s2, 1, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s6
; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 ; GFX10_W64-NEXT: s_and_b32 s2, 1, s2
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GFX10_W64-NEXT: v_div_fmas_f32 v2, s4, v0, v1 ; GFX10_W64-NEXT: v_div_fmas_f32 v2, s4, v0, v1
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s1 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s1
; GFX10_W64-NEXT: global_store_dword v[0:1], v2, off ; GFX10_W64-NEXT: global_store_dword v[0:1], v2, off
; GFX10_W64-NEXT: s_endpgm ; GFX10_W64-NEXT: s_endpgm
%cmp = icmp eq i32 %i, 0 %cmp = icmp eq i32 %i, 0
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; GFX10_W32-NEXT: v_mov_b32_e32 v3, s6 ; GFX10_W32-NEXT: v_mov_b32_e32 v3, s6
; GFX10_W32-NEXT: v_mov_b32_e32 v4, s7 ; GFX10_W32-NEXT: v_mov_b32_e32 v4, s7
; GFX10_W32-NEXT: s_add_u32 s0, s4, 8 ; GFX10_W32-NEXT: s_add_u32 s0, s4, 8
; GFX10_W32-NEXT: s_addc_u32 s1, s5, 0 ; GFX10_W32-NEXT: s_addc_u32 s1, s5, 0
; GFX10_W32-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10_W32-NEXT: s_cmp_lg_u32 s2, 0
; GFX10_W32-NEXT: v_add_co_u32_e64 v1, vcc_lo, v3, v1 ; GFX10_W32-NEXT: v_add_co_u32_e64 v1, vcc_lo, v3, v1
; GFX10_W32-NEXT: s_cselect_b32 s2, 1, 0 ; GFX10_W32-NEXT: s_cselect_b32 s2, 1, 0
; GFX10_W32-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo ; GFX10_W32-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
; GFX10_W32-NEXT: v_add_co_u32_e64 v3, vcc_lo, v1, 8
; GFX10_W32-NEXT: s_and_b32 s2, 1, s2 ; GFX10_W32-NEXT: s_and_b32 s2, 1, s2
; GFX10_W32-NEXT: v_add_co_u32_e64 v3, vcc_lo, v1, 8
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s2, 0, s2
; GFX10_W32-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo ; GFX10_W32-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
; GFX10_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s2, 0, s2
; GFX10_W32-NEXT: s_clause 0x2 ; GFX10_W32-NEXT: s_clause 0x2
; GFX10_W32-NEXT: global_load_dword v1, v[1:2], off ; GFX10_W32-NEXT: global_load_dword v1, v[1:2], off
; GFX10_W32-NEXT: global_load_dword v2, v[3:4], off offset:-4 ; GFX10_W32-NEXT: global_load_dword v2, v[3:4], off offset:-4
; GFX10_W32-NEXT: global_load_dword v3, v[3:4], off ; GFX10_W32-NEXT: global_load_dword v3, v[3:4], off
; GFX10_W32-NEXT: s_and_b32 vcc_lo, vcc_lo, s2 ; GFX10_W32-NEXT: s_and_b32 vcc_lo, vcc_lo, s2
; GFX10_W32-NEXT: s_waitcnt vmcnt(0) ; GFX10_W32-NEXT: s_waitcnt vmcnt(0)
; GFX10_W32-NEXT: v_div_fmas_f32 v2, v1, v2, v3 ; GFX10_W32-NEXT: v_div_fmas_f32 v2, v1, v2, v3
; GFX10_W32-NEXT: v_mov_b32_e32 v0, s0 ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s0
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; GFX10_W64-NEXT: v_mov_b32_e32 v3, s6 ; GFX10_W64-NEXT: v_mov_b32_e32 v3, s6
; GFX10_W64-NEXT: v_mov_b32_e32 v4, s7 ; GFX10_W64-NEXT: v_mov_b32_e32 v4, s7
; GFX10_W64-NEXT: s_add_u32 s0, s4, 8 ; GFX10_W64-NEXT: s_add_u32 s0, s4, 8
; GFX10_W64-NEXT: s_addc_u32 s1, s5, 0 ; GFX10_W64-NEXT: s_addc_u32 s1, s5, 0
; GFX10_W64-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10_W64-NEXT: s_cmp_lg_u32 s2, 0
; GFX10_W64-NEXT: v_add_co_u32_e64 v1, vcc, v3, v1 ; GFX10_W64-NEXT: v_add_co_u32_e64 v1, vcc, v3, v1
; GFX10_W64-NEXT: s_cselect_b32 s2, 1, 0 ; GFX10_W64-NEXT: s_cselect_b32 s2, 1, 0
; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v2, vcc, v4, v2, vcc ; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v2, vcc, v4, v2, vcc
; GFX10_W64-NEXT: v_add_co_u32_e64 v3, vcc, v1, 8
; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 ; GFX10_W64-NEXT: s_and_b32 s2, 1, s2
; GFX10_W64-NEXT: v_add_co_u32_e64 v3, vcc, v1, 8
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2
; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v4, vcc, 0, v2, vcc ; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v4, vcc, 0, v2, vcc
; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2
; GFX10_W64-NEXT: s_clause 0x2 ; GFX10_W64-NEXT: s_clause 0x2
; GFX10_W64-NEXT: global_load_dword v1, v[1:2], off ; GFX10_W64-NEXT: global_load_dword v1, v[1:2], off
; GFX10_W64-NEXT: global_load_dword v2, v[3:4], off offset:-4 ; GFX10_W64-NEXT: global_load_dword v2, v[3:4], off offset:-4
; GFX10_W64-NEXT: global_load_dword v3, v[3:4], off ; GFX10_W64-NEXT: global_load_dword v3, v[3:4], off
; GFX10_W64-NEXT: s_and_b64 vcc, vcc, s[2:3] ; GFX10_W64-NEXT: s_and_b64 vcc, vcc, s[2:3]
; GFX10_W64-NEXT: s_waitcnt vmcnt(0) ; GFX10_W64-NEXT: s_waitcnt vmcnt(0)
; GFX10_W64-NEXT: v_div_fmas_f32 v2, v1, v2, v3 ; GFX10_W64-NEXT: v_div_fmas_f32 v2, v1, v2, v3
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0
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; GFX10_W32-NEXT: v_mov_b32_e32 v1, s1 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s1
; GFX10_W32-NEXT: global_store_dword v[0:1], v2, off ; GFX10_W32-NEXT: global_store_dword v[0:1], v2, off
; GFX10_W32-NEXT: s_endpgm ; GFX10_W32-NEXT: s_endpgm
; ;
; GFX10_W64-LABEL: test_div_fmas_f32_i1_phi_vcc: ; GFX10_W64-LABEL: test_div_fmas_f32_i1_phi_vcc:
; GFX10_W64: ; %bb.0: ; %entry ; GFX10_W64: ; %bb.0: ; %entry
; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x4c ; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x4c
; GFX10_W64-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX10_W64-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX10_W64-NEXT: s_mov_b32 s4, 0 ; GFX10_W64-NEXT: s_mov_b32 s6, 0
; GFX10_W64-NEXT: v_lshlrev_b64 v[1:2], 2, v[0:1] ; GFX10_W64-NEXT: v_lshlrev_b64 v[1:2], 2, v[0:1]
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: v_mov_b32_e32 v4, s3 ; GFX10_W64-NEXT: v_mov_b32_e32 v4, s3
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s2 ; GFX10_W64-NEXT: v_mov_b32_e32 v3, s2
; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10_W64-NEXT: v_add_co_u32_e64 v1, vcc, v3, v1 ; GFX10_W64-NEXT: v_add_co_u32_e64 v1, vcc, v3, v1
; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v2, vcc, v4, v2, vcc ; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v2, vcc, v4, v2, vcc
; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10_W64-NEXT: global_load_dwordx3 v[1:3], v[1:2], off ; GFX10_W64-NEXT: global_load_dwordx3 v[1:3], v[1:2], off
; GFX10_W64-NEXT: s_and_saveexec_b64 s[6:7], vcc ; GFX10_W64-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX10_W64-NEXT: s_cbranch_execz BB13_2 ; GFX10_W64-NEXT: s_cbranch_execz BB13_2
; GFX10_W64-NEXT: ; %bb.1: ; %bb ; GFX10_W64-NEXT: ; %bb.1: ; %bb
; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74 ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10_W64-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0
; GFX10_W64-NEXT: BB13_2: ; %exit ; GFX10_W64-NEXT: BB13_2: ; %exit
; GFX10_W64-NEXT: v_nop ; GFX10_W64-NEXT: v_nop
; GFX10_W64-NEXT: s_or_b64 exec, exec, s[6:7] ; GFX10_W64-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX10_W64-NEXT: s_and_b32 s0, 1, s4 ; GFX10_W64-NEXT: s_and_b32 s0, 1, s6
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_add_u32 s0, s2, 8 ; GFX10_W64-NEXT: s_add_u32 s0, s2, 8
; GFX10_W64-NEXT: s_addc_u32 s1, s3, 0 ; GFX10_W64-NEXT: s_addc_u32 s1, s3, 0
; GFX10_W64-NEXT: s_waitcnt vmcnt(0) ; GFX10_W64-NEXT: s_waitcnt vmcnt(0)
; GFX10_W64-NEXT: v_div_fmas_f32 v2, v1, v2, v3 ; GFX10_W64-NEXT: v_div_fmas_f32 v2, v1, v2, v3
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s1 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s1
Show All 33 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll

Show First 20 Lines • Show All 476 Lines • ▼ Show 20 Lines
; ;
; GFX10-LABEL: atomic_add_i32_2d: ; GFX10-LABEL: atomic_add_i32_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc a16 ; GFX10-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i16(i32 %data, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0) %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i16(i32 %data, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float %out = bitcast i32 %v to float
ret float %out ret float %out
Show All 16 Lines
; GFX9-NEXT: s_mov_b32 s7, s9 ; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX9-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc a16 ; GFX9-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc a16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: atomic_add_i32_3d: ; GFX10-LABEL: atomic_add_i32_3d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc a16 ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.3d.i32.i16(i32 %data, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0) %v = call i32 @llvm.amdgcn.image.atomic.add.3d.i32.i16(i32 %data, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float %out = bitcast i32 %v to float
ret float %out ret float %out
Show All 16 Lines
; GFX9-NEXT: s_mov_b32 s7, s9 ; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX9-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc a16 da ; GFX9-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: atomic_add_i32_cube: ; GFX10-LABEL: atomic_add_i32_cube:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc a16 ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.cube.i32.i16(i32 %data, i16 %s, i16 %t, i16 %face, <8 x i32> %rsrc, i32 0, i32 0) %v = call i32 @llvm.amdgcn.image.atomic.add.cube.i32.i16(i32 %data, i16 %s, i16 %t, i16 %face, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float %out = bitcast i32 %v to float
ret float %out ret float %out
Show All 19 Lines
; ;
; GFX10-LABEL: atomic_add_i32_1darray: ; GFX10-LABEL: atomic_add_i32_1darray:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16 ; GFX10-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i16(i32 %data, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0) %v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i16(i32 %data, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float %out = bitcast i32 %v to float
ret float %out ret float %out
Show All 16 Lines
; GFX9-NEXT: s_mov_b32 s7, s9 ; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX9-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc a16 da ; GFX9-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: atomic_add_i32_2darray: ; GFX10-LABEL: atomic_add_i32_2darray:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16 ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i16(i32 %data, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0) %v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i16(i32 %data, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float %out = bitcast i32 %v to float
ret float %out ret float %out
Show All 16 Lines
; GFX9-NEXT: s_mov_b32 s7, s9 ; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX9-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc a16 ; GFX9-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc a16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: atomic_add_i32_2dmsaa: ; GFX10-LABEL: atomic_add_i32_2dmsaa:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16 ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i16(i32 %data, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0) %v = call i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i16(i32 %data, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float %out = bitcast i32 %v to float
ret float %out ret float %out
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; GFX10-LABEL: atomic_add_i32_2darraymsaa: ; GFX10-LABEL: atomic_add_i32_2darraymsaa:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff ; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v5, v4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v2
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v5, v4
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16 ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i16(i32 %data, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0) %v = call i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i16(i32 %data, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float %out = bitcast i32 %v to float
ret float %out ret float %out
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; ;
; GFX10-LABEL: atomic_add_i64_2d: ; GFX10-LABEL: atomic_add_i64_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc a16 ; GFX10-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i64 @llvm.amdgcn.image.atomic.add.2d.i64.i16(i64 %data, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0) %v = call i64 @llvm.amdgcn.image.atomic.add.2d.i64.i16(i64 %data, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i64 %v to <2 x float> %out = bitcast i64 %v to <2 x float>
ret <2 x float> %out ret <2 x float> %out
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; GFX9-NEXT: s_mov_b32 s7, s9 ; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX9-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX9-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 unorm glc a16 ; GFX9-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 unorm glc a16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: atomic_add_i64_3d: ; GFX10-LABEL: atomic_add_i64_3d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm glc a16 ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i64 @llvm.amdgcn.image.atomic.add.3d.i64.i16(i64 %data, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0) %v = call i64 @llvm.amdgcn.image.atomic.add.3d.i64.i16(i64 %data, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i64 %v to <2 x float> %out = bitcast i64 %v to <2 x float>
ret <2 x float> %out ret <2 x float> %out
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; GFX9-NEXT: s_mov_b32 s7, s9 ; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX9-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX9-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 unorm glc a16 da ; GFX9-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 unorm glc a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: atomic_add_i64_cube: ; GFX10-LABEL: atomic_add_i64_cube:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm glc a16 ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i64 @llvm.amdgcn.image.atomic.add.cube.i64.i16(i64 %data, i16 %s, i16 %t, i16 %face , <8 x i32> %rsrc, i32 0, i32 0) %v = call i64 @llvm.amdgcn.image.atomic.add.cube.i64.i16(i64 %data, i16 %s, i16 %t, i16 %face , <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i64 %v to <2 x float> %out = bitcast i64 %v to <2 x float>
ret <2 x float> %out ret <2 x float> %out
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; ;
; GFX10-LABEL: atomic_add_i64_1darray: ; GFX10-LABEL: atomic_add_i64_1darray:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16 ; GFX10-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i64 @llvm.amdgcn.image.atomic.add.1darray.i64.i16(i64 %data, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0) %v = call i64 @llvm.amdgcn.image.atomic.add.1darray.i64.i16(i64 %data, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i64 %v to <2 x float> %out = bitcast i64 %v to <2 x float>
ret <2 x float> %out ret <2 x float> %out
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; GFX9-NEXT: s_mov_b32 s7, s9 ; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX9-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX9-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 unorm glc a16 da ; GFX9-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 unorm glc a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: atomic_add_i64_2darray: ; GFX10-LABEL: atomic_add_i64_2darray:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16 ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i64 @llvm.amdgcn.image.atomic.add.2darray.i64.i16(i64 %data, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0) %v = call i64 @llvm.amdgcn.image.atomic.add.2darray.i64.i16(i64 %data, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i64 %v to <2 x float> %out = bitcast i64 %v to <2 x float>
ret <2 x float> %out ret <2 x float> %out
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; GFX9-NEXT: s_mov_b32 s7, s9 ; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX9-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX9-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 unorm glc a16 ; GFX9-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 unorm glc a16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: atomic_add_i64_2dmsaa: ; GFX10-LABEL: atomic_add_i64_2dmsaa:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16 ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i64 @llvm.amdgcn.image.atomic.add.2dmsaa.i64.i16(i64 %data, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0) %v = call i64 @llvm.amdgcn.image.atomic.add.2dmsaa.i64.i16(i64 %data, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i64 %v to <2 x float> %out = bitcast i64 %v to <2 x float>
ret <2 x float> %out ret <2 x float> %out
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; GFX10-LABEL: atomic_add_i64_2darraymsaa: ; GFX10-LABEL: atomic_add_i64_2darraymsaa:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v6, 0xffff ; GFX10-NEXT: v_mov_b32_e32 v6, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v2, v2, v6, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v6, v5
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v6, v3
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v6, v5
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16 ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call i64 @llvm.amdgcn.image.atomic.add.2darraymsaa.i64.i16(i64 %data, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0) %v = call i64 @llvm.amdgcn.image.atomic.add.2darraymsaa.i64.i16(i64 %data, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i64 %v to <2 x float> %out = bitcast i64 %v to <2 x float>
ret <2 x float> %out ret <2 x float> %out
▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll

Show First 20 Lines • Show All 582 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_mov_b32 s11, s13 ; GFX9-NEXT: s_mov_b32 s11, s13
; GFX9-NEXT: v_and_or_b32 v1, v2, v3, s12 ; GFX9-NEXT: v_and_or_b32 v1, v2, v3, s12
; GFX9-NEXT: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16 ; GFX9-NEXT: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10NSA-LABEL: gather4_l_2d: ; GFX10NSA-LABEL: gather4_l_2d:
; GFX10NSA: ; %bb.0: ; %main_body ; GFX10NSA: ; %bb.0: ; %main_body
; GFX10NSA-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10NSA-NEXT: s_mov_b32 s0, s2 ; GFX10NSA-NEXT: s_mov_b32 s0, s2
; GFX10NSA-NEXT: s_mov_b32 s2, s4 ; GFX10NSA-NEXT: s_mov_b32 s2, s4
; GFX10NSA-NEXT: s_mov_b32 s4, s6 ; GFX10NSA-NEXT: s_mov_b32 s4, s6
; GFX10NSA-NEXT: s_mov_b32 s6, s8 ; GFX10NSA-NEXT: s_mov_b32 s6, s8
; GFX10NSA-NEXT: s_mov_b32 s8, s10 ; GFX10NSA-NEXT: s_mov_b32 s8, s10
; GFX10NSA-NEXT: s_mov_b32 s10, s12 ; GFX10NSA-NEXT: s_mov_b32 s10, s12
; GFX10NSA-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10NSA-NEXT: s_lshl_b32 s12, s0, 16 ; GFX10NSA-NEXT: s_lshl_b32 s12, s0, 16
; GFX10NSA-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10NSA-NEXT: v_and_or_b32 v1, v2, v3, s12
; GFX10NSA-NEXT: s_mov_b32 s1, s3 ; GFX10NSA-NEXT: s_mov_b32 s1, s3
; GFX10NSA-NEXT: s_mov_b32 s3, s5 ; GFX10NSA-NEXT: s_mov_b32 s3, s5
; GFX10NSA-NEXT: s_mov_b32 s5, s7 ; GFX10NSA-NEXT: s_mov_b32 s5, s7
; GFX10NSA-NEXT: s_mov_b32 s7, s9 ; GFX10NSA-NEXT: s_mov_b32 s7, s9
; GFX10NSA-NEXT: s_mov_b32 s9, s11 ; GFX10NSA-NEXT: s_mov_b32 s9, s11
; GFX10NSA-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10NSA-NEXT: s_mov_b32 s11, s13 ; GFX10NSA-NEXT: s_mov_b32 s11, s13
; GFX10NSA-NEXT: v_and_or_b32 v1, v2, v3, s12
; GFX10NSA-NEXT: ; implicit-def: $vcc_hi ; GFX10NSA-NEXT: ; implicit-def: $vcc_hi
; GFX10NSA-NEXT: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX10NSA-NEXT: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog ; GFX10NSA-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 1, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 1, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 19 Lines
; GFX9-NEXT: s_mov_b32 s11, s13 ; GFX9-NEXT: s_mov_b32 s11, s13
; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s12 ; GFX9-NEXT: v_and_or_b32 v2, v3, v4, s12
; GFX9-NEXT: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16 ; GFX9-NEXT: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10NSA-LABEL: gather4_c_l_2d: ; GFX10NSA-LABEL: gather4_c_l_2d:
; GFX10NSA: ; %bb.0: ; %main_body ; GFX10NSA: ; %bb.0: ; %main_body
; GFX10NSA-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10NSA-NEXT: s_mov_b32 s0, s2 ; GFX10NSA-NEXT: s_mov_b32 s0, s2
; GFX10NSA-NEXT: s_mov_b32 s2, s4 ; GFX10NSA-NEXT: s_mov_b32 s2, s4
; GFX10NSA-NEXT: s_mov_b32 s4, s6 ; GFX10NSA-NEXT: s_mov_b32 s4, s6
; GFX10NSA-NEXT: s_mov_b32 s6, s8 ; GFX10NSA-NEXT: s_mov_b32 s6, s8
; GFX10NSA-NEXT: s_mov_b32 s8, s10 ; GFX10NSA-NEXT: s_mov_b32 s8, s10
; GFX10NSA-NEXT: s_mov_b32 s10, s12 ; GFX10NSA-NEXT: s_mov_b32 s10, s12
; GFX10NSA-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10NSA-NEXT: s_lshl_b32 s12, s0, 16 ; GFX10NSA-NEXT: s_lshl_b32 s12, s0, 16
; GFX10NSA-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10NSA-NEXT: v_and_or_b32 v2, v3, v4, s12
; GFX10NSA-NEXT: s_mov_b32 s1, s3 ; GFX10NSA-NEXT: s_mov_b32 s1, s3
; GFX10NSA-NEXT: s_mov_b32 s3, s5 ; GFX10NSA-NEXT: s_mov_b32 s3, s5
; GFX10NSA-NEXT: s_mov_b32 s5, s7 ; GFX10NSA-NEXT: s_mov_b32 s5, s7
; GFX10NSA-NEXT: s_mov_b32 s7, s9 ; GFX10NSA-NEXT: s_mov_b32 s7, s9
; GFX10NSA-NEXT: s_mov_b32 s9, s11 ; GFX10NSA-NEXT: s_mov_b32 s9, s11
; GFX10NSA-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10NSA-NEXT: s_mov_b32 s11, s13 ; GFX10NSA-NEXT: s_mov_b32 s11, s13
; GFX10NSA-NEXT: v_and_or_b32 v2, v3, v4, s12
; GFX10NSA-NEXT: ; implicit-def: $vcc_hi ; GFX10NSA-NEXT: ; implicit-def: $vcc_hi
; GFX10NSA-NEXT: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX10NSA-NEXT: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog ; GFX10NSA-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 22 Lines
; ;
; GFX10NSA-LABEL: gather4_lz_2d: ; GFX10NSA-LABEL: gather4_lz_2d:
; GFX10NSA: ; %bb.0: ; %main_body ; GFX10NSA: ; %bb.0: ; %main_body
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10NSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10NSA-NEXT: s_mov_b32 s0, s2 ; GFX10NSA-NEXT: s_mov_b32 s0, s2
; GFX10NSA-NEXT: s_mov_b32 s1, s3 ; GFX10NSA-NEXT: s_mov_b32 s1, s3
; GFX10NSA-NEXT: s_mov_b32 s2, s4 ; GFX10NSA-NEXT: s_mov_b32 s2, s4
; GFX10NSA-NEXT: s_mov_b32 s3, s5 ; GFX10NSA-NEXT: s_mov_b32 s3, s5
; GFX10NSA-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10NSA-NEXT: s_mov_b32 s4, s6 ; GFX10NSA-NEXT: s_mov_b32 s4, s6
; GFX10NSA-NEXT: s_mov_b32 s5, s7 ; GFX10NSA-NEXT: s_mov_b32 s5, s7
; GFX10NSA-NEXT: s_mov_b32 s6, s8 ; GFX10NSA-NEXT: s_mov_b32 s6, s8
; GFX10NSA-NEXT: s_mov_b32 s7, s9 ; GFX10NSA-NEXT: s_mov_b32 s7, s9
; GFX10NSA-NEXT: s_mov_b32 s8, s10 ; GFX10NSA-NEXT: s_mov_b32 s8, s10
; GFX10NSA-NEXT: s_mov_b32 s9, s11 ; GFX10NSA-NEXT: s_mov_b32 s9, s11
; GFX10NSA-NEXT: s_mov_b32 s10, s12 ; GFX10NSA-NEXT: s_mov_b32 s10, s12
; GFX10NSA-NEXT: s_mov_b32 s11, s13 ; GFX10NSA-NEXT: s_mov_b32 s11, s13
; GFX10NSA-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10NSA-NEXT: ; implicit-def: $vcc_hi ; GFX10NSA-NEXT: ; implicit-def: $vcc_hi
; GFX10NSA-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX10NSA-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog ; GFX10NSA-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 22 Lines
; ;
; GFX10NSA-LABEL: gather4_c_lz_2d: ; GFX10NSA-LABEL: gather4_c_lz_2d:
; GFX10NSA: ; %bb.0: ; %main_body ; GFX10NSA: ; %bb.0: ; %main_body
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10NSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10NSA-NEXT: s_mov_b32 s0, s2 ; GFX10NSA-NEXT: s_mov_b32 s0, s2
; GFX10NSA-NEXT: s_mov_b32 s1, s3 ; GFX10NSA-NEXT: s_mov_b32 s1, s3
; GFX10NSA-NEXT: s_mov_b32 s2, s4 ; GFX10NSA-NEXT: s_mov_b32 s2, s4
; GFX10NSA-NEXT: s_mov_b32 s3, s5 ; GFX10NSA-NEXT: s_mov_b32 s3, s5
; GFX10NSA-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10NSA-NEXT: s_mov_b32 s4, s6 ; GFX10NSA-NEXT: s_mov_b32 s4, s6
; GFX10NSA-NEXT: s_mov_b32 s5, s7 ; GFX10NSA-NEXT: s_mov_b32 s5, s7
; GFX10NSA-NEXT: s_mov_b32 s6, s8 ; GFX10NSA-NEXT: s_mov_b32 s6, s8
; GFX10NSA-NEXT: s_mov_b32 s7, s9 ; GFX10NSA-NEXT: s_mov_b32 s7, s9
; GFX10NSA-NEXT: s_mov_b32 s8, s10 ; GFX10NSA-NEXT: s_mov_b32 s8, s10
; GFX10NSA-NEXT: s_mov_b32 s9, s11 ; GFX10NSA-NEXT: s_mov_b32 s9, s11
; GFX10NSA-NEXT: s_mov_b32 s10, s12 ; GFX10NSA-NEXT: s_mov_b32 s10, s12
; GFX10NSA-NEXT: s_mov_b32 s11, s13 ; GFX10NSA-NEXT: s_mov_b32 s11, s13
; GFX10NSA-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10NSA-NEXT: ; implicit-def: $vcc_hi ; GFX10NSA-NEXT: ; implicit-def: $vcc_hi
; GFX10NSA-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX10NSA-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
; GFX10NSA-NEXT: ; return to shader part epilog ; GFX10NSA-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
Show All 27 Lines
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 3, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 3, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
ret <4 x float> %v.vec ret <4 x float> %v.vec
} }
declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
attributes #0 = { nounwind readonly } attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll

Show All 24 Lines
; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw: ; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 24 Lines
; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw_tfe: ; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
Show All 27 Lines
; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe: ; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 3, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 3, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
ret <4 x float> %v.vec ret <4 x float> %v.vec
} }
declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0 declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0 declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
attributes #0 = { nounwind readonly } attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
Show All 27 Lines
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 3, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 3, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
ret <4 x float> %v.vec ret <4 x float> %v.vec
} }
declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
attributes #0 = { nounwind readonly } attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll

Show All 18 Lines
; GFX9-NEXT: s_mov_b32 s7, s9 ; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: v_and_or_b32 v1, v2, v3, s8 ; GFX9-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX9-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 ; GFX9-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: load_3d_v4f32_xyzw: ; GFX10-LABEL: load_3d_v4f32_xyzw:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 ; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 18 Lines
; GFX9-NEXT: v_mov_b32_e32 v6, s11 ; GFX9-NEXT: v_mov_b32_e32 v6, s11
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[5:6], v4, off ; GFX9-NEXT: global_store_dword v[5:6], v4, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: load_3d_v4f32_xyzw_tfe: ; GFX10-LABEL: load_3d_v4f32_xyzw_tfe:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
Show All 21 Lines
; GFX9-NEXT: v_mov_b32_e32 v6, s11 ; GFX9-NEXT: v_mov_b32_e32 v6, s11
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[5:6], v4, off ; GFX9-NEXT: global_store_dword v[5:6], v4, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: load_3d_v4f32_xyzw_tfe_lwe: ; GFX10-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_lshl_b32 s8, s0, 16 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 3, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 3, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
ret <4 x float> %v.vec ret <4 x float> %v.vec
} }
declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0 declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
declare { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0 declare { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
attributes #0 = { nounwind readonly } attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
Show All 27 Lines
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 3, i32 0) %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 3, i32 0)
%v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.vec = extractvalue { <4 x float>, i32 } %v, 0
%v.err = extractvalue { <4 x float>, i32 } %v, 1 %v.err = extractvalue { <4 x float>, i32 } %v, 1
store i32 %v.err, i32 addrspace(1)* %out, align 4 store i32 %v.err, i32 addrspace(1)* %out, align 4
ret <4 x float> %v.vec ret <4 x float> %v.vec
} }
declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
attributes #0 = { nounwind readonly } attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; ;
; GFX10-LABEL: sample_l_2d: ; GFX10-LABEL: sample_l_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f16(i32 15, half %s, half %t, half -0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f16(i32 15, half %s, half %t, half -0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 25 Lines
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_lshl_b32 s12, s0, 16 ; GFX10-NEXT: s_lshl_b32 s12, s0, 16
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; GFX10-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f16(i32 15, float %zcompare, half %s, half -2.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f16(i32 15, float %zcompare, half %s, half -2.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
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; ;
; GFX10-LABEL: sample_c_l_2d: ; GFX10-LABEL: sample_c_l_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
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; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_lshl_b32 s12, s0, 16 ; GFX10-NEXT: s_lshl_b32 s12, s0, 16
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; GFX10-NEXT: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f16(i32 15, i32 %offset, half %s, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f16(i32 15, i32 %offset, half %s, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
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; ;
; GFX10-LABEL: sample_l_o_2d: ; GFX10-LABEL: sample_l_o_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f16(i32 15, i32 %offset, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f16(i32 15, i32 %offset, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
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; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_lshl_b32 s12, s0, 16 ; GFX10-NEXT: s_lshl_b32 s12, s0, 16
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, s12
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, s12
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; GFX10-NEXT: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f16(i32 15, i32 %offset, float %zcompare, half %s, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f16(i32 15, i32 %offset, float %zcompare, half %s, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
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; ;
; GFX10-LABEL: sample_c_l_o_2d: ; GFX10-LABEL: sample_c_l_o_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f16(i32 15, i32 %offset, float %zcompare, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f16(i32 15, i32 %offset, float %zcompare, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 22 Lines
; ;
; GFX10-LABEL: gather4_l_2d: ; GFX10-LABEL: gather4_l_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 15, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 15, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
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; ;
; GFX10-LABEL: gather4_c_l_2d: ; GFX10-LABEL: gather4_c_l_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 22 Lines
; ;
; GFX10-LABEL: gather4_l_o_2d: ; GFX10-LABEL: gather4_l_o_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_gather4_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: image_gather4_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f16(i32 15, i32 %offset, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f16(i32 15, i32 %offset, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 22 Lines
; ;
; GFX10-LABEL: gather4_c_l_o_2d: ; GFX10-LABEL: gather4_c_l_o_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_gather4_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: image_gather4_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f16(i32 15, i32 %offset, float %zcompare, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f16(i32 15, i32 %offset, float %zcompare, half %s, half %t, half 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
Show All 15 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll

Show First 20 Lines • Show All 587 Lines • ▼ Show 20 Lines
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 0) call void @llvm.amdgcn.s.setreg(i32 14337, i32 0)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_1() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_1() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x1 ; GFX10-NEXT: s_round_mode 0x1
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 1) call void @llvm.amdgcn.s.setreg(i32 14337, i32 1)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_2() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_2() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x2 ; GFX10-NEXT: s_round_mode 0x2
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 2) call void @llvm.amdgcn.s.setreg(i32 14337, i32 2)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_4() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_4() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x4 ; GFX10-NEXT: s_round_mode 0x4
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 4) call void @llvm.amdgcn.s.setreg(i32 14337, i32 4)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_8() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_8() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x8 ; GFX10-NEXT: s_round_mode 0x8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 8) call void @llvm.amdgcn.s.setreg(i32 14337, i32 8)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_16() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_16() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 1
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 1
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 16) call void @llvm.amdgcn.s.setreg(i32 14337, i32 16)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_32() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_32() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 2
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 32) call void @llvm.amdgcn.s.setreg(i32 14337, i32 32)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_64() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_64() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 4
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 4
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 64) call void @llvm.amdgcn.s.setreg(i32 14337, i32 64)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_128() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_128() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 8
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 8
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 128) call void @llvm.amdgcn.s.setreg(i32 14337, i32 128)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_15() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_15() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0xf ; GFX10-NEXT: s_round_mode 0xf
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 15) call void @llvm.amdgcn.s.setreg(i32 14337, i32 15)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_255() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_255() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0xf ; GFX10-NEXT: s_round_mode 0xf
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 15
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 15
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 255) call void @llvm.amdgcn.s.setreg(i32 14337, i32 255)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
; Truncate extra high bit ; Truncate extra high bit
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_597() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_597() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x5 ; GFX10-NEXT: s_round_mode 0x5
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 5
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 5
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 597) call void @llvm.amdgcn.s.setreg(i32 14337, i32 597)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_set_8_bits_straddles_round_and_denorm() { define amdgpu_kernel void @test_setreg_set_8_bits_straddles_round_and_denorm() {
; GFX6789-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm: ; GFX6789-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm:
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll

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; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_sdot4_cast_v4i8: ; GFX10-LABEL: v_sdot4_cast_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: s_movk_i32 s5, 0xff ; GFX10-NEXT: s_movk_i32 s5, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1 ; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1
; GFX10-NEXT: v_and_b32_e32 v1, s5, v2 ; GFX10-NEXT: v_and_b32_e32 v1, s5, v2
; GFX10-NEXT: v_and_b32_e32 v2, s5, v3 ; GFX10-NEXT: v_and_b32_e32 v2, s5, v3
; GFX10-NEXT: v_lshlrev_b32_sdwa v3, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v3, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_b32_e32 v5, s5, v6 ; GFX10-NEXT: v_and_b32_e32 v5, s5, v6
; GFX10-NEXT: v_and_b32_e32 v6, s5, v7 ; GFX10-NEXT: v_and_b32_e32 v6, s5, v7
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll

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; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_udot4_cast_v4i8: ; GFX10-LABEL: v_udot4_cast_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: s_movk_i32 s5, 0xff ; GFX10-NEXT: s_movk_i32 s5, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1 ; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1
; GFX10-NEXT: v_and_b32_e32 v1, s5, v2 ; GFX10-NEXT: v_and_b32_e32 v1, s5, v2
; GFX10-NEXT: v_and_b32_e32 v2, s5, v3 ; GFX10-NEXT: v_and_b32_e32 v2, s5, v3
; GFX10-NEXT: v_lshlrev_b32_sdwa v3, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v3, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_b32_e32 v5, s5, v6 ; GFX10-NEXT: v_and_b32_e32 v5, s5, v6
; GFX10-NEXT: v_and_b32_e32 v6, s5, v7 ; GFX10-NEXT: v_and_b32_e32 v6, s5, v7
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
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llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

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; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i32_constant: ; GFX1064-LABEL: add_i32_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB0_2 ; GFX1064-NEXT: s_cbranch_execz BB0_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
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; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i32_constant: ; GFX1032-LABEL: add_i32_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s2, exec_lo ; GFX1032-NEXT: s_mov_b32 s2, exec_lo
; GFX1032-NEXT: ; implicit-def: $vcc_hi ; GFX1032-NEXT: ; implicit-def: $vcc_hi
; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB0_2 ; GFX1032-NEXT: s_cbranch_execz BB0_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2 ; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1032-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo ; GFX1032-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo
; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s2, 5 ; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s2, 5
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_add_u32_e32 v0, s0, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i32_uniform: ; GFX1064-LABEL: add_i32_uniform:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: s_clause 0x1 ; GFX1064-NEXT: s_clause 0x1
; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX1064-NEXT: s_load_dword s0, s[0:1], 0x2c ; GFX1064-NEXT: s_load_dword s0, s[0:1], 0x2c
; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[6:7], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064-NEXT: s_cbranch_execz BB1_2 ; GFX1064-NEXT: s_cbranch_execz BB1_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s1, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s1, s[2:3]
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; ;
; GFX1032-LABEL: add_i32_uniform: ; GFX1032-LABEL: add_i32_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_clause 0x1 ; GFX1032-NEXT: s_clause 0x1
; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX1032-NEXT: s_load_dword s0, s[0:1], 0x2c ; GFX1032-NEXT: s_load_dword s0, s[0:1], 0x2c
; GFX1032-NEXT: s_mov_b32 s2, exec_lo ; GFX1032-NEXT: s_mov_b32 s2, exec_lo
; GFX1032-NEXT: ; implicit-def: $vcc_hi ; GFX1032-NEXT: ; implicit-def: $vcc_hi
; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB1_2 ; GFX1032-NEXT: s_cbranch_execz BB1_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2 ; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1032-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo ; GFX1032-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s2, s0, s2 ; GFX1032-NEXT: s_mul_i32 s2, s0, s2
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; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 2 ; GFX9-NEXT: s_nop 2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i64_constant: ; GFX1064-LABEL: add_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[4:5], exec
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[4:5], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s5, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s5, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB5_2 ; GFX1064-NEXT: s_cbranch_execz BB5_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
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; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i64_constant: ; GFX1032-LABEL: add_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vcc_hi ; GFX1032-NEXT: ; implicit-def: $vcc_hi
; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0
; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB5_2 ; GFX1032-NEXT: s_cbranch_execz BB5_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo ; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo
; GFX1032-NEXT: v_mul_hi_u32_u24_e64 v2, s3, 5 ; GFX1032-NEXT: v_mul_hi_u32_u24_e64 v2, s3, 5
; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s3, 5 ; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s3, 5
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; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i64_uniform: ; GFX1064-LABEL: add_i64_uniform:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s7, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s7, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB6_2 ; GFX1064-NEXT: s_cbranch_execz BB6_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
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; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB6_2: ; GFX1064-NEXT: BB6_2:
; GFX1064-NEXT: v_nop ; GFX1064-NEXT: v_nop
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v0
; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v0
; GFX1064-NEXT: v_mul_lo_u32 v0, s2, v0 ; GFX1064-NEXT: v_mul_lo_u32 v0, s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
; GFX1064-NEXT: v_readfirstlane_b32 s5, v2 ; GFX1064-NEXT: v_readfirstlane_b32 s4, v2
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3 ; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3
; GFX1064-NEXT: v_add_co_u32_e64 v0, vcc, s4, v0 ; GFX1064-NEXT: v_add_co_u32_e64 v0, vcc, s2, v0
; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, s5, v1, vcc ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, s4, v1, vcc
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i64_uniform: ; GFX1032-LABEL: add_i64_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: s_mov_b32 s5, exec_lo
; GFX1032-NEXT: ; implicit-def: $vcc_hi ; GFX1032-NEXT: ; implicit-def: $vcc_hi
; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s5, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s5, 0
; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB6_2 ; GFX1032-NEXT: s_cbranch_execz BB6_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 ; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5
; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo ; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s6, s3, s5 ; GFX1032-NEXT: s_mul_i32 s6, s3, s5
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; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB6_2: ; GFX1032-NEXT: BB6_2:
; GFX1032-NEXT: v_nop ; GFX1032-NEXT: v_nop
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v0
; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v0
; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 ; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
; GFX1032-NEXT: v_readfirstlane_b32 s5, v2 ; GFX1032-NEXT: v_readfirstlane_b32 s4, v2
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3 ; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3
; GFX1032-NEXT: v_add_co_u32_e64 v0, vcc_lo, s4, v0 ; GFX1032-NEXT: v_add_co_u32_e64 v0, vcc_lo, s2, v0
; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%old = atomicrmw add i64 addrspace(3)* @local_var64, i64 %additive acq_rel %old = atomicrmw add i64 addrspace(3)* @local_var64, i64 %additive acq_rel
store i64 %old, i64 addrspace(1)* %out store i64 %old, i64 addrspace(1)* %out
ret void ret void
} }
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; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i32_constant: ; GFX1064-LABEL: sub_i32_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB8_2 ; GFX1064-NEXT: s_cbranch_execz BB8_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
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; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i32_constant: ; GFX1032-LABEL: sub_i32_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s2, exec_lo ; GFX1032-NEXT: s_mov_b32 s2, exec_lo
; GFX1032-NEXT: ; implicit-def: $vcc_hi ; GFX1032-NEXT: ; implicit-def: $vcc_hi
; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB8_2 ; GFX1032-NEXT: s_cbranch_execz BB8_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2 ; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1032-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo ; GFX1032-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo
; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s2, 5 ; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s2, 5
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i32_uniform: ; GFX1064-LABEL: sub_i32_uniform:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: s_clause 0x1 ; GFX1064-NEXT: s_clause 0x1
; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX1064-NEXT: s_load_dword s0, s[0:1], 0x2c ; GFX1064-NEXT: s_load_dword s0, s[0:1], 0x2c
; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[6:7], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064-NEXT: s_cbranch_execz BB9_2 ; GFX1064-NEXT: s_cbranch_execz BB9_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s1, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s1, s[2:3]
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; ;
; GFX1032-LABEL: sub_i32_uniform: ; GFX1032-LABEL: sub_i32_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_clause 0x1 ; GFX1032-NEXT: s_clause 0x1
; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX1032-NEXT: s_load_dword s0, s[0:1], 0x2c ; GFX1032-NEXT: s_load_dword s0, s[0:1], 0x2c
; GFX1032-NEXT: s_mov_b32 s2, exec_lo ; GFX1032-NEXT: s_mov_b32 s2, exec_lo
; GFX1032-NEXT: ; implicit-def: $vcc_hi ; GFX1032-NEXT: ; implicit-def: $vcc_hi
; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB9_2 ; GFX1032-NEXT: s_cbranch_execz BB9_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2 ; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1032-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo ; GFX1032-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s2, s0, s2 ; GFX1032-NEXT: s_mul_i32 s2, s0, s2
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; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i64_constant: ; GFX1064-LABEL: sub_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[4:5], exec
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[4:5], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s5, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s5, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB11_2 ; GFX1064-NEXT: s_cbranch_execz BB11_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
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; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i64_constant: ; GFX1032-LABEL: sub_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vcc_hi ; GFX1032-NEXT: ; implicit-def: $vcc_hi
; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0
; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB11_2 ; GFX1032-NEXT: s_cbranch_execz BB11_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo ; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo
; GFX1032-NEXT: v_mul_hi_u32_u24_e64 v2, s3, 5 ; GFX1032-NEXT: v_mul_hi_u32_u24_e64 v2, s3, 5
; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s3, 5 ; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s3, 5
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; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i64_uniform: ; GFX1064-LABEL: sub_i64_uniform:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s7, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s7, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB12_2 ; GFX1064-NEXT: s_cbranch_execz BB12_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
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; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB12_2: ; GFX1064-NEXT: BB12_2:
; GFX1064-NEXT: v_nop ; GFX1064-NEXT: v_nop
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v0
; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v0
; GFX1064-NEXT: v_mul_lo_u32 v0, s2, v0 ; GFX1064-NEXT: v_mul_lo_u32 v0, s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
; GFX1064-NEXT: v_readfirstlane_b32 s5, v2 ; GFX1064-NEXT: v_readfirstlane_b32 s4, v2
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3 ; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3
; GFX1064-NEXT: v_sub_co_u32_e64 v0, vcc, s4, v0 ; GFX1064-NEXT: v_sub_co_u32_e64 v0, vcc, s2, v0
; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s5, v1, vcc ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s4, v1, vcc
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i64_uniform: ; GFX1032-LABEL: sub_i64_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: s_mov_b32 s5, exec_lo
; GFX1032-NEXT: ; implicit-def: $vcc_hi ; GFX1032-NEXT: ; implicit-def: $vcc_hi
; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s5, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s5, 0
; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB12_2 ; GFX1032-NEXT: s_cbranch_execz BB12_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 ; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5
; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo ; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s6, s3, s5 ; GFX1032-NEXT: s_mul_i32 s6, s3, s5
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; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB12_2: ; GFX1032-NEXT: BB12_2:
; GFX1032-NEXT: v_nop ; GFX1032-NEXT: v_nop
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v0
; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v0
; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 ; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
; GFX1032-NEXT: v_readfirstlane_b32 s5, v2 ; GFX1032-NEXT: v_readfirstlane_b32 s4, v2
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3 ; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3
; GFX1032-NEXT: v_sub_co_u32_e64 v0, vcc_lo, s4, v0 ; GFX1032-NEXT: v_sub_co_u32_e64 v0, vcc_lo, s2, v0
; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%old = atomicrmw sub i64 addrspace(3)* @local_var64, i64 %subitive acq_rel %old = atomicrmw sub i64 addrspace(3)* @local_var64, i64 %subitive acq_rel
store i64 %old, i64 addrspace(1)* %out store i64 %old, i64 addrspace(1)* %out
ret void ret void
} }
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; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] ; GFX1064-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB18_2: ; GFX1064-NEXT: BB18_2:
; GFX1064-NEXT: v_nop ; GFX1064-NEXT: v_nop
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX1064-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: max_i64_constant: ; GFX1032-LABEL: max_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
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; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] ; GFX1032-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB18_2: ; GFX1032-NEXT: BB18_2:
; GFX1032-NEXT: v_nop ; GFX1032-NEXT: v_nop
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo
; GFX1032-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%old = atomicrmw max i64 addrspace(3)* @local_var64, i64 5 acq_rel %old = atomicrmw max i64 addrspace(3)* @local_var64, i64 5 acq_rel
store i64 %old, i64 addrspace(1)* %out store i64 %old, i64 addrspace(1)* %out
ret void ret void
} }
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; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] ; GFX1064-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB20_2: ; GFX1064-NEXT: BB20_2:
; GFX1064-NEXT: v_nop ; GFX1064-NEXT: v_nop
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX1064-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: min_i64_constant: ; GFX1032-LABEL: min_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
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; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] ; GFX1032-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB20_2: ; GFX1032-NEXT: BB20_2:
; GFX1032-NEXT: v_nop ; GFX1032-NEXT: v_nop
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo
; GFX1032-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[4:5], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%old = atomicrmw min i64 addrspace(3)* @local_var64, i64 5 acq_rel %old = atomicrmw min i64 addrspace(3)* @local_var64, i64 5 acq_rel
store i64 %old, i64 addrspace(1)* %out store i64 %old, i64 addrspace(1)* %out
ret void ret void
} }
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; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] ; GFX1064-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB22_2: ; GFX1064-NEXT: BB22_2:
; GFX1064-NEXT: v_nop ; GFX1064-NEXT: v_nop
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX1064-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, s3, vcc
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, s5, vcc
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: umax_i64_constant: ; GFX1032-LABEL: umax_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
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; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] ; GFX1032-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB22_2: ; GFX1032-NEXT: BB22_2:
; GFX1032-NEXT: v_nop ; GFX1032-NEXT: v_nop
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo
; GFX1032-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, s3, vcc_lo
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, s5, vcc_lo
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%old = atomicrmw umax i64 addrspace(3)* @local_var64, i64 5 acq_rel %old = atomicrmw umax i64 addrspace(3)* @local_var64, i64 5 acq_rel
store i64 %old, i64 addrspace(1)* %out store i64 %old, i64 addrspace(1)* %out
ret void ret void
} }
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; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] ; GFX1064-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB24_2: ; GFX1064-NEXT: BB24_2:
; GFX1064-NEXT: v_nop ; GFX1064-NEXT: v_nop
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX1064-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: umin_i64_constant: ; GFX1032-LABEL: umin_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
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; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] ; GFX1032-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB24_2: ; GFX1032-NEXT: BB24_2:
; GFX1032-NEXT: v_nop ; GFX1032-NEXT: v_nop
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo
; GFX1032-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%old = atomicrmw umin i64 addrspace(3)* @local_var64, i64 5 acq_rel %old = atomicrmw umin i64 addrspace(3)* @local_var64, i64 5 acq_rel
store i64 %old, i64 addrspace(1)* %out store i64 %old, i64 addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/cc-update.ll

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; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX1010-LABEL: test_kern_stack: ; GFX1010-LABEL: test_kern_stack:
; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: ; implicit-def: $vcc_hi ; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: s_endpgm
entry: entry:
%x = alloca i32, align 4, addrspace(5) %x = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %x, align 4 store volatile i32 0, i32 addrspace(5)* %x, align 4
ret void ret void
} }
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; ;
; GFX1010-LABEL: test_kern_stack_and_call: ; GFX1010-LABEL: test_kern_stack_and_call:
; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_movk_i32 s32, 0x200 ; GFX1010-NEXT: s_movk_i32 s32, 0x200
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5] ; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+4 ; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+4
; GFX1010-NEXT: ; implicit-def: $vcc_hi ; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: s_endpgm
entry: entry:
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; ;
; GFX1010-LABEL: test_force_fp_kern_stack: ; GFX1010-LABEL: test_force_fp_kern_stack:
; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_mov_b32 s33, 0 ; GFX1010-NEXT: s_mov_b32 s33, 0
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: ; implicit-def: $vcc_hi ; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: s_endpgm
entry: entry:
%x = alloca i32, align 4, addrspace(5) %x = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %x, align 4 store volatile i32 0, i32 addrspace(5)* %x, align 4
ret void ret void
} }
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; GFX1010-LABEL: test_force_fp_kern_stack_and_call: ; GFX1010-LABEL: test_force_fp_kern_stack_and_call:
; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_movk_i32 s32, 0x200 ; GFX1010-NEXT: s_movk_i32 s32, 0x200
; GFX1010-NEXT: s_mov_b32 s33, 0 ; GFX1010-NEXT: s_mov_b32 s33, 0
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5] ; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+4 ; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+4
; GFX1010-NEXT: ; implicit-def: $vcc_hi ; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: s_endpgm
entry: entry:
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; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: s_mov_b32 s6, 0x20000 ; GFX1010-NEXT: s_mov_b32 s6, 0x20000
; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 ; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8
; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: s_waitcnt vmcnt(0) ; GFX1010-NEXT: s_waitcnt vmcnt(0)
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX1010-NEXT: v_nop ; GFX1010-NEXT: v_nop
; GFX1010-NEXT: s_mov_b32 s6, 0x20000 ; GFX1010-NEXT: s_mov_b32 s6, 0x20000
; GFX1010-NEXT: ;;#ASMSTART ; GFX1010-NEXT: ;;#ASMSTART
; GFX1010-NEXT: ;;#ASMEND ; GFX1010-NEXT: ;;#ASMEND
; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], s6 ; 4-byte Folded Reload ; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], s6 ; 4-byte Folded Reload
; GFX1010-NEXT: s_waitcnt vmcnt(0) ; GFX1010-NEXT: s_waitcnt vmcnt(0)
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llvm/test/CodeGen/AMDGPU/idot2.ll

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; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX10-DL-NEXT: s_mov_b32 s4, 0xffff ; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s5, s[0:1], 0x0 ; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s6, s2, s4 ; GFX10-DL-NEXT: s_and_b32 s6, s2, s5
; GFX10-DL-NEXT: s_and_b32 s4, s3, s4 ; GFX10-DL-NEXT: s_and_b32 s5, s3, s5
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16 ; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16
; GFX10-DL-NEXT: v_mul_u32_u24_e64 v0, s5, s6
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 16 ; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 16
; GFX10-DL-NEXT: v_mul_u32_u24_e64 v0, s4, s6
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, s5, v0 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, s4, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: idot2_MixedTypedMul: ; GFX10-DL-LABEL: idot2_MixedTypedMul:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_lshr_b32 s5, s2, 16 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_lshr_b32 s6, s3, 16 ; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16
; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 16
; GFX10-DL-NEXT: s_sext_i32_i16 s0, s0
; GFX10-DL-NEXT: s_sext_i32_i16 s1, s1
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s1, s0, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_sext_i32_i16 s2, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: s_sext_i32_i16 s3, s3
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s3, s2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
%vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2 %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: idot2_MixedExt: ; GFX10-DL-LABEL: idot2_MixedExt:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_ashr_i32 s5, s2, 16 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_ashr_i32 s6, s3, 16 ; GFX10-DL-NEXT: s_ashr_i32 s2, s0, 16
; GFX10-DL-NEXT: s_ashr_i32 s3, s1, 16
; GFX10-DL-NEXT: s_sext_i32_i16 s0, s0
; GFX10-DL-NEXT: s_and_b32 s1, s1, 0xffff
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s1, s0, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_sext_i32_i16 s2, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s3, s2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
%vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2 %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
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; GFX10-DL-LABEL: notudot2_SameVec: ; GFX10-DL-LABEL: notudot2_SameVec:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s3, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16 ; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16
; GFX10-DL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s2, s3
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s2, s4 ; GFX10-DL-NEXT: s_and_b32 s2, s4, 0xffff
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s3, v0 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: notudot2_v4i16_Even: ; GFX10-DL-LABEL: notudot2_v4i16_Even:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: s_mov_b32 s7, 0xffff
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s6, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-DL-NEXT: s_mov_b32 s7, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s3, s3, s7
; GFX10-DL-NEXT: s_and_b32 s5, s5, s7
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_and_b32 s2, s2, s7 ; GFX10-DL-NEXT: s_and_b32 s1, s1, s7
; GFX10-DL-NEXT: s_and_b32 s4, s4, s7 ; GFX10-DL-NEXT: s_and_b32 s3, s3, s7
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s3, v0 ; GFX10-DL-NEXT: s_and_b32 s0, s0, s7
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s2, v0 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: s_and_b32 s1, s2, s7
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<4 x i16> addrspace(1)* %src2, <4 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <4 x i16>, <4 x i16> addrspace(1)* %src1 %vec1 = load <4 x i16>, <4 x i16> addrspace(1)* %src1
%vec2 = load <4 x i16>, <4 x i16> addrspace(1)* %src2 %vec2 = load <4 x i16>, <4 x i16> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: notudot2_v4i16_Middle: ; GFX10-DL-LABEL: notudot2_v4i16_Middle:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: s_mov_b32 s7, 0xffff
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s6, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-DL-NEXT: s_mov_b32 s7, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s3, s3, s7
; GFX10-DL-NEXT: s_and_b32 s5, s5, s7
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16 ; GFX10-DL-NEXT: s_and_b32 s1, s1, s7
; GFX10-DL-NEXT: s_lshr_b32 s4, s4, 16 ; GFX10-DL-NEXT: s_and_b32 s3, s3, s7
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s3, v0 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s2, v0 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: s_lshr_b32 s1, s2, 16
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<4 x i16> addrspace(1)* %src2, <4 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <4 x i16>, <4 x i16> addrspace(1)* %src1 %vec1 = load <4 x i16>, <4 x i16> addrspace(1)* %src1
%vec2 = load <4 x i16>, <4 x i16> addrspace(1)* %src2 %vec2 = load <4 x i16>, <4 x i16> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: notudot2_DiffIndex: ; GFX10-DL-LABEL: notudot2_DiffIndex:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff ; GFX10-DL-NEXT: s_mov_b32 s2, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_lshr_b32 s6, s2, 16 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_and_b32 s7, s3, s5 ; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-DL-NEXT: s_and_b32 s6, s1, s2
; GFX10-DL-NEXT: s_and_b32 s0, s0, s2
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 16
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s3, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_and_b32 s2, s2, s5 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 16
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s7, s6, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
%vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2 %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot2_MultipleUses_add1: ; GFX10-DL-LABEL: udot2_MultipleUses_add1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_lshr_b32 s6, s2, 16 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_lshr_b32 s7, s3, 16 ; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 16
; GFX10-DL-NEXT: s_and_b32 s2, s2, s5 ; GFX10-DL-NEXT: s_mov_b32 s6, 0xffff
; GFX10-DL-NEXT: s_and_b32 s3, s3, s5 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s7, s6, v0 ; GFX10-DL-NEXT: s_and_b32 s0, s0, s6
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s3, s2, v0 ; GFX10-DL-NEXT: s_and_b32 s1, s1, s6
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s1, s0, v0
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
%vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2 %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: idot2_MultipleUses_add1: ; GFX10-DL-LABEL: idot2_MultipleUses_add1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_ashr_i32 s5, s2, 16 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_ashr_i32 s6, s3, 16 ; GFX10-DL-NEXT: s_ashr_i32 s2, s0, 16
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: s_ashr_i32 s3, s1, 16
; GFX10-DL-NEXT: s_sext_i32_i16 s2, s2 ; GFX10-DL-NEXT: s_sext_i32_i16 s0, s0
; GFX10-DL-NEXT: s_sext_i32_i16 s3, s3 ; GFX10-DL-NEXT: s_sext_i32_i16 s1, s1
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s3, s2, v0 ; GFX10-DL-NEXT: v_mad_i32_i24 v1, s1, s0, v0
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
%vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2 %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot2_MultipleUses_mul1: ; GFX10-DL-LABEL: udot2_MultipleUses_mul1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff ; GFX10-DL-NEXT: s_mov_b32 s2, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s6, s2, s5 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_and_b32 s5, s3, s5 ; GFX10-DL-NEXT: s_and_b32 s3, s0, s2
; GFX10-DL-NEXT: s_and_b32 s2, s1, s2
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 16
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s1, s0, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 16
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s6, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s5, s6, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
%vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2 %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: idot2_MultipleUses_mul1: ; GFX10-DL-LABEL: idot2_MultipleUses_mul1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_sext_i32_i16 s5, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_sext_i32_i16 s6, s3 ; GFX10-DL-NEXT: s_sext_i32_i16 s2, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: s_sext_i32_i16 s3, s1
; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 16 ; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 16
; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 16 ; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 16
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s6, s5, v0 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, s1, s0, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s3, s2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
%vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2 %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot2_MultipleUses_mul2: ; GFX10-DL-LABEL: udot2_MultipleUses_mul2:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_lshr_b32 s5, s2, 16 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_lshr_b32 s6, s3, 16 ; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16
; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 16
; GFX10-DL-NEXT: s_mov_b32 s6, 0xffff
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: s_and_b32 s0, s0, s6
; GFX10-DL-NEXT: s_and_b32 s1, s1, s6
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_mov_b32 s4, 0xffff ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0
; GFX10-DL-NEXT: s_and_b32 s2, s2, s4
; GFX10-DL-NEXT: s_and_b32 s3, s3, s4
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
%vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2 %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: idot2_MultipleUses_mul2: ; GFX10-DL-LABEL: idot2_MultipleUses_mul2:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_ashr_i32 s5, s2, 16 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_ashr_i32 s6, s3, 16 ; GFX10-DL-NEXT: s_ashr_i32 s2, s0, 16
; GFX10-DL-NEXT: s_ashr_i32 s3, s1, 16
; GFX10-DL-NEXT: s_sext_i32_i16 s0, s0
; GFX10-DL-NEXT: s_sext_i32_i16 s1, s1
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s1, s0, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_sext_i32_i16 s2, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: s_sext_i32_i16 s3, s3
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s3, s2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<2 x i16> addrspace(1)* %src2, <2 x i16> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1 %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
%vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2 %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
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llvm/test/CodeGen/AMDGPU/idot4s.ll

Show First 20 Lines • Show All 637 Lines • ▼ Show 20 Lines
; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: idot4_multiuse_mul1: ; GFX10-DL-LABEL: idot4_multiuse_mul1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_sext_i32_i8 s5, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_sext_i32_i8 s6, s3 ; GFX10-DL-NEXT: s_sext_i32_i8 s2, s0
; GFX10-DL-NEXT: s_sext_i32_i8 s3, s1
; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_i32 s7, s1, 0x80008
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s7, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 24
; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80008 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x80008
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s5, s6, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s7, v0
; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80010
; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x80010
; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 24
; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s5, s6, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s7, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2, <4 x i8> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1
%vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2
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; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v0, 8, s2 ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v0, 8, s2
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v1, 8, s3 ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v1, 8, s3
; GFX10-DL-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v2, s4
; GFX10-DL-NEXT: s_sext_i32_i8 s5, s2 ; GFX10-DL-NEXT: s_sext_i32_i8 s4, s2
; GFX10-DL-NEXT: s_sext_i32_i8 s6, s3 ; GFX10-DL-NEXT: s_sext_i32_i8 s5, s3
; GFX10-DL-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-DL-NEXT: v_bfe_i32 v1, v1, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2
; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80010 ; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80010
; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s5, s6, v2
; GFX10-DL-NEXT: s_bfe_i32 s5, s3, 0x80010 ; GFX10-DL-NEXT: s_bfe_i32 s5, s3, 0x80010
; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 24
; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 24 ; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v0, v0, v1, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, v0, v1, v2
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s5, v0 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s5, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v0 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
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; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ushort v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ushort v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x80000
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x80000
; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16 ; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 8, s0 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 8, s0
; GFX10-DL-NEXT: s_lshr_b32 s5, s1, 16 ; GFX10-DL-NEXT: s_bfe_i32 s0, s0, 0x80000
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x80000
; GFX10-DL-NEXT: v_and_b32_e32 v7, s0, v3
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 8, s1 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 8, s1
; GFX10-DL-NEXT: v_and_b32_e32 v6, s3, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v6, s3, v3
; GFX10-DL-NEXT: v_and_b32_e32 v7, s4, v3 ; GFX10-DL-NEXT: s_lshr_b32 s0, s1, 16
; GFX10-DL-NEXT: s_bfe_i32 s0, s2, 0x80000 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v8, 8, s2
; GFX10-DL-NEXT: s_bfe_i32 s1, s5, 0x80000
; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6
; GFX10-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v7 ; GFX10-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v7
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v6, 8, s2 ; GFX10-DL-NEXT: s_bfe_i32 s1, s2, 0x80000
; GFX10-DL-NEXT: v_and_b32_e32 v8, s1, v3 ; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6
; GFX10-DL-NEXT: v_and_b32_e32 v3, s0, v3 ; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x80000
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 8, s5 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v6, 8, s0
; GFX10-DL-NEXT: v_and_b32_e32 v7, s2, v3
; GFX10-DL-NEXT: v_and_b32_e32 v3, s1, v3
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5
; GFX10-DL-NEXT: v_lshl_or_b32 v3, v6, 16, v3 ; GFX10-DL-NEXT: v_lshl_or_b32 v5, v6, 16, v7
; GFX10-DL-NEXT: v_lshl_or_b32 v5, v7, 16, v8 ; GFX10-DL-NEXT: v_lshl_or_b32 v3, v8, 16, v3
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v5 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v5
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v4, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v4, v2
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: global_store_short v[0:1], v2, off ; GFX10-DL-NEXT: global_store_short v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
Show All 24 Lines

llvm/test/CodeGen/AMDGPU/idot4u.ll

Show First 20 Lines • Show All 617 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[2:3], 0x0
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_movk_i32 s1, 0xff ; GFX10-DL-NEXT: s_movk_i32 s1, 0xff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s3, s2, s1 ; GFX10-DL-NEXT: s_and_b32 s3, s2, s1
; GFX10-DL-NEXT: s_and_b32 s1, s0, s1 ; GFX10-DL-NEXT: s_and_b32 s1, s0, s1
; GFX10-DL-NEXT: s_bfe_u32 s2, s2, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s0, s0, 0x80008 ; GFX10-DL-NEXT: s_bfe_u32 s0, s0, 0x80008
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s2, v2 ; GFX10-DL-NEXT: s_bfe_u32 s1, s2, 0x80008
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2, <4 x i8> addrspace(1)* %src2,
i8 addrspace(1)* nocapture %dst) { i8 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1
%vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1
; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 ; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2
; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot4_CommutationAccrossMADs: ; GFX10-DL-LABEL: udot4_CommutationAccrossMADs:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: s_movk_i32 s4, 0xff
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_movk_i32 s2, 0xff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x80008 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x80008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008
; GFX10-DL-NEXT: s_and_b32 s5, s0, s2
; GFX10-DL-NEXT: s_and_b32 s2, s1, s2
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v2
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x80010 ; GFX10-DL-NEXT: s_and_b32 s2, s0, s4
; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x80010 ; GFX10-DL-NEXT: s_and_b32 s3, s1, s4
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v2
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2, <4 x i8> addrspace(1)* %src2,
i8 addrspace(1)* nocapture %dst) { i8 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1
%vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot4_multiuse_mul1: ; GFX10-DL-LABEL: udot4_multiuse_mul1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_movk_i32 s5, 0xff ; GFX10-DL-NEXT: s_movk_i32 s2, 0xff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s6, s2, s5 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_and_b32 s5, s3, s5 ; GFX10-DL-NEXT: s_and_b32 s3, s0, s2
; GFX10-DL-NEXT: s_and_b32 s2, s1, s2
; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x80008
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s7, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80008 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80008
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s7, v0
; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s7, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2, <4 x i8> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1
%vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot4_multiuse_add1: ; GFX10-DL-LABEL: udot4_multiuse_add1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: s_movk_i32 s7, 0xff
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_movk_i32 s5, 0xff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_u32 s6, s2, 0x80008 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80008 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008
; GFX10-DL-NEXT: s_and_b32 s8, s2, s5 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0
; GFX10-DL-NEXT: s_and_b32 s5, s3, s5 ; GFX10-DL-NEXT: s_and_b32 s2, s0, s7
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s7, v0 ; GFX10-DL-NEXT: s_and_b32 s3, s1, s7
; GFX10-DL-NEXT: s_bfe_u32 s6, s2, 0x80010 ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s2, s3, v0
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80010 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s8, s5, v0 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_add_nc_u32_e32 v0, s4, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s2, s3, v1 ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s2, s3, v1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v0, s6, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s0, s1, v1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2, <4 x i8> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1
%vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2
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; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ushort v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ushort v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008
; GFX10-DL-NEXT: s_sext_i32_i8 s4, s0
; GFX10-DL-NEXT: s_sext_i32_i8 s5, s1
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_sext_i32_i8 s2, s0
; GFX10-DL-NEXT: s_sext_i32_i8 s3, s1
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2
; GFX10-DL-NEXT: global_store_short v[0:1], v2, off ; GFX10-DL-NEXT: global_store_short v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2, <4 x i8> addrspace(1)* %src2,
i16 addrspace(1)* nocapture %dst) { i16 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX10-DL-NEXT: s_movk_i32 s5, 0xff ; GFX10-DL-NEXT: s_movk_i32 s6, 0xff
; GFX10-DL-NEXT: s_mov_b32 s6, 0xffff ; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3
; GFX10-DL-NEXT: s_and_b32 s7, s2, s5
; GFX10-DL-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-DL-NEXT: v_mov_b32_e32 v2, s4
; GFX10-DL-NEXT: s_and_b32 s5, s3, s5 ; GFX10-DL-NEXT: s_and_b32 s4, s2, s6
; GFX10-DL-NEXT: v_and_b32_sdwa v0, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 ; GFX10-DL-NEXT: s_and_b32 s6, s3, s6
; GFX10-DL-NEXT: v_and_b32_sdwa v1, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 ; GFX10-DL-NEXT: v_and_b32_sdwa v0, s5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-DL-NEXT: v_and_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s6, v2
; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80010 ; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s7, s5, v2
; GFX10-DL-NEXT: s_bfe_u32 s5, s3, 0x80010 ; GFX10-DL-NEXT: s_bfe_u32 s5, s3, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24 ; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v1, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v1, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s5, v0 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s5, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v0 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
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; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v4, 8, s0 ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v4, 8, s0
; GFX10-DL-NEXT: v_and_b32_sdwa v7, v3, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_and_b32_sdwa v7, v3, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v5, 8, s1 ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v5, 8, s1
; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16 ; GFX10-DL-NEXT: s_lshr_b32 s2, s1, 16
; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 16 ; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v7 ; GFX10-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v7
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6
; GFX10-DL-NEXT: v_and_b32_sdwa v3, v3, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: v_and_b32_sdwa v3, v3, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5
; GFX10-DL-NEXT: v_lshl_or_b32 v5, s1, 16, v6 ; GFX10-DL-NEXT: v_lshl_or_b32 v5, s1, 16, v6
; GFX10-DL-NEXT: v_lshl_or_b32 v3, s0, 16, v3 ; GFX10-DL-NEXT: v_lshl_or_b32 v3, s0, 16, v3
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v5 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v5
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v4, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v4, v2
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3
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; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v3, 8, s0 ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v3, 8, s0
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v4, 8, s1 ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v4, 8, s1
; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 24 ; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 24
; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 24 ; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 24
; GFX10-DL-NEXT: s_lshr_b32 s4, s0, 16 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s2, s3
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, v3, v4 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, v3, v4
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, s0, s1 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, s0, s1
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s2, s3 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-DL-NEXT: s_lshr_b32 s0, s1, 16 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 16
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v3 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v3
; GFX10-DL-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 8, v5 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 8, v5
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s4, s0 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s0, s1
; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xffff, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX10-DL-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4 ; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v5 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v5
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
Show All 24 Lines

llvm/test/CodeGen/AMDGPU/idot8s.ll

Show First 20 Lines • Show All 481 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 12 ; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 12
; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 12 ; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 12
; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40000 ; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40000
; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40000 ; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40000
; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x40004
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s2 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s2
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s3 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s3
; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_i32 s7, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_i32 s7, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_i32 s8, s1, 0x40008 ; GFX10-DL-NEXT: s_bfe_i32 s8, s1, 0x40008
; GFX10-DL-NEXT: s_bfe_i32 s2, s1, 0x40004 ; GFX10-DL-NEXT: s_bfe_i32 s2, s1, 0x40004
; GFX10-DL-NEXT: v_mul_i32_i24_e64 v5, s7, s8
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v3, 12, v3 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v3, 12, v3
; GFX10-DL-NEXT: s_mov_b32 s3, 0xffff
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4
; GFX10-DL-NEXT: v_mul_i32_i24_e64 v5, s7, s8
; GFX10-DL-NEXT: v_and_b32_e32 v3, s3, v3
; GFX10-DL-NEXT: v_and_b32_e32 v4, s3, v4
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40010
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2
; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40014
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s6, s2, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s6, s2, v2
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_mov_b32 s2, 0xffff
; GFX10-DL-NEXT: v_and_b32_e32 v3, s2, v3
; GFX10-DL-NEXT: v_and_b32_e32 v4, s2, v4
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010
; GFX10-DL-NEXT: v_mad_u32_u24 v2, v3, v4, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, v3, v4, v2
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40014
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40018
; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 28 ; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 28
; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 28 ; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 28
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v2
; GFX10-DL-NEXT: global_store_short v[0:1], v2, off ; GFX10-DL-NEXT: global_store_short v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i16 addrspace(1)* nocapture %dst) { i16 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1
▲ Show 20 Lines • Show All 301 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 12 ; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 12
; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 12 ; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 12
; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40000 ; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40000
; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40000 ; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40000
; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x40004
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s2 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s2
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s3 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s3
; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_i32 s7, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_i32 s7, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_i32 s8, s1, 0x40008 ; GFX10-DL-NEXT: s_bfe_i32 s8, s1, 0x40008
; GFX10-DL-NEXT: s_bfe_i32 s2, s1, 0x40004 ; GFX10-DL-NEXT: s_bfe_i32 s2, s1, 0x40004
; GFX10-DL-NEXT: v_mul_i32_i24_e64 v5, s7, s8
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v3, 12, v3 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v3, 12, v3
; GFX10-DL-NEXT: s_movk_i32 s3, 0xff
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4
; GFX10-DL-NEXT: v_mul_i32_i24_e64 v5, s7, s8
; GFX10-DL-NEXT: v_and_b32_e32 v3, s3, v3
; GFX10-DL-NEXT: v_and_b32_e32 v4, s3, v4
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40010
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2
; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40014
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s6, s2, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s6, s2, v2
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_movk_i32 s2, 0xff
; GFX10-DL-NEXT: v_and_b32_e32 v3, s2, v3
; GFX10-DL-NEXT: v_and_b32_e32 v4, s2, v4
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010
; GFX10-DL-NEXT: v_mad_u32_u24 v2, v3, v4, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, v3, v4, v2
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40014
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40018
; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 28 ; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 28
; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 28 ; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 28
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v2
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i8 addrspace(1)* nocapture %dst) { i8 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: idot8_multiuses_mul1: ; GFX10-DL-LABEL: idot8_multiuses_mul1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_i32 s5, s2, 0x40000 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_bfe_i32 s6, s3, 0x40000 ; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40000
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40000
; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x40004 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0
; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x40004 ; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s5, s6, v0 ; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40004
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s5, s6, v0 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40004
; GFX10-DL-NEXT: s_bfe_i32 s5, s2, 0x40008 ; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1
; GFX10-DL-NEXT: s_bfe_i32 s6, s3, 0x40008 ; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40008
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s4, s7, v1 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40008
; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x4000c
; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x4000c
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s5, s6, v1
; GFX10-DL-NEXT: s_bfe_i32 s5, s2, 0x40010
; GFX10-DL-NEXT: s_bfe_i32 s6, s3, 0x40010
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s4, s7, v1
; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x40014
; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x40014
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s5, s6, v1
; GFX10-DL-NEXT: s_bfe_i32 s5, s2, 0x40018
; GFX10-DL-NEXT: s_bfe_i32 s6, s3, 0x40018
; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 28
; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 28
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s4, s7, v1
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s5, s6, v1
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1 ; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x4000c
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x4000c
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40010
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40014
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40018
; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 28
; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 28
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1
; GFX10-DL-NEXT: v_mad_i32_i24 v1, s0, s1, v1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v0, v1 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v0, v1
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1
%vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2
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; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ushort v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ushort v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s4, s0, 15
; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40004
; GFX10-DL-NEXT: s_and_b32 s6, s1, 15
; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 28
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s5 ; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s8, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40014
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s6, s6, s7 ; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s9, s0, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s7, s0, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40008 ; GFX10-DL-NEXT: s_and_b32 s8, s0, 15
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v3, 12, s4 op_sel_hi:[0,1] ; GFX10-DL-NEXT: s_bfe_u32 s0, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s0, s0, 0x4000c ; GFX10-DL-NEXT: s_and_b32 s9, s1, 15
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v4, 12, s6 op_sel_hi:[0,1] ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s8, s0
; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s8, s1, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x4000c ; GFX10-DL-NEXT: v_pk_lshlrev_b16 v3, 12, s0 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s9, s8
; GFX10-DL-NEXT: s_bfe_u32 s9, s1, 0x4000c
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v4, 12, s0 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_bfe_u32 s0, s1, 0x40008
; GFX10-DL-NEXT: v_pk_ashrrev_i16 v3, 12, v3 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v3, 12, v3 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s5, s0 ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s6, s6, s7
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s0, s9
; GFX10-DL-NEXT: v_pk_ashrrev_i16 v4, 12, v4 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v4, 12, v4 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40010 ; GFX10-DL-NEXT: v_pk_lshlrev_b16 v5, 12, s6 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s7, s4 ; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s0 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40010
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v5, 12, s0 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_bfe_u32 s0, s1, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s0, s1, 0x40014
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v4 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v4
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s4 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s8, s9
; GFX10-DL-NEXT: v_pk_ashrrev_i16 v4, 12, v5 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v4, 12, v5 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s5, s0
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28
; GFX10-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v6 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v6 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s5
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s6, s0
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s4 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s4 op_sel_hi:[0,1]
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v7, 12, s0 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_lshlrev_b16 v7, 12, s0 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s2, s3
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s1, s6, s1 ; GFX10-DL-NEXT: s_bfe_u32 s8, s1, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s0, s1, 28
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s1, s2, s3
; GFX10-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v7 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v7 op_sel_hi:[0,1]
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v7, 12, s1 op_sel_hi:[0,1] ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s8, s0
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v7, 12, s0 op_sel_hi:[0,1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: v_pk_ashrrev_i16 v3, 12, v6 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v3, 12, v6 op_sel_hi:[0,1]
; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s0 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s1 op_sel_hi:[0,1]
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v5 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v5
; GFX10-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v7 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v7 op_sel_hi:[0,1]
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: v_pk_ashrrev_i16 v4, 12, v6 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v4, 12, v6 op_sel_hi:[0,1]
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
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; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_mov_b32 s2, 0xffff ; GFX10-DL-NEXT: s_mov_b32 s2, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_lshr_b32 s7, s0, 4 ; GFX10-DL-NEXT: s_lshr_b32 s7, s0, 4
; GFX10-DL-NEXT: s_lshr_b32 s14, s1, 4 ; GFX10-DL-NEXT: s_lshr_b32 s14, s1, 4
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s7
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s14
; GFX10-DL-NEXT: s_lshr_b32 s8, s0, 12 ; GFX10-DL-NEXT: s_lshr_b32 s8, s0, 12
; GFX10-DL-NEXT: s_lshr_b32 s15, s1, 12 ; GFX10-DL-NEXT: s_lshr_b32 s15, s1, 12
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s0 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s0
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s7
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s14
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s1 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s1
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v14, 12, s15 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v14, 12, s15
; GFX10-DL-NEXT: s_lshr_b32 s9, s0, 8
; GFX10-DL-NEXT: s_lshr_b32 s16, s1, 8
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v6, 12, s8 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v6, 12, s8
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 12, v7 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 12, v7
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v12 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v13, 12, v13
; GFX10-DL-NEXT: s_lshr_b32 s9, s0, 8
; GFX10-DL-NEXT: s_lshr_b32 s16, s1, 8
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s9 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s9
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s16
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v3, 12, v3 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v3, 12, v3
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s16
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, v7, v12
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v19, 12, v6 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v19, 12, v6
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, v7, v13
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v14, 12, v14 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v14, 12, v14
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 12, v5
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v12
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, v3, v4
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v6, 8, v7
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, v19, v14
; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 20 ; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 20
; GFX10-DL-NEXT: s_lshr_b32 s4, s0, 16 ; GFX10-DL-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-DL-NEXT: s_lshr_b32 s5, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s5, s0, 28
; GFX10-DL-NEXT: s_lshr_b32 s6, s0, 24 ; GFX10-DL-NEXT: s_lshr_b32 s6, s0, 24
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, v3, v4
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, v19, v14
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v6, 8, v7
; GFX10-DL-NEXT: s_lshr_b32 s10, s1, 20 ; GFX10-DL-NEXT: s_lshr_b32 s10, s1, 20
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v13
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 12, v5
; GFX10-DL-NEXT: s_lshr_b32 s11, s1, 16
; GFX10-DL-NEXT: v_or_b32_sdwa v3, v3, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_or_b32_sdwa v3, v3, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NEXT: s_lshr_b32 s12, s1, 28
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v8, 12, s6 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v8, 12, s6
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s5 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s5
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s4 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s4
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v11, 12, s3 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v11, 12, s3
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s10 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s10
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v5, v12 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v5, v12
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 8, v4 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 8, v4
; GFX10-DL-NEXT: s_lshr_b32 s11, s1, 16
; GFX10-DL-NEXT: s_lshr_b32 s12, s1, 28
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s11 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s11
; GFX10-DL-NEXT: s_lshr_b32 s13, s1, 24
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v6, 12, v8 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v6, 12, v8
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v8, 12, v9 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v8, 12, v9
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v9, 12, v10 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v9, 12, v10
; GFX10-DL-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_and_b32_e32 v3, s2, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v3, s2, v3
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v16, 12, s12 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v16, 12, s12
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 12, v11 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 12, v11
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v10, 12, v13 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v10, 12, v13
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s13 ; GFX10-DL-NEXT: s_lshr_b32 s13, s1, 24
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 12, v7 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 12, v7
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s13
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v11, 12, v16 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v11, 12, v16
; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v5, v10 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v5, v10
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v15 ; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v10, v9, v7 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v10, v9, v7
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v15
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v8, v8, v11 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v8, v8, v11
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v9, 8, v4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v9, 8, v4
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v5 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v5
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v6, v12 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v6, v12
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v6, 8, v8 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v6, 8, v8
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v9 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v9
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llvm/test/CodeGen/AMDGPU/idot8u.ll

Show First 20 Lines • Show All 453 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ushort v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ushort v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15
; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40008
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c
; GFX10-DL-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x4000c
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2
; GFX10-DL-NEXT: global_store_short v[0:1], v2, off ; GFX10-DL-NEXT: global_store_short v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i16 addrspace(1)* nocapture %dst) { i16 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1
▲ Show 20 Lines • Show All 265 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15
; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40008
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c
; GFX10-DL-NEXT: v_and_b32_e32 v2, 0xff, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x4000c
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i8 addrspace(1)* nocapture %dst) { i8 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1
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; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15
; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40008
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c ; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s5
; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x4000c ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s4, v2
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s6, v2
; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s4
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014
; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2
; GFX10-DL-NEXT: v_and_b32_e32 v3, 15, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 15, v3
; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2
; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i4 addrspace(1)* nocapture %dst) { i4 addrspace(1)* nocapture %dst) {
entry: entry:
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; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15
; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x4000c
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x4000c
; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s2, s3
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s7 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s6, v2
; GFX10-DL-NEXT: v_and_b32_e32 v3, 15, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 15, v3
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010
; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2
; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i4 addrspace(1)* nocapture %dst) { i4 addrspace(1)* nocapture %dst) {
entry: entry:
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; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot8_multiuses_mul1: ; GFX10-DL-LABEL: udot8_multiuses_mul1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s5, s2, 15 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_and_b32 s6, s3, 15 ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15
; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s8, s2, 0x40008 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0
; GFX10-DL-NEXT: s_bfe_u32 s9, s3, 0x40008 ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s6, v0 ; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40008
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s4, s7, v0 ; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x4000c ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x4000c ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s6, v0 ; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x4000c
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s8, s9, v1 ; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s8, s2, 0x40010 ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1
; GFX10-DL-NEXT: s_bfe_u32 s9, s3, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40010
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s4, s7, v1 ; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x40014 ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40014
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s8, s9, v1 ; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s8, s2, 0x40018 ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1
; GFX10-DL-NEXT: s_bfe_u32 s9, s3, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 28 ; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 28 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s4, s7, v1 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s8, s9, v1 ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s2, s3, v1 ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s0, s1, v1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v0, v1 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v0, v1
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i32 addrspace(1)* nocapture %dst) { i32 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1
%vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2
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; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15
; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40004
; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15
; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s7, s0, 0x4000c
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s2, s2, s5 ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s2, s2, s5
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40008
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s3, s3, s4 ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s3, s3, s4
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40008
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, s2, s3 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, s2, s3
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s3, s5, s6 ; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s7 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s5
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s2, s2, s3
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x40014
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, s2, s4
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40014 ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s2, s2, s3
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, s4, s3 ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s5
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s2, s2, s5
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s6, s7
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s3, s0 ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s1, s3, s1
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s1, s5, s1
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, s2, s4 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, s2, s4
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:BYTE_0
; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s2, s0
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, s0, s1 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, s0, s1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v4 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: global_store_short v[0:1], v2, off ; GFX10-DL-NEXT: global_store_short v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
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; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004
; GFX10-DL-NEXT: s_and_b32 s4, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15
; GFX10-DL-NEXT: s_and_b32 s6, s1, 15 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, s3, s5
; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x4000c ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15
; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x4000c ; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x4000c
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, s2, s3 ; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, s2, s3
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, s4, s6 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s6, s5
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40008
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s5, s7
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v3 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v3
; GFX10-DL-NEXT: s_mov_b32 s4, 0xffff ; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s2, s1, 0x40008
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v6, s2, s3 ; GFX10-DL-NEXT: s_mov_b32 s3, 0xffff
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v5, 8, v5 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v6, s4, s2
; GFX10-DL-NEXT: v_or_b32_e32 v3, v4, v3 ; GFX10-DL-NEXT: v_or_b32_e32 v3, v4, v3
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x40014 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v5, 8, v5
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40018 ; GFX10-DL-NEXT: v_and_b32_e32 v3, s3, v3
; GFX10-DL-NEXT: v_or_b32_sdwa v4, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-DL-NEXT: v_or_b32_sdwa v4, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-DL-NEXT: v_and_b32_e32 v3, s4, v3 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s4, s6
; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40018
; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40010
; GFX10-DL-NEXT: s_lshr_b32 s8, s1, 28
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s3, s6
; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4 ; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4
; GFX10-DL-NEXT: s_bfe_u32 s1, s1, 0x40018 ; GFX10-DL-NEXT: s_lshr_b32 s4, s1, 28
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v6, s2, s7 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v6, s2, s7
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, s0, s8 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, s0, s4
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v5, 8, v5
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v4
; GFX10-DL-NEXT: s_bfe_u32 s0, s1, 0x40018
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v10, s5, s0
; GFX10-DL-NEXT: v_or_b32_e32 v5, v6, v5
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 8, v7 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 8, v7
; GFX10-DL-NEXT: v_and_b32_e32 v5, s3, v5
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v5 ; GFX10-DL-NEXT: v_or_b32_sdwa v3, v10, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s5, s1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v8 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v8
; GFX10-DL-NEXT: v_or_b32_e32 v3, v6, v3 ; GFX10-DL-NEXT: v_or_b32_e32 v3, v5, v3
; GFX10-DL-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2
; GFX10-DL-NEXT: v_and_b32_e32 v3, s4, v3
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v5
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v4
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v3
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v5
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i8 addrspace(1)* nocapture %dst) { i8 addrspace(1)* nocapture %dst) {
entry: entry:
%vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1
%vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2
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; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX10-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15
; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c
; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40008
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c ; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s5
; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x4000c ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s4, v2
; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s6, v2
; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s4
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010
; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014
; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2
; GFX10-DL-NEXT: v_and_b32_e32 v3, 15, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 15, v3
; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2
; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
<8 x i4> addrspace(1)* %src2, <8 x i4> addrspace(1)* %src2,
i4 addrspace(1)* nocapture %dst) { i4 addrspace(1)* nocapture %dst) {
entry: entry:
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llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll

Show All 28 Lines
; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_short v[0:1], v1, off ; GFX10-NEXT: global_store_short v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask0: ; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask0:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_short v[0:1], v1, off ; GFX10-NEXT: global_store_short v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask1: ; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask1:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask0: ; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask0:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask1: ; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask1:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask3: ; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask3:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: v_mov_b32_e32 v3, v1 ; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[1:2], off ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[1:2], off
; GFX10-NEXT: global_store_dword v[0:1], v3, off ; GFX10-NEXT: global_store_dword v[0:1], v3, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_v4f16_tfe_dmask15: ; GFX8-UNPACKED-LABEL: load_1d_v4f16_tfe_dmask15:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
Show All 35 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll

Show First 20 Lines • Show All 587 Lines • ▼ Show 20 Lines
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 0) call void @llvm.amdgcn.s.setreg(i32 14337, i32 0)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_1() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_1() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x1 ; GFX10-NEXT: s_round_mode 0x1
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 1) call void @llvm.amdgcn.s.setreg(i32 14337, i32 1)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_2() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_2() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x2 ; GFX10-NEXT: s_round_mode 0x2
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 2) call void @llvm.amdgcn.s.setreg(i32 14337, i32 2)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_4() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_4() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x4 ; GFX10-NEXT: s_round_mode 0x4
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 4) call void @llvm.amdgcn.s.setreg(i32 14337, i32 4)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_8() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_8() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x8 ; GFX10-NEXT: s_round_mode 0x8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 8) call void @llvm.amdgcn.s.setreg(i32 14337, i32 8)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_16() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_16() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 1
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 1
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 16) call void @llvm.amdgcn.s.setreg(i32 14337, i32 16)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_32() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_32() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 2
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 32) call void @llvm.amdgcn.s.setreg(i32 14337, i32 32)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_64() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_64() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 4
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 4
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 64) call void @llvm.amdgcn.s.setreg(i32 14337, i32 64)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_128() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_128() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 8
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 8
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 128) call void @llvm.amdgcn.s.setreg(i32 14337, i32 128)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_15() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_15() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0xf ; GFX10-NEXT: s_round_mode 0xf
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 15) call void @llvm.amdgcn.s.setreg(i32 14337, i32 15)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_255() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_255() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0xf ; GFX10-NEXT: s_round_mode 0xf
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 15
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 15
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 255) call void @llvm.amdgcn.s.setreg(i32 14337, i32 255)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
; Truncate extra high bit ; Truncate extra high bit
define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_597() { define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_597() {
; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597: ; GFX6789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:
; GFX6789: ; %bb.0: ; GFX6789: ; %bb.0:
; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; GFX6789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255
; GFX6789-NEXT: ;;#ASMSTART ; GFX6789-NEXT: ;;#ASMSTART
; GFX6789-NEXT: ;;#ASMEND ; GFX6789-NEXT: ;;#ASMEND
; GFX6789-NEXT: s_endpgm ; GFX6789-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597: ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x5 ; GFX10-NEXT: s_round_mode 0x5
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 5
; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 5
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 597) call void @llvm.amdgcn.s.setreg(i32 14337, i32 597)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
ret void ret void
} }
define amdgpu_kernel void @test_setreg_set_8_bits_straddles_round_and_denorm() { define amdgpu_kernel void @test_setreg_set_8_bits_straddles_round_and_denorm() {
; GFX6789-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm: ; GFX6789-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm:
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llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll

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; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048 ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096 ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off
; ;
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off
entry: entry:
%call = tail call i64 @_Z13get_global_idj(i32 0) %call = tail call i64 @_Z13get_global_idj(i32 0)
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llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir

Show All 19 Lines bb.0:
; GCN: liveins: $sgpr4_sgpr5 ; GCN: liveins: $sgpr4_sgpr5
; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0, 0 :: (dereferenceable invariant load 4, align 16, addrspace 4) ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0, 0 :: (dereferenceable invariant load 4, align 16, addrspace 4)
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GCN: $vcc_hi = IMPLICIT_DEF ; GCN: $vcc_hi = IMPLICIT_DEF
; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store 4, addrspace 3) ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store 4, addrspace 3)
; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
; GCN: $m0 = S_MOV_B32 0
; GCN: $vgpr0 = COPY [[S_LOAD_DWORD_IMM]] ; GCN: $vgpr0 = COPY [[S_LOAD_DWORD_IMM]]
; GCN: $m0 = S_MOV_B32 0
; GCN: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec { ; GCN: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
; GCN: DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4) ; GCN: DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
; GCN: S_WAITCNT 0 ; GCN: S_WAITCNT 0
; GCN: } ; GCN: }
; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_2]], 0, 0, implicit $exec :: (store 4, addrspace 3) ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_2]], 0, 0, implicit $exec :: (store 4, addrspace 3)
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
$vcc_hi = IMPLICIT_DEF $vcc_hi = IMPLICIT_DEF
%2:sgpr_64 = COPY $sgpr4_sgpr5 %2:sgpr_64 = COPY $sgpr4_sgpr5
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llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll

Show All 9 Lines
; into the MUBUF instruction, and so we end up emitting an incorrect offset. ; into the MUBUF instruction, and so we end up emitting an incorrect offset.
; Fixing this may involve adding stack access pseudos so that we don't have to ; Fixing this may involve adding stack access pseudos so that we don't have to
; speculatively refer to the ABI stack pointer register at all. ; speculatively refer to the ABI stack pointer register at all.
; An assert was hit when frame offset register was used to address FrameIndex. ; An assert was hit when frame offset register was used to address FrameIndex.
define amdgpu_kernel void @kernel_background_evaluate(float addrspace(5)* %kg, <4 x i32> addrspace(1)* %input, <4 x float> addrspace(1)* %output, i32 %i) { define amdgpu_kernel void @kernel_background_evaluate(float addrspace(5)* %kg, <4 x i32> addrspace(1)* %input, <4 x float> addrspace(1)* %output, i32 %i) {
; GCN-LABEL: kernel_background_evaluate: ; GCN-LABEL: kernel_background_evaluate:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s6, s[0:1], 0x24 ; GCN-NEXT: s_load_dword s0, s[0:1], 0x24
; GCN-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GCN-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GCN-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GCN-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GCN-NEXT: s_mov_b32 s38, -1 ; GCN-NEXT: s_mov_b32 s38, -1
; GCN-NEXT: s_mov_b32 s39, 0x31c16000 ; GCN-NEXT: s_mov_b32 s39, 0x31c16000
; GCN-NEXT: s_add_u32 s36, s36, s3 ; GCN-NEXT: s_add_u32 s36, s36, s3
; GCN-NEXT: s_addc_u32 s37, s37, 0 ; GCN-NEXT: s_addc_u32 s37, s37, 0
; GCN-NEXT: v_mov_b32_e32 v1, 0x2000 ; GCN-NEXT: v_mov_b32_e32 v1, 0x2000
; GCN-NEXT: v_mov_b32_e32 v2, 0x4000 ; GCN-NEXT: v_mov_b32_e32 v2, 0x4000
; GCN-NEXT: v_mov_b32_e32 v3, 0 ; GCN-NEXT: v_mov_b32_e32 v3, 0
; GCN-NEXT: v_mov_b32_e32 v4, 0x400000 ; GCN-NEXT: v_mov_b32_e32 v4, 0x400000
; GCN-NEXT: s_mov_b64 s[0:1], s[36:37]
; GCN-NEXT: s_mov_b64 s[2:3], s[38:39]
; GCN-NEXT: s_mov_b32 s32, 0xc0000 ; GCN-NEXT: s_mov_b32 s32, 0xc0000
; GCN-NEXT: v_add_nc_u32_e64 v40, 4, 0x4000 ; GCN-NEXT: v_add_nc_u32_e64 v40, 4, 0x4000
; GCN-NEXT: ; implicit-def: $vcc_hi ; GCN-NEXT: ; implicit-def: $vcc_hi
; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4 ; GCN-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+4 ; GCN-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+4
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s6 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b64 s[0:1], s[36:37]
; GCN-NEXT: s_mov_b64 s[2:3], s[38:39]
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GCN-NEXT: s_cbranch_execz BB0_2 ; GCN-NEXT: s_cbranch_execz BB0_2
; GCN-NEXT: ; %bb.1: ; %if.then4.i ; GCN-NEXT: ; %bb.1: ; %if.then4.i
; GCN-NEXT: buffer_load_dword v0, v40, s[36:39], s32 offen ; GCN-NEXT: buffer_load_dword v0, v40, s[36:39], s32 offen
; GCN-NEXT: buffer_load_dword v1, v40, s[36:39], s32 offen offset:4 ; GCN-NEXT: buffer_load_dword v1, v40, s[36:39], s32 offen offset:4
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
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llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll

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; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10: s_getpc_b64 s[4:5] ; GFX10: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+4 ; GFX10-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+4
; GFX10-NEXT: v_mov_b32_e32 v40, v16 ; GFX10-NEXT: v_mov_b32_e32 v40, v16
; GFX10-NEXT: v_mov_b32_e32 v41, v15 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: image_gather4_c_b_cl v[0:3], v[12:19], s[36:43], s[44:47] dmask:0x1 ; GFX10-NEXT: image_gather4_c_b_cl v[0:3], v[12:19], s[36:43], s[44:47] dmask:0x1
; GFX10-NEXT: v_mov_b32_e32 v41, v15
; GFX10-NEXT: v_mov_b32_e32 v42, v14 ; GFX10-NEXT: v_mov_b32_e32 v42, v14
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: v_mov_b32_e32 v43, v13 ; GFX10-NEXT: v_mov_b32_e32 v43, v13
; GFX10-NEXT: v_mov_b32_e32 v44, v12 ; GFX10-NEXT: v_mov_b32_e32 v44, v12
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: image_gather4_c_b_cl v[0:3], [v44, v43, v42, v41, v40], s[36:43], s[44:47] dmask:0x1 ; GFX10-NEXT: image_gather4_c_b_cl v[0:3], [v44, v43, v42, v41, v40], s[36:43], s[44:47] dmask:0x1
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llvm/test/CodeGen/AMDGPU/wave32.ll

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; GCN: s_cbranch_execz ; GCN: s_cbranch_execz
; GCN: ; %bb.{{[0-9]+}}: ; %.preheader ; GCN: ; %bb.{{[0-9]+}}: ; %.preheader
; GCN: BB{{.*}}: ; GCN: BB{{.*}}:
; GFX1032: s_or_b32 [[MASK0:s[0-9]+]], [[MASK0]], vcc_lo ; GFX1032: s_or_b32 [[MASK0:s[0-9]+]], [[MASK0]], vcc_lo
; GFX1064: s_or_b64 [[MASK0:s\[[0-9:]+\]]], [[MASK0]], vcc ; GFX1064: s_or_b64 [[MASK0:s\[[0-9:]+\]]], [[MASK0]], vcc
; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo ; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo
; GFX1064: s_andn2_b64 [[MASK1:s\[[0-9:]+\]]], [[MASK1]], exec ; GFX1064: s_andn2_b64 [[MASK1:s\[[0-9:]+\]]], [[MASK1]], exec
; GCN: global_store_dword
; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo ; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo
; GFX1064: s_and_b64 [[MASK0]], [[MASK0]], exec ; GFX1064: s_and_b64 [[MASK0]], [[MASK0]], exec
; GCN: global_store_dword
; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]] ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]]
; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]] ; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]]
; GCN: BB{{.*}}: ; %Flow ; GCN: BB{{.*}}: ; %Flow
; GFX1032: s_and_b32 [[TMP0:s[0-9]+]], exec_lo, [[MASK1]] ; GFX1032: s_and_b32 [[TMP0:s[0-9]+]], exec_lo, [[MASK1]]
; GFX1064: s_and_b64 [[TMP0:s\[[0-9:]+\]]], exec, [[MASK1]] ; GFX1064: s_and_b64 [[TMP0:s\[[0-9:]+\]]], exec, [[MASK1]]
; GFX1032: s_or_b32 [[ACC:s[0-9]+]], [[TMP0]], [[ACC]] ; GFX1032: s_or_b32 [[ACC:s[0-9]+]], [[TMP0]], [[ACC]]
; GFX1064: s_or_b64 [[ACC:s\[[0-9:]+\]]], [[TMP0]], [[ACC]] ; GFX1064: s_or_b64 [[ACC:s\[[0-9:]+\]]], [[TMP0]], [[ACC]]
; GFX1032: s_andn2_b32 exec_lo, exec_lo, [[ACC]] ; GFX1032: s_andn2_b32 exec_lo, exec_lo, [[ACC]]
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